Abstract: An integrated circuit device incorporating a metallurgical bond to enhance thermal conduction to a heat sink. In a semiconductor device, a surface of an integrated circuit die is metallurgically bonded to a surface of a heat sink. In an exemplary method of manufacturing the device, the upper surface of a package substrate includes an inner region and a peripheral region. The integrated circuit die is positioned over the substrate surface and a first surface of the integrated circuit die is placed in contact with the package substrate. A metallic layer is formed on a second opposing surface of the integrated circuit die. A preform is positioned on the metallic layer and a heat sink is positioned over the preform. A joint layer is formed with the preform, metallurgically bonding the heat sink to the second surface of the integrated circuit die.

Abstract: An integrated heat spreader (IHS) having a groove and a cavity formed therein is disclosed. In one embodiment, the groove has an insulating layer formed therein, and a power conduit is mounted in the groove, the power conduit is electrically isolated from the IHS by the insulating layer, and the power conduit conducts a voltage relative to the IHS to deliver power to the cavity. In another embodiment, the IHS is soldered to a semiconductor die and a package substrate. In a further embodiment, the power conduit comprises an edge connector.

Abstract: An integrated circuit device incorporating a metallurgical bond to enhance thermal conduction to a heat sink. In a semiconductor device, a surface of an integrated circuit die is metallurgically bonded to a surface of a heat sink. In an exemplary method of manufacturing the device, the upper surface of a package substrate includes an inner region and a peripheral region. The integrated circuit die is positioned over the substrate surface and a first surface of the integrated circuit die is placed in contact with the package substrate. A metallic layer is formed on a second opposing surface of the integrated circuit die. A preform is positioned on the metallic layer and a heat sink is positioned over the preform. A joint layer is formed with the preform, metallurgically bonding the heat sink to the second surface of the integrated circuit die.

Abstract: Conducting liquid crystal polymer matrix comprising carbon nanotubes aligned in the matrix is provided, along with use thereof and method of fabrication.

Abstract: A thermally-enhanced ball grid array package structure is provided that includes an integrated circuit chip, a heat spreader and a substrate. The integrated circuit chip has a specified surface area. The heat spreader is coupled to the integrated circuit chip. The substrate is coupled to the heat spreader. The substrate has a specified surface area. The heat spreader covers a specified portion of the surface area of the substrate that is greater than the surface area of the integrated circuit chip. The heat spreader is operable to dissipate heat from the integrated circuit chip over the specified portion of the surface area of the substrate.

Abstract: At least one bearing body in a power semiconductor module has a surface section on which a first semiconductor component and at least one additional semiconductor component are arranged adjacent to each other. The semiconductor components have contact surfaces, oriented away from the surface section of the bearing body, that are in a contact in a planar manner to provide a flat connection line between the contact surfaces of the semiconductor components. The flat connection line has a lower inductivity and a lower instance dependency of inductivity compared to a bonding wire. A distance between the semiconductor components along the surface section is greater than a lateral measurement of at least one of the semiconductor components and can be, selectively, relatively large, allowing for thermal and/or temperature expansion and a lower thermal load of the semiconductor module than previously obtained.

Abstract: A method for manufacturing a heat sink of a semiconductor device is described. In the method, an adhesive tape is provided, wherein the adhesive tape includes a first surface and a second surface on opposite sides, and the first surface of the adhesive tape adheres to a surface of a temporary substrate. At least one semiconductor device is provided, wherein the semiconductor device includes a first side and a second side opposite to the first side, and the first side of the one semiconductor device is pressed and set into a portion of the second surface of the adhesive tape, and the second side of the one semiconductor device is exposed. A thin metal layer is formed on the second side of the semiconductor device and the exposed portion of the second surface of the adhesive tape. A metal heat sink is formed on the thin metal layer. Then, the adhesive tape and the temporary substrate are removed.

Abstract: A circuit assembly having an insulating base, a heat-conducting plate and a circuit containing die is disclosed. The die is in thermal contact with the heat-conducting plate, which is bonded to the insulating base. The insulating base includes heat-conducting channels that are in thermal contact with the heat-conducting plate. The die includes an integrated circuit therein and is mounted such that the heat-conducting plate is disposed between the die and the insulating plate. The insulating base preferably includes signal conducting channels for providing electrical connections to the die, the heat-conducting plate having an opening therein for making the connections between the die and the conducting channels. The assembly may also include a heat-spreading cover in thermal contact with the heat-conducting base plate, the heat-spreading cover overlying the die. The heat-conducting channels are preferably filled with solder, and include a solder protrusion extending from the heat-conducting channels.

Abstract: The mounting structure of a power device is simplified so as to reduce cost while achieving improvements in heat dissipation and reliability. A power module 100 is comprised of a metal wiring board 13, a power device 11 disposed on an upper surface of the metal wiring board 13 via a solder layer 12, a metal heat dissipating plate 15 disposed on a lower surface of the metal wiring board 13, and a heat sink 19 disposed on a lower surface of the metal heat dissipating plate 15. A resin-based insulating layer 14 is disposed between any desired two of the aforementioned layers.

Abstract: A semiconductor package including a bidirectional compound semiconductor component and two power semiconductor devices connected in a cascode configuration.

Abstract: An electronic device. The electronic device includes a circuit board, a heat dissipation module, and a light-emitting diode. The circuit board includes a heating element thereon. The heat dissipation module is disposed on the circuit board and the heating element. The light-emitting diode is disposed on the heat dissipation module. The heat dissipation module is connected to the heating element and the light-emitting diode.

Abstract: A custom-molded heat sink corresponds to an individual substrate and includes a heat sink lid having at least one cavity corresponding to at least one die mounted on a substrate. A conductive layer is deposited in the at least one cavity that substantially fills the space between the at least one cavity and the at least one die when the lid is coupled to the substrate.

Abstract: A solder is deposited on the backside of a wafer. The wafer can be pre-deposited with a barrier layer such as a titanium base and other materials. Deposition is carried out by electroplating, electroless plating, chemical vapor deposition, and physical vapor deposition. The solder-deposited die is bonded with a heat spreader that did not require a pre-deposited solder.

Abstract: The invention relates to a power module comprising a substrate (2), whose surfaces are provided with at least one electrically conductive layer (4, 6), at least one active semiconductor chip (8), which is electrically connected to an electrically conductive layer (6), a film (12) consisting of an electrically conductive material, which is in close contact with the surfaces of the semiconductor chips (8) of the electrically conductive layer (6) and the substrate (2) and is provided with planar printed conductors (16).

Abstract: A method and apparatus for making a package having improved heat conduction characteristics and high frequency response. A relatively thick package substrate, such as copper, has a wiring layer bonded to one face, leaving the opposite face exposed, for example, to be a surface for connection to a heat sink. One ore more chips are bonded to the wiring layer, and an array of connectors, such as solder balls are provided around the periphery of the chip(s) for connection to a printed circuit board. In some embodiments, the printed circuit board has a hole that the chip(s) extend into to allow smaller external-connection solder balls. In some embodiments, a second heat sink is connected to the back of the chip through the PCB hole.

Abstract: A process for fabricating a chip package structure with the following steps is provided. First, a chip having an active surface is provided. A plurality of solder bumps is disposed on the active surface. Then, a polymer material including flux is placed on the surface of the solder bumps by a dipping process. The chip is disposed on a carrier such that the carrier is in contact with the solder bumps. A reflow process is carried out so that the chip and the carrier are electrically connected through the solder bumps and a plurality of supporting structures made from the polymer material are formed around the junctions between the solder bumps and the carrier. The supporting structures enhance the endurance of the solder bumps to thermal stress and reduce damage due to fatigue.

Abstract: A chip package including a heat spreader, a circuit substrate, locating structures, a chip, wires, and an encapsulating compound is provided. The heat spreader has a bonding surface, and the circuit substrate is disposed on the bonding surface of the heat spreader. The circuit substrate has an opening, which exposes a portion of the bonding surface. The locating structures are disposed on the heat spreader for fixing the circuit substrate and attaching the circuit substrate to the bonding surface closely. The chip is disposed on the bonding surface exposed by the opening, and the wires are coupled between the chip and the circuit substrate. The encapsulating compound is disposed on the bonding surface exposed by the opening for covering the chip, the wires, and a portion of the circuit substrate. The chip package has high reliability and high yield of processing.

Abstract: A central processing unit (CPU) is disclosed. The CPU includes a CPU die; and a power management die bonded to the CPU die in a three dimensional packaging layout.

Abstract: Under the present invention, a semiconductor chip is electrically connected to a substrate (e.g., organic, ceramic, etc.) by an interposer structure. The interposer structure comprises an elastomeric, compliant material that includes metallurgic through connections having a predetermined shape. In a typical embodiment, the metallurgical through connections electrically connect an under bump metallization of the semiconductor chip to a top surface metallization of the substrate. By utilizing the interposer structure in accordance with the present invention, the problems associated with previous semiconductor module designs are alleviated.

Abstract: The formation of electronic assemblies including a heat spreader coupled to at least one die is described. One embodiment relates to a method including positioning a solder on a heat spreader. The method also includes forming a solid state diffusion bond between the solder and the heat spreader. The solid state diffusion bonded solder and heat spreader are positioned on a die and heated to a temperature sufficient to melt the solder and form a bond between the solder and the die, in the absence of a flux. Other embodiments are described and claimed.

Abstract: A chip package includes a thermal interface material disposed between a die backside and a heat sink. A dielectric sheet is also disposed between the die backside and the heat sink. The dielectric sheet diminishes overall heat transfer from the die to the heat sink by a small fraction of total possible heat transfer without the dielectric sheet. A method of operating the chip includes biasing the chip with the dielectric sheet in place.

Abstract: A semiconductor device includes: first and second metallic plates, each of which includes a heat radiation surface and an inner surface; a semiconductor element between the metallic plates; a block between the second metallic plate and the semiconductor element; a solder member between the second metallic plate and the block; and a resin mold. The heat radiation surface is exposed from the resin mold. The second metallic plate includes a groove for preventing the solder member from expanding outside of the block. The groove is disposed on the inner surface and disposed on an outer periphery of the block. The second metallic plate further includes an inner surface member on an inner surface of the groove. The inner surface member has a solder wettability, which is larger than a solder wettability of the block.

Abstract: A semiconductor device includes an interposer having first and second faces pointing in opposite directions to each other and a metallization pattern formed on the first face, and a semiconductor chip mounted on the first face of the interposer and having an electrode electrically connected with the metallization pattern. The interposer has a spacer formed within an overlapping region of the second face which the semiconductor chip overlaps and a land formed out of the overlapping region of the second face which the semiconductor chip overlaps. The spacer is formed so as not to be electrically connected with the metallization pattern, and the land is electrically connected with the metallization pattern.

Abstract: A chip package is provided. The chip package includes at least one chip, an interconnection structure, a plurality of second pads and at least one panel-shaped component, wherein the chip includes a plurality of first pads on a surface thereof. The interconnection structure is disposed on the chip, and the first pads of the chip are electrically coupled to the interconnection structure. The second pads are disposed on the interconnection structure, and the panel-shaped component is embedded in the interconnection structure. The panel-shaped component also includes a plurality of electrodes on its two opposite surfaces, and the second pads are electrically coupled to the first pads of the chip through the interconnection structure and the panel-shaped component.

Abstract: An efficient chip stacking structure is described that includes a leadframe having two surfaces to each of which can be attached stacks of chips. A chip stack can be formed by placing a chip active surface on a back surface of another chip. Electrical connections between chips and leads on the leadframe are facilitated by bonding pads on chip active surfaces and by via that extend from the bonding pads through the chips to the back surfaces.

Abstract: A structure provides for the control of bond wire impedance. In an example embodiment, there is an integrated circuit device comprising a semiconductor device die having a plurality of grounding pads, signal pads, and power pads and a package for mounting the integrated circuit and includes a conductive path having at least one reference trace that surrounds the integrated circuit. A grounding arch is disposed over the semiconductor device die.

Abstract: A semiconductor package in which heat is easily dissipated and a semiconductor chip is not damaged during a molding process, and a method of manufacturing the same. The semiconductor package with a heat dissipating structure includes a substrate, a semiconductor chip, which is mounted on the substrate and electrically connected with the substrate by bonding means, a heat slug which is adhered to the semiconductor chip and formed of a thermally conductive material, and a heat spreader partially exposed to the outside of the semiconductor package, and which is formed on the heat slug to be spaced a buffer gap apart from the heat slug.

Abstract: Electrically, mechanically, and thermally enhanced ball grid array (BGA) packages are described. An IC die is mounted in a centrally located cavity of a substantially planar first surface of a stiffener. The first surface of a substrate is attached to a substantially planar second surface of the stiffener. The second surface of the stiffener is opposed to the first surface of the stiffener. A centrally located protruding portion on the second surface of the stiffener is opposed to the centrally located cavity. The protruding portion extends through an opening in the substrate. A wire bond is coupled from a bond pad of the IC die to a contact pad on the first surface of the substrate through a through-pattern in the stiffener. The through-pattern in the stiffener is one of an opening through the stiffener, a recessed portion in an edge of the stiffener, a notch in an edge of the recessed portion, and a notch in an edge of the opening.

Abstract: Removing heat generated by an operating IC chip from both the chip and the electronics package containing the chip is essential for proper system operation and to increase the life of the electronics package. Using an air permeable lid with the electronic package increases the heat transfer away from the IC chip and electronics package, thereby cooling the chip and the package.

Abstract: A thermally-enhanced ball grid array package structure is provided that includes an integrated circuit chip, a heat spreader and a substrate. The integrated circuit chip has a specified surface area. The heat spreader is coupled to the integrated circuit chip. The substrate is coupled to the heat spreader. The substrate has a specified surface area. The heat spreader covers a specified portion of the surface area of the substrate that is greater than the surface area of the integrated circuit chip. The heat spreader is operable to dissipate heat from the integrated circuit chip over the specified portion of the surface area of the substrate.

Abstract: Electronically grounded heat spreaders are employed in connection with the dissipation of heat, which is generated by electronic devices, such as semiconductor chips. Also provided is a novel method for the adhesive fastening of metallic heat spreaders to semiconductor chips through the combined use of electrically conductive and non-conductive adhesive materials.

Abstract: A technique is provided for dissipating heat from an integrated circuit within a package. A thermally conductive strip may be disposed adjacent to an integrated circuit die before packaging. The package is formed around the integrated circuit and the thermally conductive strip such that a portion of the thermally conductive strip extends through the package. Heat is conducted from the integrated circuit through the thermally conductive strip to the environment surrounding the package. A thermally conductive strip may be installed within a package by an adhesive or other mechanical means. A thermally conductive strip may be comprised of a metallic foil or other thermally conductive material.

Abstract: Electrically, mechanically, and thermally enhanced ball grid array (BGA) packages are described. A substrate has a surface, wherein the surface has an opening therein. A stiffener has a surface coupled to the surface of the substrate. An area of the surface of the stiffener can be greater than, equal to, or less than an area of the surface of the substrate. A thermal connector is coupled to the surface of the stiffener through the opening. A surface of the thermal connector is capable of attachment to a printed circuit board (PCB) when the BGA package is mounted to the PCB. The thermal connector can have a height such that the thermal connector extends into a cavity formed in a surface of the PCB when the BGA package is mounted to the PCB. Alternatively, the stiffener and thermal connector may be combined into a single piece stiffener, wherein the stiffener has a protruding portion.

Abstract: A semiconductor device includes a semiconductor substrate having a main surface, the main surface including a first area formed with a high-frequency circuit element and a second area located around the first area and formed with a low-frequency circuit element. The semiconductor device also includes a sealing resin which covers the main surface; a plurality of first external terminals which are formed above the second area and which are electrically connected to the high-frequency circuit element, the first external terminals protruding from the surface of the sealing resin. The semiconductor device further includes a plurality of second external terminals which are formed above the second area and which are electrically connected to the low-frequency circuit element, the second external terminals protruding from the surface of the sealing resin.

Abstract: A light engine (16) includes at least one LED (12) for generating light of one of a plurality of wavelengths. The LED (12) is disposed on the magnetic core printed circuit board (14). A heatsink (26) is disposed in thermal communication with a base (24) and the LED (12) for conducting thermal energy away from the LED (12). The light engine (16) is magnetically attached to the heatsink (26) via a magnet (50) which is attached to the heatsink (26) to create that a magnetic force between the magnetic core board (14) and the heatsink (26).

Abstract: A semiconductor device for dissipating heat generated by a die during operation and having a low height profile, a semiconductor die package incorporating the device, and methods of fabricating the device and package are provided. In one embodiment, the semiconductor device comprises a thick thermally conductive plane (e.g., copper plane) mounted on a thin support substrate and interfaced with a die. Thermally conductive via interconnects extending through the substrate conduct heat generated by the die from the conductive plane to conductive balls mounted on traces on the opposing side of the substrate. In another embodiment, the semiconductor devices comprises a thick thermally conductive plane (e.g., copper foil) sandwiched between insulative layers, with signal planes (e.g., traces, bonding pads) disposed on the insulative layers, a die mounted on a first signal plane, and solder balls mounted on bonding pads of a second signal plane.

Abstract: An electrically and thermally enhanced die-up tape substrate ball grid array (BGA) package and die-up plastic substrate BGA package are described. A substrate that has a first surface and a second surface is provided. An IC die is mounted to the first substrate surface. A plurality of solder balls is attached to the second substrate surface. A thermal connector is mounted to the second substrate surface. The thermal connector is configured be coupled to a printed circuit board.

Abstract: A CPU cooling assembly having a first, covering layer of conductive material above the upper surface of an enclosed, heat producing chip and a third, upper layer of conductive material (a heat sink base plate) thermally bonded to the first by an intermediate, second layer of thin, conforming material (thermal grease) that is far less thermally conductive, and more resistive, than the other two layers. The relative thickness relationship of the first and third, more conductive, layers is essentially reversed from the prior art, with first layer being relatively thicker than the third. This creates an overall lower resistance for the three layer sandwich.

Abstract: Heat sink structures employing carbon nanotube or nanowire arrays to reduce the thermal interface resistance between an integrated circuit chip and the heat sink are disclosed. Carbon nanotube arrays are combined with a thermally conductive metal filler disposed between the nanotubes. This structure produces a thermal interface with high axial and lateral thermal conductivities.

Abstract: An electrically and thermally enhanced die-up tape substrate ball grid array (BGA) package and die-up plastic substrate BGA package are described. A substrate that has a first surface and a second surface is provided. The stiffener has a first surface and a second surface. The second stiffener surface is attached to the first substrate surface. An IC die has a first surface and a second surface. The first IC die surface is mounted to the first stiffener surface. A plurality of solder balls is attached to the second substrate surface. In one aspect, a heat spreader is mounted to the second IC die surface. In another aspect, the stiffener is coupled to ground to act as a ground plane. In another aspect, the substrate has a window opening that exposes a portion of the second stiffener surface. The exposed portion of the second stiffener surface is configured to be coupled to a printed circuit board (PCB). In another aspect, a metal ring is attached to the first stiffener surface.

Abstract: A three-dimensional integrated circuit that provides reduced interconnect signal delay over known 2-dimensional systems. The three-dimensional integrated circuit also allows improved circuit cooling. The three-dimensional integrated circuit includes two or more electrically connected integrated circuits, separated by a cooling channel.

Abstract: A dimpled heat spreader includes a central portion configured to couple to the circuit board component, an outer portion coupled to the central portion, and dimpled portions disposed within the outer portion. The outer portion is configured to extend from the central portion and support the dimpled portions beyond a footprint of the circuit board component when the central portion couples to the circuit board component. The dimpled portions of such a heat spreader provides more exposed surface area (e.g., per square inch) than conventional heat spreaders with flat end portions for improved and enhanced heat dissipation via natural convection into the ambient air. Moreover, a heat spreader with such dimpled portions is relatively easy and cost effective to make vis-à-vis more complex structures such as fins or posts thus enabling a manufacturer to produce dimpled heat spreaders using a high volume, low cost assembly process.

Abstract: An optoelectronic assembly for an electronic system includes a transparent substrate having a first surface and an opposite second surface, the transparent substrate being thermally conductive and being metallized on the surface. A support electronic chip set is configured for at least one of providing multiplexing, demultiplexing, coding, decoding and optoelectronic transducer driving and receive functions and is bonded to the second surface of the transparent substrate. A first substrate having a first surface and an opposite second surface, is in communication with the transparent substrate via the metallized second surface and support chip set therebetween. A second substrate is in communication with the second surface of the first substrate and is configured for mounting at least one of data processing, data switching and data storage chips.

Abstract: A semiconductor package and a method for forming the same are provided. The semiconductor package comprises a chip having an active surface and a back surface. The semiconductor package further comprises a substrate having an upper surface and a lower surface opposite the upper surface. The chip is electrically connected to the upper surface of the substrate. A lid is thermally coupled to the back surface of the chip. A thermal interface material (TIM) is located between the chip and the lid. The TIM includes voids to reduce thermomechanical stresses applied on the chip and the TIM, thereby preventing package cracks.

Abstract: A first electronic device, a second electronic device which generates less heat than the first electric device, and an electrode are connected by a heat leveling plate formed of an electrically conductive material having high thermal conductivity. A heat radiation plate is provided below an insulated substrate to which the first and second electronic devices are mounted. The second electronic device is cooled by a heat radiation path which extends through the insulated substrate and the heat radiation plate and a heat radiation path which extends through the second electronic device and the electrode to the heat radiation plate. The first and the second electronic device have substantially the same temperature due to heat radiation through the heat leveling plate. As a result, cooling effect of the electronic devices can be enhanced.