Abstract: The manufacturing yield of semiconductor devices (CMUTs) is improved. Before a polyimide film serving as a protective film is formed, a membrane is repeatedly vibrated to evaluate the breakdown voltage between an upper electrode and a lower electrode, and the upper electrode of a defective CMUT cell whose breakdown voltage between the upper electrode and the lower electrode is reduced due to the repeated vibrations of the membrane is removed in advance to cut off the electrical connection with other normal CMUT cells. By this means, in a block RB or a channel RCH including the recovered CMUT cell RC, reduction in the breakdown voltage between the upper electrode and the lower electrode after the repeated vibrations of the membrane is prevented.

Abstract: A semiconductor device includes first lines extending in a first direction and formed in a first wiring layer in a predetermined arrangement order, second lines formed in a second wiring layer different from the first wring layer in the predetermined arrangement order, and contacts electrically connecting between the first lines and the second lines so as to match the arrangement order. In the semiconductor device, at least adjacent two tracks are defined in a linear manner parallel to a second direction perpendicular to the first direction. Then, each of the second lines includes a first line portion extending along one of the two tracks, a second line portion extending along another of the two tracks, and a connection portion connecting between the first and second line portions, while two or more of the contacts are formed at the connection portion.

Abstract: In one embodiment, a bi-directional diode structure is formed to have a substantially symmetrical current-voltage characteristic.

Abstract: A method of manufacturing a semiconductor device includes providing first and second semiconductor substrates, each having first and second main surfaces opposite to one another. A roughened surface is formed on at least one of the first main surface of the first semiconductor substrate and the second main surface of the second semiconductor substrate. A dielectric layer is formed on the first main surface of the semiconductor substrate and the second semiconductor substrate is disposed on the dielectric layer opposite to the first semiconductor substrate. The second main surface of the second semiconductor substrate contacts the dielectric layer.

Abstract: The invention relates to the creation of a housing for an integrated circuit which makes it possible to detect physical ingression into said housing. The invention applies in particular to the protection of secrets which may possibly be contained in said integrated circuit, in the event of physical attack, for example by destroying the secrets contained in an integrated circuit in the event of ingression into the housing thereof.

Abstract: An apparatus and method for low-power sensing, for example, sensing of chemical or biochemical analytes in a gas or liquid phase are disclosed. One aspect relates to the use of a thin continuous film without grain boundaries as a sensing layer in devices for sensing a predetermined analyte and to low power devices having such sensing layer. The sensing layer has a surface exposed to the analyte. The electrical impedance of the sensing layer changes upon adsorption of the predetermined analyte on the exposed surface of the sensing layer. The sensing layer may have a thickness in the range between about 1 nm and 100 nm, such as between about 1 nm and 30 nm. The sensing layer may be an amorphous layer.

Abstract: An improved piezoresistive-based sensor (78) can include a cavity (66) in a substantially solid substrate (68). A reactive agent can optionally be present in the cavity (66). A flexible machined membrane can form a wall of the cavity (66). The flexible machined membrane can include an array of channels (76) configured to permit selective passage of a target material into and out of the cavity. Additionally, the flexible machined membrane can include a piezoresistive features (74) associated with the membrane. The reactive agent included in the cavity (66) can be volumetrically responsive to the presence of the target material or fluid. These sensors can be configured as pressure sensors, chemical sensors, flow sensors, and the like.

Abstract: A biosensor includes at least two field effect transistor devices, each including a silicon substrate, a silicon oxide film formed on a surface of the silicon substrate, a source electrode disposed on the silicon oxide film, a drain electrode disposed on the silicon oxide film, a channel for connecting the source electrode and the drain electrode, and a gate electrode capable of controlling the channel, wherein one of the at least two field effect transistor devices is provided with a reaction field on which a target recognition molecule is to be immobilized, and the other one of the at least two field effect transistor devices is provided with a reaction field on which a target recognition molecule is not to be immobilized.

Abstract: Methods and apparatus relating to FET arrays including large FET arrays for monitoring chemical and/or biological reactions such as nucleic acid sequencing-by-synthesis reactions. Some methods provided herein relate to improving signal (and also signal to noise ratio) from released hydrogen ions during nucleic acid sequencing reactions.

Abstract: In embodiments of the current invention, methods of combinatorial processing and a test chip for use in these methods are described. These methods and test chips enable the efficient development of materials, processes, and process sequence integration schemes for semiconductor manufacturing processes. In general, the methods simplify the processing sequence of forming devices or partially formed devices on a test chip such that the devices can be tested immediately after formation. The immediate testing allows for the high throughput testing of varied materials, processes, or process sequences on the test chip. The test chip has multiple site isolated regions where each of the regions is varied from one another and the test chip is designed to enable high throughput testing of the different regions.

Abstract: A contact efuse structure includes a silicon layer and a contact contacting the silicon layer with one end. When a voltage is applied to the contact, a void is formed at the end of the contact, and thus the contact is open. Such structure may be utilized in an efuse device or a read only memory. A method of making a contact efuse device and a method of making a read only memory are also disclosed.

Abstract: An arrangement of nonvolatile memory devices, having at least one memory device level stacked level by level above a semiconductor substrate, each memory level comprising an oxide layer substantially disposed above a semiconductor substrate, a plurality of word lines substantially disposed above the oxide layer; a plurality of bit lines substantially disposed above the oxide layer; a plurality of via plugs substantially in electrical contact with the word lines and, an anti-fuse dielectric material substantially disposed on side walls beside the bit lines and substantially in contact with the plurality of bit lines side wall anti-fuse dielectrics.

Abstract: We introduce a new technology for Manufactureable, High Power Density, High Volume Utilization Nuclear Batteries. Betavoltaic batteries are an excellent choice for battery applications which require long life, high power density, or the ability to operate in harsh environments. In order to optimize the performance of betavoltaic batteries for these applications or any other application, it is desirable to maximize the efficiency of beta particle energy conversion into power, while at the same time increasing the power density of an overall device. The small (submicron) thickness of the active volume of both the isotope layer and the semiconductor device is due to the short absorption length of beta electrons. The absorption length determines the self absorption of the beta particles in the radioisotope layer as well as the range, or travel distance, of the betas in the semiconductor converter which is typically a semiconductor device comprising at least one PN junction.

Abstract: Methods and apparatus relating to very large scale FET arrays for analyte measurements. ChemFET (e.g., ISFET) arrays may be fabricated using conventional CMOS processing techniques based on improved FET pixel and array designs that increase measurement sensitivity and accuracy, and at the same time facilitate significantly small pixel sizes and dense arrays. Improved array control techniques provide for rapid data acquisition from large and dense arrays. Such arrays may be employed to detect a presence and/or concentration changes of various analyte types in a wide variety of chemical and/or biological processes. In one example, chemFET arrays facilitate DNA sequencing techniques based on monitoring changes in hydrogen ion concentration (pH), changes in other analyte concentration, and/or binding events associated with chemical processes relating to DNA synthesis.

Abstract: A micro-channel chip can be coated uniformly with a thin inorganic oxide film and can prevent an ionic hydrophobic substance from adsorbing through a surface of an inorganic oxide film. In the micro-channel chip, surfaces of inner walls of through-holes in an upper plate member and a channel of a lower plate member are entirely coated with a SiO 2 film. The SiO 2 film is formed of two layers, namely a bottom layer that contains a high content of carbon atoms and is formed in a part that contacts a resin substrate, and a surface layer that contains nearly zero content of carbon atoms and t is formed in a part that is exposed on the surface of a channel.

Abstract: Disclosed is a semiconductor device (1) for determining NO concentrations in fluids such as exhaled breath. The device (1) typically comprises a pair of electrodes (18) separated from each other to define a channel region (16) in an organic semiconductor (14), a gate structure (10) for controlling said channel region, and a receptor layer (22) at least partially overlapping said channel region, said receptor layer comprising a porphine or phtalocyanine coordination complex including a group III-XII transition metal ion or a lead (Pb) ion for complexing NO. Such a semiconductor device is capable of sensing NO concentrations in the ppb range.

Abstract: An electrical detector is provided that comprises a nanofluidic channel with an integrated nanoscale charge sensor. The charge sensor can be an unfunctionalized nanowire, nanotube, transistor or capacitor and can be of carbon, silicon, carbon/silicon or other semiconducting material. The nanofluidic channel depth is on the order of the Debye screening length. Methods are also provided for detecting charged molecules or biological or chemical species with the electrical detector. Charged molecules or species in solution are driven through the nanofluidic channel of the electrical detector and contact the charge sensor, thereby producing a detectable signal. Methods are also provided for detecting a local solution potential of interest. A solution flowing through the nanofluidic channel of the electrical detector contacts the charge sensor, thereby producing a detectable local solution potential signal.

Abstract: A method of manufacturing a power semiconductor device according to the present invention includes the steps of: (a) forming a silicon nitride film on a semiconductor substrate; (b) after the step (a), forming a ring-shaped trench along a peripheral portion of the semiconductor substrate 6; (c) forming a first silicon oxide film on an inner surface of the trench; (d) after the step (c), forming a second silicon oxide film on an entire surface of the semiconductor substrate to bury the trench; (e) planarizing the second silicon oxide film by using the silicon nitride film as a stopper; and (f) forming a third silicon oxide film in a region in which the silicon nitride film is removed.

Abstract: There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a MEMS device, and technique of fabricating or manufacturing a MEMS device, having mechanical structures encapsulated in a chamber prior to final packaging. The material that encapsulates the mechanical structures, when deposited, includes one or more of the following attributes: low tensile stress, good step coverage, maintains its integrity when subjected to subsequent processing, does not significantly and/or adversely impact the performance characteristics of the mechanical structures in the chamber (if coated with the material during deposition), and/or facilitates integration with high-performance integrated circuits. In one embodiment, the material that encapsulates the mechanical structures is, for example, silicon (polycrystalline, amorphous or porous, whether doped or undoped), silicon carbide, silicon-germanium, germanium, or gallium-arsenide.

Abstract: According to one embodiment, a method for manufacturing a semiconductor device, wherein an amorphous semiconductor film comprising a microcrystal is annealed using a microwave, to crystallize the amorphous semiconductor film comprising the microcrystal using the microcrystal as a nucleus.

Abstract: On object of the invention is to provide a nonvolatile memory device, in which data can be added to the memory device after a manufacturing process and forgery and the like by rewriting can be prevented, and a semiconductor device including the memory device. Another object of the invention is to provide a highly-reliable, inexpensive, and nonvolatile memory device and a semiconductor device including the memory device. A memory element includes a first conductive layer, a second conductive layer, a first insulating layer with a thickness of 0.1 nm or more and 4 nm or less being in contact with the first conductive layer, and an organic compound layer interposed between the first conductive layer, the first insulating layer, and the second conductive layer.

Abstract: The present invention introduces a small-size temperature sensor, which exploits a random or oriented network of un-functionalized, single or multi-walled, carbon nanotubes to monitor a wide range of temperatures. Such network is manufactured in the form of freestanding thin film with an electric conductance proven to be a monotonic function of the temperature, above 4.2 K. Said carbon nanotube film is wire-connected to a high precision source-measurement unit, which measures its electric conductance by a standard two or four-probe technique. Said temperature sensor has a low power consumption, an excellent stability and durability, a high sensitivity and a fast response; its manufacturing method is simple and robust and yields low-cost devices. Said temperature sensor, freely scalable in dimension, is suitable for local accurate measurements of rapidly and widely changing temperatures, while introducing a negligible disturb to the measurement environment.

Abstract: A double-faced adhesive film including: a supporting film; a first adhesive layer laminated on one surface of the supporting film; and a second adhesive layer laminated on the other surface of the supporting film, wherein the glass transition temperatures, after curing, of the first adhesive layer and the second adhesive layer are each 100° C. or lower, and the first adhesive layer and the second adhesive layer are the layers capable of being formed by a method including the steps of directly applying a varnish to the supporting film and drying the applied varnish.

Abstract: Aimed at reducing the area of a protective circuit in a semiconductor device provided therewith, a semiconductor device of the present invention has a first-conductivity-type well, a plurality of first diffusion layers formed in the well, a plurality of second diffusion layers formed in the well, and a diffusion resistance layer formed in the well, wherein the first diffusion layers have a second conductivity type, and are connected in parallel with each other to an input/output terminal of the semiconductor device; the second diffusion layers are arranged alternately with a plurality of first diffusion layers, and are connected to a power source or to the ground; the diffusion resistance layer has a second conductivity type, and is located in adjacent to any of the plurality of second diffusion layers; the diffusion resistance layer is connected to the input/output terminal of the semiconductor device, while being arranged in parallel with the first diffusion layers, and connects the internal circuit and the

Abstract: Method and apparatus providing a wafer level fabrication of imager modules in which a permanent carrier protects imager devices on an imager wafer and is used to support a lens wafer.

Abstract: A sensor device (100, 2800) for detecting particles, the sensor device (100, 2800) comprising a substrate (102), a first doped region (104) formed in the substrate (102) by a first dopant of a first type of conductivity, a second doped region (106, 150) formed in the substrate (102) by a second dopant of a second type of conductivity which differs from the first type of conductivity, a depletion region (108) at a junction between the first doped region (104) and the second doped region (106, 150), a sensor active region (110) adapted to influence a property of the depletion region (108) in the presence of the particles, and a detection unit (112) adapted to detect the particles based on an electric measurement performed upon application of a predetermined reference voltage between the first doped region (104) and the second doped region (106, 150), the electric measurement being indicative of the presence of the particles in the sensor active region (110).

Abstract: The present invention provides a semiconductor device including: a first resistance element formed of a first polysilicon layer that contains impurities; a second resistance element provided on a same surface as the first polysilicon layer, and formed of a second polysilicon layer that contains an equal amount of impurities to the first polysilicon layer; a first interlayer insulation film provided so as to cover the first resistance element and the second resistance element; and a first metal layer provided on the first interlayer insulation film so as to cover the second resistance element with the first interlayer insulation film disposed therebetween.

Abstract: This patent discloses an integrated electronic and optical MEMS (micro-electro-mechanical systems) based sensor wherein the same embossed diaphragm is used as the sensing element of both integrated parts. The optical part of the sensor is based on a Fabry-Perot cavity and the electronic part of the sensor is based on the piezoresistive effect. The signal output obtained from the electronic part of the sensor will be used to assist the fabrication of the Fabry-Perot cavities and as a reference to establish the quiescence point (Q-point) of the signal output from the optical part of the sensor. The invention includes sensors for detecting mechanical movements, such as those caused by pressure, sound, magnetic fields, temperature, chemical reaction or biological activities.

Abstract: A chemically sensitive field effect transistor includes a substrate, a conductor track structure situated on the substrate, and a functional layer which is contacted via the conductor track structure. To be able to form a thin, oxidation-stable and temperature-stable conductor track structure, the conductor track structure is made of a metal mixture which includes platinum and one or more metals selected from the group made up of rhodium, iridium, ruthenium, palladium, osmium, gold, scandium, yttrium, lanthanum, the lanthanides, titanium, zirconium, hafnium, niobium, tantalum, chromium, tungsten, rhenium, iron, cobalt, nickel, copper, boron, aluminum, gallium, indium, silicon, and germanium.

Abstract: A semiconductor device comprises a substrate, an active semiconductor layer situated on the substrate, a stack of interconnect layers deposited on the active semiconductor layer, and a neutron conversion layer deposited on the stack of interconnect layers, wherein the stack of interconnect layers is configured such that at least about 10% of secondary charged particles generated in the neutron conversion layer will have a sufficient ion track length in the active semiconductor layer to generate a detectable charge in the active semiconductor layer. Another semiconductor device comprises a substrate, an active semiconductor layer situated on the substrate, a neutron conversion layer deposited on the active semiconductor layer, and a stack of interconnect layers deposited on the neutron conversion layer.

Abstract: This invention provides a semiconductor type gas sensor that can considerably increase the detection sensitivity to low-concentration gases, and can increase the response-recovery speed to achieve a conspicuous improvement in the overall performance, as well as a manufacturing method thereof. This invention is a semiconductor type gas sensor including a semiconductor substrate having a hollow portion in a central part, an insulating film of a diaphragm structure disposed on this substrate to form to cover the hollow portion, a heater formed on this insulating film, a resistance-measuring electrode, and a gas-sensitive film formed on the resistance-measuring electrode, characterized in that the gas-sensitive film is made of monoclinic tungsten oxide containing a hexagonal tungsten oxide crystal.

Abstract: A method comprising: providing at least one first diamond film comprising polycrystalline diamond, e.g., nanocrystalline or ultrananocrystalline diamond, disposed on a substrate, wherein the first diamond film comprises a surface comprising diamond asperities and having a first diamond film thickness, removing asperities from the first diamond film to form a second diamond film having a second diamond film thickness, wherein the second thickness is either substantially the same as the first thickness, or the second thickness is about 100 nm or less thinner than the first diamond film thickness, optionally patterning the second diamond film to expose substrate regions and, optionally, depositing semiconductor material on the exposed substrate regions, and depositing a solid layer on the second diamond film to form a first layered structure.

Abstract: A semiconductor device capable of wireless communication, which has high reliability in terms of resistance to external force, in particular, pressing force and can prevent electrostatic discharge in an integrated circuit without preventing reception of an electric wave. The semiconductor device includes an on-chip antenna connected to the integrated circuit and a booster antenna which transmits a signal or power included in a received electric wave to the on-chip antenna without contact. In the semiconductor device, the integrated circuit and the on-chip antenna are interposed between a pair of structure bodies formed by impregnating a fiber body with a resin. One of the structure bodies is provided between the on-chip antenna and the booster antenna. A conductive film having a surface resistance value of approximately 106 to 1014 ?/cm2 is formed on at least one surface of each structure body.

Abstract: Disclosed is a device comprising a substrate carrying a microscopic structure in a cavity capped by a capping layer including a material of formula SiNxHy, wherein x>1.33 and y>0. A method of forming such a device is also disclosed.

Abstract: A capacitive chemical sensor, along with methods of making and using the sensor are provided. The sensors described herein eliminate undesirable capacitance by etching away the substrate underneath the capacitive chemical sensor, eliminating most of the substrate capacitance and making changes in the chemical-sensitive layer capacitance easier to detect.

Abstract: A method is described for manufacturing a semiconductor device that comprises the steps of providing on a substrate a layer of a conducting material in a pattern comprising isolated elements having a first set of edges. The method further includes providing, on the substrate, a series of wall structures for forming one or more cavities there between. The wall structures have a second set of edges cooperating with the first set of edges. The second set of edges is positioned outside the first set of edges by a pre-defined distance. The method furthermore includes depositing a liquid material in the cavities. A display and an electronic apparatus incorporating the above described features is also disclosed.

Abstract: An arrangement of nonvolatile memory devices, having at least one memory device level stacked level by level above a semiconductor substrate, each memory level comprising an oxide layer substantially disposed above a semiconductor substrate, a plurality of word lines substantially disposed above the oxide layer; a plurality of bit lines substantially disposed above the oxide layer; a plurality of via plugs substantially in electrical contact with the word lines and, an anti-fuse dielectric material substantially disposed on side walls beside the bit lines and substantially in contact with the plurality of bit lines side wall anti-fuse dielectrics.

Abstract: An improved SRAM and fabrication method are disclosed. The method comprises use of a nitride layer to encapsulate PFETs and logic NFETs, protecting the gates of those devices from oxygen exposure. NFETs that are used in the SRAM cells are exposed to oxygen during the anneal process, which alters the effective work function of the gate metal, such that the threshold voltage is increased, without the need for increasing the dopant concentration, which can adversely affect issues such as mismatch due to random dopant fluctuation, GIDL and junction leakage.

Abstract: A thermoelectric module has a first substrate, a second substrate spaced from the first substrate, a plurality of P type thermoelectric elements and N type thermoelectric elements arranged in the space between the first and second substrates, and a plurality of electrodes which connect the P type and N type thermoelectric elements in series. Each electrode is connected to a respective one of the plurality of P type thermoelectric elements at a first connection and a respective one of the plurality of N type thermoelectric elements in the space, and a sealant is located at an edge portion of the space. Each one of a series of first or outer electrodes closest to the edge portion of the space has a concave portion that is concaved in a direction departing from the edge portion of the space and is at a position between the first connection and the second connection.

Abstract: The present invention provides a nitrogen-oxide gas sensor that is able to measure nitric oxide and nitrogen dioxide at the same time and ensure measurement accuracy and long stability. For these purposes, the nitrogen-oxide gas sensor includes: an oxide ion conductive solid electrolyte; a primary film that contacts the solid electrolyte and is made of a p-type semi-conductor metal oxide; a secondary film that contacts the solid electrolyte and is made of a p-type semiconductor metal oxide; an n-type semiconductor metal oxide that is included in at least one of the primary and secondary films; a power source that applies electric power to the primary and secondary films by electrically connecting a primary node to the primary film and a secondary node to the secondary film; and a measurement unit that measures the electric potential difference between the primary and secondary nodes.

Abstract: A method that includes forming a first layer having a first dopant concentration, the first layer having an integrated circuit region and a micro-electromechanical region and doping the micro-electromechanical region of the first layer to have a second dopant concentration is presented. The method includes forming a second layer having a third dopant concentration overlying the first layer, doping the second layer that overlies the micro-electromechanical region to have a fourth dopant concentration, forming a micro-electromechanical structure in the micro-electromechanical region using the first and second layers, and forming active components in the integrated circuit region using the second layer.

Abstract: A low-cost micro-electro-mechanical system (MEMS) has a mass-produced carrier fabricated as a pre-molded leadframe so that the space of the leadframe center is filled with compound and a two-tier recess is created in the center. The first tier is filled by an inset with a first perforation and a second perforation. An integrated circuit chip with an opening and a membrane at the end of the opening, operable as a pressure sensor, microphone, speaker, etc, is assembled on the inset so that the opening is aligned with the first perforation. The chip is protected by a cover transected by a vent aligned with the second inset perforation. An air channel can then reach from the ambient through the vent and the second perforation to the second tier recess, which connects to the first perforation and the chip opening to the membrane.

Abstract: The invention relates to an electronic device for measuring and/or controlling a property of an analyte (100). The electronic device comprises: i) an electrode (Snsr) forming an interface with the analyte (100) in which the electrode (Snsr) is immersed in operational use, the interface having an interface temperature (T), and ii) a resistive heater (Htr) being thermally and capacitively coupled to the electrode (Snsr), the resistive heater (Htr) being configured for setting the interface temperature (T) by controlling a current through the resistive heater (Htr). The resistive heater (Htr) is provided with signal integrity protection for reducing the capacitive charging of the electrode (Snsr) by the resistive heater (Htr) if the current through the resistive heater (Htr) is modulated.

Abstract: This photodetector capable of detecting electromagnetic radiation comprises: a doped semiconductor absorption layer for said radiation, capable of converting said radiation into charge carriers; a reflective layer that reflects the incident radiation that is not absorbed by semiconductor layer towards the latter, located underneath semiconductor layer; and a metallic structure placed on semiconductor layer that forms, with semiconductor layer, a surface Plasmon resonator so as to concentrate the incident electromagnetic radiation on metallic structure in the field concentration zones of semiconductor layer. Semiconductor zones for collecting charge carriers that are oppositely doped to the doping of semiconductor layer are formed in said semiconductor layer and have a topology that complements that of the field concentration zones.

Abstract: There is provided a semiconductor memory device including: a first wiring layer; a second wiring layer; a third wiring layer; a memory array region; a first gate array region being formed at a region at which the first wiring layer, the second wiring layer and the third wiring layer can be used in wiring of the plural unit cells; and a second gate array region being formed at a region at which two wiring layers that are the first wiring layer and the second wiring layer can be used in wiring of the plural memory cells, and the plural unit cells are arrayed so as to be separated at an interval needed for placement, by using the first wiring layer, of wiring that should be placed by using the third wiring layer.

Abstract: A MEMS switch (1, 81), and methods of fabricating thereof, the switch comprising: a sealed cavity (24); and a membrane (26); wherein the sealed cavity (24) is defined in part by the membrane (26); and the membrane is a 5 metallic membrane (26), for example consisting of a single type of metal or metal alloy. The MEMS switch (1, 81) may comprise a top electrode (30), for example extending into the cavity (24), located in a hole (32) in the metallic membrane (26). Fabrication may include providing a sacrificial layer (22) in a partly defined cavity (24). The bending stiffness of the membrane (26) may be 10 higher along an RF line (102) than along a line (104) perpendicular to the RF line (102), for example by virtue of the cavity (24) being elliptical.

Abstract: In a multi-core semiconductor device, a data bus between CPUs or the like consumes a larger amount of power. By provision of a plurality of CPUs which transmit data by a backscattering method of a wireless signal, a router circuit which mediates data transmission and reception between the CPUs or the like, and a thread control circuit which has a thread scheduling function, a semiconductor device which consumes less power and has high arithmetic performance can be provided at low cost.

Abstract: The invention provides devices, systems, and methods for detecting an analyte vapor. Particularly, electronegative analyte vapors, such as those vapors evolving from explosive compounds, are typical analytes detected the devices. The devices operate using a resistivity change mechanism wherein a nanostructured chemiresistive material undergoes a resistivity change in the presence of an analyte vapor. A resistivity change indicates the presence of an analyte.

Abstract: An output stage for a switched mode power supply has a high-side switch having a first power FET and a first speed-up FET monolithically integrated onto a first die. A low-side switch has a second power FET and a second speed-up FET monolithically integrated onto a second die. A semiconductor device has the power FET and the speed-up FET monolithically integrated in a “source-down” configuration. A method of operating an output stage of a switched mode power supply alternately turns on and off a high-side and a low-side switch and drives at least one of the switches with a speed-up FET monolithically integrated with the switch.

Abstract: Systems and methods for producing high quantum efficiency silicon devices. A silicon MBE has a preparation chamber that provides for cleaning silicon surfaces using an oxygen plasma to remove impurities and a gaseous (dry) NH3+NF3 room temperature oxide removal process that leaves the silicon surface hydrogen terminated. Silicon wafers up to 8 inches in diameter have devices that can be fabricated using the cleaning procedures and MBE processing, including delta doping.