Abstract: A semiconductor structure includes a gate, an oxide channel layer, a gate insulating layer, a source, a drain and a dielectric stacked layer. The oxide channel layer is stacked over the gate, with the gate insulting layer disposed therebetween. The source and the drain are disposed on a side of the oxide channel layer and in parallel to each other. A portion of the oxide channel layer is exposed between the source and the drain. The dielectric stacked layer is disposed on the substrate and includes plural of first inorganic dielectric layers with a first refraction index and plural of second inorganic dielectric layers with a second refraction index that are stacked alternately. At least one of the first inorganic dielectric layers directly covers the source, the drain and the portion of the oxide channel layer. The first refraction index is smaller than the second refraction index.

Abstract: An etching resist including first and second portions, the first portion being thicker than the second portion, is formed on a metallic layer. Through the etching resist, a semiconductor layer and the metallic layer are patterned by etching so as to form a wiring from the metallic layer and leave the semiconductor layer under the wiring. An electrical test is conducted on the wiring. The second portion is removed while the first portion is left unremoved. Selective etching is performed through the first portion so as to leave the semiconductor layer unetched to pattern the wiring to be divided into drain and source electrodes. A substrate is cut. In patterning the wiring, the wiring is etched to be cut at a position closer to a cutting line of the substrate with respect to the drain and source electrodes, while leaving the semiconductor layer unetched.

Abstract: A thin film transistor is provided, which comprises at least an active layer, a source electrode and a drain electrode, wherein the source electrode and the drain electrode are located on the active layer and spaced apart from each other; a channel is defined in the active layer between the source electrode and the drain electrode; edges of the active layer are aligned with outer edges of the source electrode and the drain electrode, the outer edge of the source electrode is an edge of the source electrode opposite to the drain electrode, and the outer edge of the drain electrode is an edge of the drain electrode opposite to the source electrode. Also, a method of manufacturing a thin film transistor is provided.

Abstract: Sol-gel-processed thin-film transistors (TFTs) with amorphours Y—In—Zn—O (YIZO) as an active layer are fabricated with various mole ratios of Y, which indicates that Y3+ could play the role of carrier suppressor in InZnO (IZO) systems and reduce off current of YIZO-TFT and its channel mobility, threshold voltage, subthreshold swing voltage, and on/off ratio.

Abstract: Device structures, design structures, and fabrication methods for a metal-oxide-semiconductor field-effect transistor. A gate structure is formed on a top surface of a substrate. First and second trenches are formed in the substrate adjacent to a sidewall of the gate structure. The second trench is formed laterally between the first trench and the first sidewall. First and second epitaxial layers are respectively formed in the first and second trenches. A contact is formed to the first epitaxial layer, which serves as a drain. The second epitaxial layer in the second trench is not contacted so that the second epitaxial layer serves as a ballasting resistor.

Abstract: Disclosed is a semiconductor device including an oxide semiconductor film. A first oxide semiconductor film with a thickness of greater than or equal to 2 nm and less than or equal to 15 nm is formed over a gate insulating layer. First heat treatment is performed so that crystal growth from a surface of the first oxide semiconductor film to the inside thereof is caused, whereby a first crystal layer is formed. A second oxide semiconductor film with a thickness greater than that of the first oxide semiconductor film is formed over the first crystal layer. Second heat treatment is performed so that crystal growth from the first crystal layer to a surface of the second oxide semiconductor film is caused, whereby a second crystal layer is formed. Further, oxygen doping treatment is performed on the second crystal layer.

Abstract: A flexible substrate for a display device comprises a polymer resin, an inorganic fiber material, and an antistatic agent, and has a surface resistivity of less than 1011?. A display device includes the flexible substrate.

Abstract: Provided is a top gate thin film transistor, including on a substrate: a source electrode layer; a drain electrode layer; an oxide semiconductor layer; a gate insulating layer; a gate electrode layer including an amorphous oxide semiconductor containing at least one kind of element selected from among In, Ga, Zn, and Sn; and a protective layer containing hydrogen, in which: the gate insulating layer is formed on a channel region of the oxide semiconductor layer; the gate electrode layer is formed on the gate insulating layer; and the protective layer is formed on the gate electrode layer.

Abstract: This wiring layer structure includes: an underlying substrate of a semiconductor substrate or a glass substrate; an oxygen-containing Cu layer or an oxygen-containing Cu alloy layer which is formed on the underlying substrate; an oxide layer containing at least one of Al, Zr, and Ti which is formed on the oxygen-containing Cu layer or the oxygen-containing Cu alloy layer; and a Cu alloy layer containing at least one of Al, Zr, and Ti which is formed on the oxide layer.

Abstract: In a transistor, a drain electrode to which a high electric field is applied is formed over a flat surface, and an end portion of a gate electrode on the drain electrode side in a channel width direction and an end portion of the gate electrode in a channel length direction are covered with an oxide semiconductor with a gate insulating layer between the gate electrode and the oxide semiconductor layer, so that withstand voltage of the transistor is improved. Further, a semiconductor device for high power application, in which the transistor is used, can be provided.

Abstract: A method and structures to achieve improved TFTs and high fill-factor pixel circuits are provided. This system relies on the fact that jet-printed lines have print accuracy, which means the location and the definition of the printed lines and dots is high. The edge of a printed line is well defined if the printing conditions are optimized. This technique utilizes the accurate definition and placement of the edges of printed lines of conductors and insulators to define small features and improved structures.

Abstract: A highly reliable transistor in which change in electrical characteristics is suppressed is provided. A highly reliable transistor in which change in electrical characteristics is suppressed is manufactured with high productivity. A display device with less image deterioration over time is provided. An inverted staggered thin film transistor which includes, between a gate insulating film and impurity semiconductor films functioning as source and drain regions, a semiconductor stacked body including a microcrystalline semiconductor region and a pair of amorphous semiconductor regions. In the microcrystalline semiconductor region, the nitrogen concentration on the gate insulating film side is low and the nitrogen concentration in a region in contact with the amorphous semiconductor is high. Further, an interface with the amorphous semiconductor has unevenness.

Abstract: A thin film transistor includes a gate electrode, a semiconductor layer, and a source electrode and a drain electrode placed on the semiconductor layer and electrically connected with the semiconductor layer. The semiconductor layer includes a light-transmitting semiconductor film and an ohmic conductive film placed on the light-transmitting semiconductor film and having a lower light transmittance than the light-transmitting semiconductor film. The ohmic conductive film is formed not to protrude from the light-transmitting semiconductor film. The ohmic conductive film is formed in separate parts with a channel part between the source electrode and the drain electrode interposed therebetween. The source electrode and the drain electrode are connected to the light-transmitting semiconductor film through the ohmic conductive film.

Abstract: A thin film transistor capable of reliably preventing the entry of light into an active layer, and a display including the thin film transistor are provided. A thin film transistor includes: a gate electrode; an active layer; and a gate insulating film arranged between the gate electrode and the active layer, the gate insulating film including a first insulating film, a first light-absorbing layer and a second insulating film, the first insulating film arranged in contact with the gate electrode, the first light-absorbing layer arranged in contact with the first insulating film and made of a material absorbing light of 420 nm or less, the second insulating film arranged between the first light-absorbing layer and the active layer.

Abstract: Provided is an alkylsilane laminate with which it is possible to obtain an organic semiconductor film having excellent semiconductor properties. Such a laminate can be useful for an organic thin-film transistor. The alkylsilane laminate comprises an underlayer (Sub) having hydroxyl groups at the surface and an alkylsilane thin film (AS) formed on this underlayer. The alkylsilane laminate is a laminate wherein the critical surface energy Ec of the alkylsilane thin film and the number of carbons (X) of the alkylsilane satisfies the following formula (1): Ec?29.00?0.63x (mN/m) (1) Also provided is a thin-film transistor (10) having such an alkylsilane laminate (Sub, AS).

Abstract: A fabrication process for a nanoelectronic device and a device are provided. Channel material is deposited on a substrate to form a channel. A source metal contact and a drain metal contact are deposited on the channel material, and the source metal contact and the drain metal contact are on opposing ends of the channel material. A polyhydroxystyrene derivative is deposited on the channel material. A top gate oxide is deposited on the polymer layer. A top gate metal is deposited on the top gate oxide.

Abstract: A fabrication process for a nanoelectronic device and a device are provided. Channel material is deposited on a substrate to form a channel. A source metal contact and a drain metal contact are deposited on the channel material, and the source metal contact and the drain metal contact are on opposing ends of the channel material. A polyhydroxystyrene derivative is deposited on the channel material. A top gate oxide is deposited on the polymer layer. A top gate metal is deposited on the top gate oxide.

Abstract: Disclosed is a photosensor element that is provided with a gate electrode (11da) disposed on an insulating substrate (10), a gate insulation film (12) disposed so as to cover the gate electrode (11da), a semiconductor layer (15db) disposed on the gate insulating film (12) so as to overlap the gate electrode (11da), and a source electrode (16da) and a drain electrode (16db) provided on the semiconductor layer (15db) so as to overlap the gate electrode (11da) and so as to face each other. The semiconductor layer (15db) is provided with an intrinsic semiconductor layer (13db) in which a channel region (C) is defined and an extrinsic semiconductor layer (14db) that is laminated on the intrinsic semiconductor layer (13db) such that the channel region (C) is exposed therefrom. The intrinsic semiconductor layer (13db) is an amorphous silicon layer containing nanocrystalline silicon particles.

Abstract: A thin-film transistor substrate includes a gate line, and a gate electrode connected to the gate line, on a base substrate; an insulating layer on the gate electrode, the insulating layer including a first part and a second part, the first part having a hydrophobic property and the second part having a hydrophilic property; a data line extended in a different direction from the gate line, and a source electrode connected to the data line and on the second part of the insulating layer; a drain electrode on the second part of the insulating layer, the drain electrode spaced apart from the source electrode; a semi-conductor pattern overlapping the source electrode, the drain electrode and a gap between the spaced apart source and drain electrodes, where the semi-conductor pattern exposes the first part of the insulating layer; and a pixel electrode in contact with the drain electrode.

Abstract: A pixel structure, a method of manufacturing the pixel structure, and an active device matrix substrate are provided. The pixel structure includes a first patterned metal layer having a common line and a gate; a first insulation layer; a semiconductor pattern; a second patterned metal layer having a source and a drain both electrically connected to the semiconductor pattern; a second insulation layer having a contact opening exposing the drain; and an electrode layer having a common electrode, and a pixel electrode connected to the drain through the contact opening. The common line, the first insulation layer, and the pixel electrode constitute a first storage capacitor. The common line, the drain, and the common electrode constitute a sandwich structure. The common line, the first insulation layer, and the drain constitute a second storage capacitor. The drain, the second insulation layer, and the common electrode constitute a third storage capacitor.

Abstract: A thin film transistor includes a gate insulating layer covering a gate electrode, a semiconductor layer in contact with the gate insulating layer, and impurity semiconductor layers which are in contact with part of the semiconductor layer and which form a source region and a drain region. The semiconductor layer includes a microcrystalline semiconductor layer formed on the gate insulating layer and a microcrystalline semiconductor region containing nitrogen in contact with the microcrystalline semiconductor layer. The thin film transistor in which off-current is small and on-current is large can be manufactured with high productivity.

Abstract: An oxide thin film transistor (TFT) and a fabrication method thereof are provided.

Abstract: A thin film transistor array panel includes a substrate, a gate line formed on the substrate and including a gate electrode, a gate insulating layer formed on the gate line, a semiconductor formed on the gate insulating layer and including a channel of a thin film transistor, a data line formed on the semiconductor and including a source electrode and a drain electrode formed on the semiconductor and opposite to the source electrode with respect to the channel of the thin film transistor, wherein the channel of the thin film transistor covers both side surfaces of the gate electrode.

Abstract: A display substrate includes a substrate, a gate line formed on the substrate, a data line formed on the substrate and crossing the gate line, a first pixel electrode formed on the substrate on which the gate and the data line are formed, an insulation layer formed on the substrate and the first pixel electrode, and a second pixel electrode formed on the insulation layer. The second pixel electrode includes a first sub-electrode that overlaps the first pixel electrode and the data line, and a second sub-electrode that is electrically connected to the data line through a switching element.

Abstract: In a method of forming an active pattern, a gate metal layer is formed on a base substrate. The gate metal layer is patterned to form a gate line, and a gate pattern spaced apart from the gate line. A gate insulation layer is formed on the base substrate including the gate line and the gate pattern thereon, to form a first protruded boundary surface corresponding to an area including the gate pattern. An amorphous semiconductor layer is formed on the base substrate including the gate insulation layer thereon, to form a second protruded boundary surface corresponding to the first protruded boundary surface. The amorphous semiconductor layer is crystallized by illuminating a laser to the amorphous semiconductor layer on the second protruded boundary surface.

Abstract: A thin film transistor panel includes a substrate, a light blocking layer on the substrate, a first protective film on the light blocking layer, a first electrode and a second electrode on the first protective film, an oxide semiconductor layer on a portion of the first protective film exposed between the first electrode and the second electrode, an insulating layer, a third electrode overlapping with the oxide semiconductor layer and on the insulating layer, and a fourth electrode on the insulating layer. The light blocking layer includes first sidewalls, and the first protective film includes second sidewalls. The first and the second sidewalls are disposed along substantially the same line.

Abstract: A method of fabricating MOTFTs on transparent substrates by positioning opaque gate metal on the substrate front surface and depositing gate dielectric material overlying the gate metal and a surrounding area and metal oxide semiconductor material on the dielectric material. Depositing selectively removable etch stop material on the semiconductor material and photoresist on the etch stop material to define an isolation area in the semiconductor material. Removing uncovered portions of the etch stop. Exposing the photoresist from the substrate rear surface using the gate metal as a mask and removing exposed portions leaving the etch stop material overlying the gate metal covered. Etching the semiconductor material to isolate the TFT. Selectively etching the etch stop layer to leave a portion overlying the gate metal defining a channel area. Depositing and patterning conductive material to form source and drain areas on opposed sides of the channel area.

Abstract: A method is used to prevent unwanted electrical contacts between various electrically conducting surfaces and lines in a display panel due to an n+ a-Si residue and/or ITO debris. The method provides a clearing pattern including at least a cleared area in the passivation layer for preventing the residue or debris from locating at the cleared area. As such, if an n+ a-Si residue happens to be deposited under the passivation layer, the part of the residue located in the cleared area is removed by an a-Si selective etching process, for example. Furthermore, with the cleared area, ITO debris deposited on the section of the dielectric layer deposited on the signal line can be electrically isolated from the electrode.

Abstract: It is an object of the present invention to provide a technique to manufacture a highly reliable display device at a low cost with high yield. A display device according to the present invention includes a semiconductor layer including an impurity region of one conductivity type; a gate insulating layer, a gate electrode layer, and a wiring layer in contact with the impurity region of one conductivity type, which are provided over the semiconductor layer; a conductive layer which is formed over the gate insulating layer and in contact with the wiring layer; a first electrode layer in contact with the conductive layer; an electroluminescent layer provided over the first electrode layer; and a second electrode layer, where the wiring layer is electrically connected to the first electrode layer with the conductive layer interposed therebetween.

Abstract: A thin film transistor includes: a gate electrode on a substrate; a source electrode; a drain electrode positioned in a same layer as the source electrode and facing the source electrode; an oxide semiconductor layer positioned between the gate electrode and the source electrode or drain electrode; and a gate insulating layer positioned between the gate electrode and the source electrode or drain electrode. The oxide semiconductor layer includes titanium oxide (TiOx) doped with niobium (Nb).

Abstract: A thin film transistor which may be included in a pixel circuit includes: a substrate; a semiconductor layer formed on the substrate and including a source region, a first drain region spaced apart from the source region by a first current path, and a second drain region spaced apart from the source region by a second current path having a length different from that of the first current path; a gate electrode insulated from the semiconductor layer by a gate insulating layer; a source electrode connected to the source region of the semiconductor layer; a first drain electrode connected to the first drain region of the semiconductor layer; and a second drain electrode connected to the second drain region of the semiconductor layer. Currents having different magnitudes may be simultaneously provided through the first current path and the second current path.

Abstract: A method is provided for controlling the channel length in a thin-film transistor (TFT). The method forms a printed ink first source/drain (S/D) structure overlying a substrate. A fluoropolymer mask is deposited to cover the first S/D structure. A boundary region is formed between the edge of the fluoropolymer mask and the edge of the printed ink first S/D structure, having a width. Then, a primary ink is printed at least partially overlying the boundary region, forming a printed ink second S/D structure, having an edge adjacent to the fluoropolymer mask edge. After removing the fluoropolymer mask, the printed ink first S/D structure edge is left separated from the printed ink second S/D structure edge by a space equal to the boundary region width. A semiconductor channel is formed partially overlying the first and second S/D structures, having a channel length equal to the boundary region width.

Abstract: A transistor structure disposed on a substrate includes a gate electrode, a gate insulating layer overlapping the gate electrode, a channel layer overlapping the gate electrode, and a plurality of first electrodes and a plurality of second electrodes overlapping the gate electrode. The gate insulating layer is disposed between the channel layer and the gate electrode. Besides, the gate insulating layer is located among the first electrodes, the second electrodes, and the gate electrode. The first electrodes and the second electrodes are alternately arranged along a first direction. Each of the first electrodes has a first width along the first direction. Each of the second electrodes has a second width along the first direction. A ratio of the first width to the second width ranges from 2 to 20. A driving circuit structure having the transistor structure is also provided.

Abstract: A second stem wires (17c), formed by a reflective pixel electrode layer formed as a different layer from first stem wires (17a), is provided in such a way as to extend along a long side of its adjacent one of the first stem wires (17a). This makes it possible to achieve a TFT array substrate (1) on which a gate drive circuit (15) and its wires (17a, 17b, 17c, 18) have been monolithically formed, wherein the width of a frame part in which the a gate drive circuit (15) and its wires (17a, 17b, 17c, 18) are formed can be reduced.

Abstract: Embodiments of methods, apparatuses, devices, and/or systems for forming a solution processed device are described.

Abstract: A thin film transistor includes a layer structure having a gate electrode, a gate insulation layer and a channel layer. A source line may contact the channel layer, and may extend along a direction crossing over the gate electrode. The source line may partially overlap the gate electrode so that both sides of the source line overlapping the gate electrode may be entirely positioned between both sides of the gate electrode. A drain line may make contact with the channel layer and may be spaced apart from the source line by a channel length. The drain line may have a structure symmetrical to that of the source line. Overlap areas among the gate electrode, the source line and the drain line may be reduced, so that the thin film transistor may ensure a high cut-off frequency.

Abstract: A pixel structure having the following structure is provided. A light-shielding layer with a flat layer covering thereon is disposed on a substrate. A channel layer, a data line and a first pad are disposed on the flat layer. A source and a drain partially cover two sides of the channel layer. A gate dielectric layer with a gate, a scan line and a second pad disposed thereon covering the channel layer, the source and the data line exposes the drain and the first pad. A protection layer covering the gate and the scan line exposes the drain, the first and second pads. A patterned transparent conductive layer includes a pixel electrode disposed on the protection layer, a first retain portion disposed on the first pad and a second retain portion disposed on the second pad.

Abstract: A method for fabricating a thin film transistor includes printing source, drain and channel regions on a passivated transparent substrate, forming a gate dielectric over the channel region and forming a gate conductor over the gate dielectric. A permanent antireflective coating is deposited over the source region, drain region and gate electrode, and an interlevel dielectric layer is formed over the permanent antireflective coating. Openings in the permanent antireflective coating and the interlevel dielectric layer are formed to provide contact holes to the source region, drain region and gate electrode. A conductor is deposited in the contact holes to electrically connect to the source region, drain region and gate electrode. Thin film transistor devices and other methods are also disclosed.

Abstract: A TFT structure is provided in which an oxidic semiconductor is used in combination with an electrode material based on a Cu alloy.

Abstract: A TFT (20) includes a semiconductor layer (12s1) of an oxide semiconductor, a source electrode (13sd) and a drain electrode (13dd) provided on the semiconductor layer (12s1) and separated from each other, a gate insulating film (15) covering a portion of the semiconductor layer between the source electrode (13sd) and the drain electrode (13dd), a gate electrode (18gd) provided over the semiconductor layer (12s1) with the gate insulating film (15) being interposed between the gate electrode (18gd) and the semiconductor layer (12s1). The source electrode (13sd) is integrally formed with the source line (13s1). The gate electrode (18gd) is integrally formed with the gate line (18g1). The semiconductor layer (12s1) extends below the source line (13s1). The entireties of the source line (13s1), the source electrode (13sd), and the drain electrode (13dd) are provided on the semiconductor layer (12s1).

Abstract: There is provided a flexible semiconductor device. The flexible semiconductor device of the present invention comprising a support layer, a semiconductor structure portion formed on the support layer, and a resin film formed on the semiconductor structure portion. The resin film comprises an opening formed by a laser irradiation therein, and also an electroconductive member which is in contact with the surface of the semiconductor structure portion is disposed within the opening of the resin film.

Abstract: A pixel structure includes a first electrode on a substrate, a first insulation layer covering the first electrode, a gate located on the first insulation layer, a second electrode located on the first insulation layer above the first electrode, a second insulation layer covering the gate and the second electrode, a semiconductor layer located on the second insulation layer above the gate, a source and a drain that are located on the semiconductor layer, a third electrode, a third insulation layer, and a pixel electrode. The third electrode is located on the second insulation layer above the second electrode and electrically connected to the first electrode. The third insulation layer covers the source, the drain, and the third electrode. The pixel electrode is located on the third insulation layer and electrically connected to the drain.

Abstract: A p-type transparent oxide semiconductor includes tin oxide compounds represented by below chemical formula 1: Sn1-xMxO2??[Chemical Formula 1] wherein, in the chemical formula 1, the M is tri-valent metal and the X is a real number of 0.01˜0.05. The p-type transparent oxide semiconductor is applicable to active semiconductor devices such as TFT-LCD and transparent solar cell, due to excellent electrical and optical properties and shows superior properties in aspects of visible light transmittance (T), carrier mobility (?) and rectification ratio as well as transparency.

Abstract: The graphene electronic device may include a gate oxide on a conductive substrate, the conductive substrate configured to function as a gate electrode, a pair of first metals on the gate oxide, the pair of the first metals separate from each other, a graphene channel layer extending between the first metals and on the first metals, and a source electrode and a drain electrode on both edges of the graphene channel layer.

Abstract: A thin film transistor substrate and a method for manufacturing the same are discussed, in which the thin film transistor comprises a gate line and a data line arranged on a substrate to cross each other; a gate electrode connected with the gate line below the gate line; an active layer formed on the gate electrode; an etch stopper formed on the active layer; an ohmic contact layer formed on the etch stopper; source and drain electrodes formed on the ohmic contact layer; and a pixel electrode connected with the drain electrode. It is possible to prevent a crack from occurring in the gate insulating film during irradiation of the laser and prevent resistance of the gate electrode from being increased.

Abstract: A thin film transistor array panel and a manufacturing method therefor. A shorting bar for connecting a thin film transistor with data lines is formed separate from the data lines, and then the data lines and the shorting bar are connected through a connecting member. As a result, all the data lines are floated during manufacture, so that variation in etching speed between data lines does not occur. Since variation in etching speed between the data lines can be prevented, performance deterioration of the transistor caused by a thickness difference in the lower layer of the data line can be prevented, as can resulting deterioration in display quality. Also, the influence of static electricity can be reduced or eliminated. Furthermore, since the data lines and the shorting bar are connected to each other, the generation of static electricity can be prevented or reduced, and quality testing is more readily performed.

Abstract: An organic film-forming polymer has a Tg of at least 70° C. and comprises a backbone comprising recurring units of Structure (A) shown in this application. These organic film-forming polymers can be used as dielectric materials in various devices with improved properties such as improved mobility.

Abstract: A gated microelectronic device is provided that has a source with a source ohmic contact with the source characterized by a source dopant type and concentration. A drain with a drain ohmic contact with the drain characterized by a drain dopant type and concentration. An intermediate channel portion characterized by a channel portion dopant type and concentration. An insulative dielectric is in contact with the channel portion and overlaid in turn by a gate. A gate contact applies a gate voltage bias to control charge carrier accumulation and depletion in the underlying channel portion. This channel portion has a dimension normal to the gate which is fully depleted in the off-state. The dopant type is the same across the source, drain and the channel portion of the device. The device on-state current is determined by the doping and, unlike a MOSFET, is not directly proportional to device capacitance.

Abstract: Provided is an alkylsilane laminate with which it is possible to obtain an organic semiconductor film having excellent semiconductor properties. Such a laminate can be useful for an organic thin-film transistor. The alkylsilane laminate comprises an underlayer (Sub) having hydroxyl groups at the surface and an alkylsilane thin film (AS) formed on this underlayer. The alkylsilane laminate is a laminate wherein the critical surface energy Ec of the alkylsilane thin film and the number of carbons (X) of the alkylsilane satisfies the following formula (1): Ec?29.00?0.63x (mN/m) (1) Also provided is a thin-film transistor (10) having such an alkylsilane laminate (Sub, AS).

Abstract: A thin film transistor TFT, including a substrate, a gate electrode on the substrate, a gate insulating layer on the gate electrode, an active layer on the gate insulating layer, the active layer corresponding to the gate electrode and including a channel region, source and drain electrodes contacting the active layer, the source and drain electrodes being separate from each other, and an ohmic contact layer between the active layer and at least one of the source and drain electrodes, the ohmic contact layer including an oxide semiconductor material.