Abstract: Manufacturing an array substrate includes forming data and gate lines which cross and a gate electrode on a substrate. The data line is discontinuously disposed to be separated from the gate line, or the gate line is discontinuously disposed to be separated from the data line. Active and gate insulating layers including bridge and source electrode vias are formed on the substrate. The bridge vias correspond to adjacent discontinuous sections of the data line or the gate line. The source electrode via corresponds to the data line. Pixel, source, and drain electrodes and a bridge line are formed on the substrate. The pixel electrode and the drain electrode are integral. The source electrode is connected to the data line through the source electrode via. The bridge line connects adjacent discontinuous sections of the data line or adjacent discontinuous sections of the gate line through bridge vias.

Abstract: An active device and a fabricating method thereof are provided. The active device includes a buffer layer, a channel, a gate, a gate insulation layer, a source and a drain. The buffer layer is disposed on a substrate and has a positioning region. A thickness of a portion of the buffer layer in the positioning region is greater than a thickness of a portion of the buffer layer outside the positioning region. The channel is disposed on the buffer layer and in the positioning region. The gate is disposed above the channel. The gate insulation layer is disposed between the channel and the gate. The source and the drain are disposed above the channel and electrically connected to the channel.

Abstract: This invention provides a semiconductor device having high operation performance and high reliability. An LDD region 707 overlapping with a gate wiring is arranged in an n-channel TFT 802 forming a driving circuit, and a TFT structure highly resistant to hot carrier injection is achieved. LDD regions 717, 718, 719 and 720 not overlapping with a gate wiring are arranged in an n-channel TFT 804 forming a pixel unit. As a result, a TFT structure having a small OFF current value is achieved. In this instance, an element belonging to the Group 15 of the Periodic Table exists in a higher concentration in the LDD region 707 than in the LDD regions 717, 718, 719 and 720.

Abstract: A thin film transistor display panel includes a substrate, a gate wire on the substrate and including a gate line and a gate electrode; a gate insulating layer on the gate wire; a semiconductor layer on the gate insulating layer; a data wire including a source electrode on the semiconductor layer, a drain electrode opposing the source electrode with respect to the gate electrode, and a data line; a passivation layer on the data wire having a contact hole exposing the drain electrode; and a pixel electrode on the passivation layer and connected to the drain electrode through the contact hole. The gate wire has a first region and second region where the gate line and the gate electrode are positioned, respectively. The thickness of the gate wire in the first region is greater than the thickness of the gate wire in the second region.

Abstract: A display apparatus includes a first substrate including pixels, a second substrate facing the first substrate, and a liquid crystal layer interposed between the first substrate and the second substrate. Each of the pixels includes a thin film transistor disposed on a first insulating substrate, a first protective layer that covers the thin film transistor and includes a SiOC layer, a first electrode disposed on the first protective layer, a second protective layer that covers the first electrode, and a second electrode disposed on the second protective layer.

Abstract: A semiconductor device in which defects in characteristics due to electrostatic discharge is reduced and a method for manufacturing the semiconductor device are provided. The semiconductor device has at least one of these structures: (1) a structure in which a first and second insulating films are in direct contact with each other in a peripheral region of a circuit portion, (2) a structure in which a first and second insulators are closely attached to each other, and (3) a structure in which a first conductive layer and a second conductive layer are provided on outer surfaces of the first insulator and the second insulator, respectively, and electrical conduction between the first and second conductive layers is achieved at a side surface of the peripheral region. Note that the conduction at the side surface can be achieved by cutting a plurality of semiconductor devices into separate semiconductor devices.

Abstract: A display substrate having a low resistance signal line and a method of manufacturing the display substrate are provided. The display substrate includes an insulation substrate, a gate line, a data line and a pixel electrode. The gate line gate line is formed through a sub-trench and an opening portion. The sub-trench is formed in the insulation substrate and the opening portion is formed through a planarization layer on the insulation substrate at a position corresponding to the position of the sub-trench. The data line crosses the gate line. The pixel electrode is electrically connected to the gate line and the data line through a switching element. Thus, a signal line is formed through a trench formed by using a planarization layer and an insulation substrate, so that a resistance of the signal line may be reduced.

Abstract: A method of forming a conductive pattern includes forming a trench on a substrate, and providing a conductive ink to the trench while an electric field is generated between the substrate and a nozzle which ejects the conductive ink.

Abstract: Provided is an array substrate including a base substrate, a thin film transistor having a semiconductor layer disposed on a first part of the base substrate. The semiconductor layer includes a source electrode and a drain electrode, a gate electrode disposed on the semiconductor layer and insulated from the semiconductor layer. A light-blocking layer disposed between the base substrate and the thin film transistor. The light-blocking layer comprises a first layer continuously disposed on and around the first part of the base substrate, and a second layer formed on the first part of the base substrate without extending outside of the first part, the second layer being disposed on the first layer.

Abstract: A method is provided for consuming oxides in a silicon (Si) nanoparticle film. The method forms a colloidal solution film of Si nanoparticles overlying a substrate. The Si nanoparticle colloidal solution film is annealed at a high temperature in the presence of titanium (Ti). In response to the annealing, Si oxide is consumed in a resultant Si nanoparticle film. In one aspect, the consuming the Si oxide in the Si nanoparticle film includes forming Ti oxide in the Si nanoparticle film. Also in response to a low temperature annealing, solvents are evaporated in the colloidal solution film of Si nanoparticles. Si and Ti oxide molecules are sintered in the Si nanoparticle film in response to the high temperature annealing.

Abstract: A method of manufacturing a thin film transistor includes: forming a gate electrode on a substrate; forming a gate insulating layer on the gate electrode; forming an organic semiconductor layer on the gate insulating layer; forming an organic semiconductor pattern by selectively removing part of the organic semiconductor layer by means of a laser ablation method; and forming source and drain electrodes on the organic semiconductor pattern.

Abstract: Discussed is a display device. The display device includes a thin film transistor, a first protective layer, a second protective layer, a pixel electrode, a connection line, a third protective layer, and a common electrode.

Abstract: It is an object to manufacture a highly reliable semiconductor device including a thin film transistor whose electric characteristics are stable. An insulating layer which covers an oxide semiconductor layer of the thin film transistor contains a boron element or an aluminum element. The insulating layer containing a boron element or an aluminum element is formed by a sputtering method using a silicon target or a silicon oxide target containing a boron element or an aluminum element. Alternatively, an insulating layer containing an antimony (Sb) element or a phosphorus (P) element instead of a boron element covers the oxide semiconductor layer of the thin film transistor.

Abstract: An object is to reduce an occupied area of a protection circuit. Another object is to increase the reliability of a display device including the protection circuit. The protection circuit includes a first wiring over a substrate, an insulating film over the first wiring, and a second wiring over the insulating film.

Abstract: A thin film transistor includes a gate terminal, an insulation layer formed on the gate terminal, a first semiconductor silicon layer formed on the insulation layer, a source terminal formed on the first semiconductor silicon layer, and a drain terminal. The drain terminal is partially located on the insulation layer and the first semiconductor silicon layer. The drain terminal and the gate terminal overlap each other via the insulation layer to form a first overlap region and also overlap each other via the first semiconductor silicon layer and the insulation layer to form a second overlap region. The first and second overlap regions respectively generate first and second parasitic capacitances. The thin film transistor includes a compensation structure, whereby when the drain terminal is shifted with respect to the gate terminal, the compensation structure maintaining area of the first overlap region and area of the second overlap region unchanged.

Abstract: Photosensing transistors, display panels employing a photosensing transistor, and methods of manufacturing the same, include a gate layer, a gate insulation layer on the gate layer, a channel layer on the gate insulation layer, an etch stop layer on a partial area of the channel layer, a source and a drain on the channel layer and separated from each other with the etch stop layer being interposed between the source and the drain, and a passivation layer covering the source, the drain, and the etch stop layer, wherein the source is separated from the etch stop layer.

Abstract: The invention relates to an electronic device including a sequence of a first thin film transistor (TFT) and a second TFT, the first TFT including a first set of electrodes separated by a first insulator, the second TFT comprising a second set of electrodes separated by a second insulator, wherein the first set of electrodes and the second set of electrodes are formed from a first shared conductive layer and a second shared conductive layer, the first insulator and the second insulator being formed by a shared dielectric layer. The invention further relates to a method of manufacturing an electronic device.

Abstract: In a method of manufacturing a thin film transistor, a gate electrode is formed on a first surface of a base substrate, a oxide semiconductor layer, insulation layer and photo resist layer are formed an the fast surface of the base substrate having the gate electrode. The insulation layer and the oxide semiconductor layer are patterned using a first photo resist pattern to form an etch-stopper and an active pattern. A source and a drain electrode are formed on the base substrate having the active pattern and the etch-stopper, the source electrode and the drain electrode are overlapped with both ends of the etch-stopper and spaced apart from each other. Therefore, a manufacturing cost may be decreased by omitting a mask when forming the active pattern and the etch-stopper.

Abstract: A liquid crystal display array substrate and a method for manufacturing the same are discussed. The liquid crystal display array substrate includes a gate line arranged on a substrate in one direction, a data line which crosses the gate line and defines a plurality of pixel areas, a thin film transistor formed at a crossing of the gate line and the data line, a pixel electrode connected to the thin film transistor, and a common electrode which is positioned opposite the pixel electrode and forms an electric field. The common electrode includes a shield line overlapping the data line, and the shield line includes at least two cutting portions having a width less than other portion of the shield line.

Abstract: A display substrate includes a gate wire formed on an insulating substrate, a semiconductor pattern formed on the gate wire and containing a metal oxynitride compound, and a data wire formed on the semiconductor pattern to cross the gate wire. The semiconductor pattern has a carrier number density ranging from 1016/cm3 to 1019/cm3.

Abstract: An organic light-emitting display device including a thin film transistor (TFT) on a substrate; an organic light emitting diode (OLED) electrically connected to the TFT, the OLED including a pixel electrode, an organic layer, and an opposite electrode; a pixel defining layer (PDL) on the pixel electrode, the PDL including an opening that exposes at least one portion of the pixel electrode; and a light scattering layer between the pixel electrode and the organic layer.

Abstract: A pixel structure and a fabrication method thereof are provided. A scan line, a gate, an oxide conductor layer, a metal conductor layer, an oxide semiconductor layer, and an insulation layer between the gate and the metal conductor layer are formed on a substrate. The oxide conductor layer includes a pixel electrode and a first auxiliary pattern partially overlapped with where the gate is. The first auxiliary pattern includes a first metal contact portion and a first semiconductor contact portion. The metal conductor layer includes a data line, a source connected to the data line, and a drain separated from the source. The drain contacts the first metal contact portion, exposes the first semiconductor contact portion between the source and the drain, and is electrically connected to the pixel electrode. The oxide semiconductor layer is connected between the source and the drain and contacts the first semiconductor contact portion.

Abstract: A TFT includes a supporting substrate, a gate electrode formed on the supporting substrate, a gate insulation film formed on the substrate so as to cover the gate electrode, a first semiconductor layer formed across from the gate electrode with respect to the gate insulation film, a second semiconductor layer formed on the first semiconductor layer, and having a first thickness and a second thickness which is greater than the first thickness, an ohmic contact layer formed on the second semiconductor layer, and a source electrode and a drain electrode formed on the ohmic contact layer, spacing apart with each other.

Abstract: A semiconductor display device is formed including an interlayer insulating. Specifically, a TFT is formed and then a nitrogen-containing inorganic insulating film that transmits less moisture compared to organic resin film is formed so as to cover the TFT. Next, organic resin including photosensitive acrylic resin is applied and an opening is formed by partially exposing the organic resin film to light. The organic resin film where the opening is formed, is then covered with a nitrogen-containing inorganic insulating film which transmits less moisture than organic resin film does. Thereafter, the gate insulating film and the two layers of the nitrogen-containing inorganic insulating films are partially etched away in the opening of the organic resin film to expose the active layer of the TFT.

Abstract: The present invention provides a pixel structure including a substrate, a common line, a first transparent electrode, an insulating layer, a drain, and a second transparent electrode. The common line is disposed on the substrate, and the first transparent electrode is disposed on the substrate and the common line and electrically connected to the common line. The insulating layer covers the substrate and the first transparent electrode, and the drain is disposed on the insulating layer. The second transparent electrode is disposed on the insulating layer and overlaps the first transparent electrode, and the second transparent electrode is in contact with the drain.

Abstract: A transistor may include a hole blocking layer between a channel layer including oxynitride and an electrode electrically connected to the channel layer. The hole blocking layer may be disposed in a region between the channel layer and at least one of a source electrode and a drain electrode. The channel layer may include, for example, zinc oxynitride (ZnON). A valence band maximum energy level of the hole blocking layer may be lower than a valence band maximum energy level of the channel layer.

Abstract: A thin film transistor includes a substrate, a source electrode and a drain electrode formed on the substrate, a channel layer formed between the source electrode and the drain electrode, an insulative layer covering the channel layer and a gate electrode formed on the insulative layer. An atomic-doping layer is formed in the channel layer. The atomic-doping layer is delta-doping with no more than one layer of atom.

Abstract: A thin film transistor array panel according to an exemplary embodiment of the present invention includes: a gate electrode disposed on an insulation substrate; a gate insulating layer disposed on the gate electrode; a semiconductor disposed on the gate insulating layer; an etching stop layer disposed on the semiconductor; an insulating layer disposed on the gate insulating layer; and a source electrode and a drain electrode overlapping the semiconductor. The semiconductor and the gate insulating layer have a first portion on which the etching stop layer and the insulating layer are disposed, and a second portion on which etching stop layer and the insulating layer are not disposed. The source electrode and the drain electrode are disposed on the second portion of the semiconductor and the gate insulating layer.

Abstract: A transistor device having a metallic source electrode, a metallic drain electrode, a metallic gate electrode and a channel in a deposited semiconductor material, the transistor device comprising: a first layer comprising the metallic gate electrode, a first metal portion of the metallic source electrode and a first metal portion of the metallic drain electrode; a second layer comprising a second metal portion of the metallic source electrode, a second metal portion of the metallic drain electrode, the deposited semiconductor material and dielectric material between the semiconductor material and the metallic gate electrode; and a third layer comprising a substrate, wherein the first, second and third layers are arranged in order such that the second layer is positioned between the first layer and the third layer.

Abstract: A thin film transistor array panel and a manufacturing method thereof according to an exemplary embodiment of the present invention form a contact hole in a second passivation layer formed of an organic insulator, protect a side of the contact hole by covering with a protection member formed of the same layer as the first field generating electrode and formed of a transparent conductive material, and etch the first passivation layer below the second passivation layer using the protection member as a mask. Therefore, it is possible to prevent the second passivation layer formed of an organic insulator from being overetched while etching the insulating layer below the second passivation layer so that the contact hole is prevented from being made excessively wide.

Abstract: A disposable dielectric structure is formed on a semiconductor-on-insulator (SOI) substrate such that all physically exposed surfaces of the disposable dielectric structure are dielectric surfaces. A semiconductor material is selectively deposited on semiconductor surfaces, while deposition of any semiconductor material on dielectric surfaces is suppressed. After formation of at least one gate spacer and source and drain regions, a planarization dielectric layer is deposited and planarized to physically expose a top surface of the disposable dielectric structure. The disposable dielectric structure is replaced with a replacement gate stack including a gate dielectric and a gate conductor portion. Lower external resistance can be provided without impacting the short channel performance of a field effect transistor device.

Abstract: Non-planar Metal Oxide Field Effect Transistors (MOSFETs) and methods for making non-planar MOSFETs with asymmetric, recessed source and drains having improved extrinsic resistance and fringing capacitance. The methods include a fin-last, replacement gate process to form the non-planar MOSFETs and employ a retrograde metal lift-off process to form the asymmetric source/drain recesses. The lift-off process creates one recess which is off-set from a gate structure while a second recess is aligned with the structure. Thus, source/drain asymmetry is achieved by the physical structure of the source/drains, and not merely by ion implantation. The resulting non-planar device has a first channel of a fin contacting a substantially undoped area on the drain side and a doped area on the source side, thus the first channel is asymmetric. A channel on atop surface of a fin is symmetric because it contacts doped areas on both the drain and source sides.

Abstract: A thin film transistor substrate for a liquid crystal display device includes a substrate, a metal layer on the substrate, and an aluminum complex oxide layer on the metal layer. The aluminum complex oxide layer comprises at least one selected from the group consisting of zirconium, tungsten, chromium and molybdenum. A passivation layer is formed on the aluminum complex oxide layer through a dipping process.

Abstract: A thin film transistor is provided. The transistor includes a gate; a first passivation layer covering the gate; a channel layer disposed on the first passivation layer; a source and a drain that are disposed on the first passivation layer and contact two sides of the channel layer; a second passivation layer covering the channel layer, the source, and the drain; first and second transparent electrode layers that are disposed on the second passivation layer and spaced apart from each other; a first transparent conductive via that penetrates the second passivation layer and connects the source and the first transparent electrode layer; and a second transparent conductive via that penetrates the second passivation layer and connects the drain and the second transparent electrode layer. A cross-sectional area of the gate is larger than a cross-sectional area of the channel layer, the source, and the drain combined.

Abstract: A method of forming a semiconductor device including forming well trenches on opposing sides of a gate structure by removing portions of a semiconductor on insulator (SOI) layer of an semiconductor on insulator (SOI) substrate, wherein the base of the well trenches is provided by a surface of a buried dielectric layer of the SOI substrate and sidewalls of the well trenches are provided by a remaining portion of the SOI layer. Forming a dielectric fill material at the base of the well trenches, wherein the dielectric fill material is in contact with the sidewalls of the well trenches and at least a portion of the surface of the buried dielectric layer that provides the base of the well trenches. Forming a source region and a drain region in the well trenches with an in-situ doped epitaxial semiconductor material.

Abstract: A thin film transistor is provided. The thin film transistor disposed on a substrate includes a gate electrode, a gate dielectric layer, a patterned semiconductor layer, a source electrode, a drain electrode covered with an anticorrosive conductive layer, a patterned passivation layer and a transparent conductive layer. The anticorrosive conductive layer includes indium tin oxide or indium zinc oxide, and is used to prevent the drain electrode from being over etched during the process of etching the passivation layer. A method for manufacturing the thin film transistor is also provided herein.

Abstract: The present invention discloses a thin film transistor array substrate and a manufacturing method for the same. A transparent conductive layer and a first metal layer are deposited on a substrate, and a multi-tone mask is utilized to form a gate electrode and a common electrode. A gate insulative layer and a semi-conductive layer are deposited on the substrate with the gate electrode and the common electrode, and the semi-conductive layer is patterned by a second mask to retain a region of the semi-conductive layer that is there-above the gate electrode. A second metal layer is deposited on the substrate with the gate insulative layer along with the retained semi-conductive layer, and the second metal layer is patterned by a third mask to form a source electrode, a drain electrode, and a pixel electrode. The present invention provides a simple manufacturing method.

Abstract: A thin film transistor (TFT) array substrate includes a TFT including an active layer, a gate electrode, source and drain electrodes, a first insulating layer between the active layer and the gate electrode, and a second insulating layer and a third insulating layer between the gate electrode and the source and drain electrodes, the first insulating layer and the second insulating layer extending in the TFT, a pixel electrode including a transparent conductive oxide material, the pixel electrode being on the first insulating layer and the second insulating layer and being connected to the source or drain electrodes via an opening in the third insulating layer, a capacitor including a first electrode on a same layer as the gate electrode and a second electrode on a same layer as the pixel electrode; and a fourth insulating layer covering the source and drain electrodes and exposing the pixel electrode via an opening.

Abstract: A planar semiconductor device including a semiconductor on insulator (SOI) substrate with source and drain portions having a thickness of less than 10 nm that are separated by a multi-layered strained channel. The multi-layer strained channel of the SOI layer includes a first layer with a first lattice dimension that is present on the buried dielectric layer of the SOI substrate, and a second layer of a second lattice dimension that is in direct contact with the first layer of the multi-layer strained channel portion. A functional gate structure is present on the multi-layer strained channel portion of the SOI substrate. The semiconductor device having the multi-layered channel may also be a finFET semiconductor device.

Abstract: The present invention provides a thin film transistor (TFT) array substrate and a method for manufacturing the same. After depositing a first metal layer on a substrate, a first mask is utilized to form gate electrodes. After depositing a gate insulating layer and a semiconductor layer on the substrate, a second mask is utilized to pattern the semiconductor layer, so as to keep portions of the semiconductor layer above the gate electrodes. After depositing a transparent and electrically conductive layer and a second metal layer on the substrate, a multi tone mask is utilized to form source electrodes, drain electrodes, pixel electrodes and common electrodes. The present invention can simplify the manufacturing process thereof.

Abstract: An active matrix substrate (2) is provided with first connecting wirings (641, 643, 645, 647) connected to gate terminals (51) to which extraction wirings (611, 613, 615, 617) are connected, second connecting wirings (642, 644, 646) connected to gate terminals (51) to which extraction wirings (612, 614, 616) are connected, bundled wirings (651 to 654) each composed of a mutually adjacent first connecting wiring and second connecting wiring bunched together, a first inspection wiring (66) capable of inputting an inspection signal to bunched wirings (652, 654) that are not adjacent to each other among the bundled wirings, and a second inspection wiring (67) capable of inputting an inspection signal to bundled wirings (651, 653) that are not adjacent to each other and not connected to the first inspection wiring (66) among the bundled wirings.

Abstract: A TFT array substrate includes a substrate, at least one gate line and gate electrode, a gate insulating layer, and at least one channel component, source electrode, drain electrode and data line. The gate line and gate electrode are disposed on the substrate, wherein both of the gate line and gate electrode have first and second conductive layers, the first conductive layer is formed on the substrate, the first conductive layer contains molybdenum nitride , the second conductive layer is formed on the first conductive layer, and the second conductive layer contains copper. The gate insulating layer is disposed on the gate line, gate electrode and the substrate. The channel component is disposed on the gate insulating layer. The source electrode and drain electrode are disposed on the channel component, and data line is disposed on the gate insulating layer.

Abstract: An array substrate includes scan lines and data lines defining pixel structures. Each pixel structure includes a first TFT, a second TFT and a pixel electrode. The first TFT includes a first gate connected to the scan line, a first source disposed above and partially overlapping the first gate, and a first drain disposed above the first gate. An end of the first source is connected to the data line. The first drain has at least one first concavity in which the first source is disposed partially. The second TFT includes a second gate connected to the scan line, a second source disposed above the second gate and connected to the first drain, and a second drain disposed above and partially overlapping the second gate. The second source has at least one second concavity in which the second drain is disposed partially. The pixel electrode connects to the second drain.

Abstract: A thin film transistor with which oxygen is easily supplied to an oxide semiconductor layer and favorable transistor characteristics are able to be restored and a display unit including the same. The thin film transistor includes, sequentially over a substrate, a gate electrode, a gate insulting film, an oxide semiconductor layer including a channel region, and a channel protective layer covering the channel region A source electrode and a drain electrode are formed on the oxide semiconductor layer located on both sides of the channel protective layer, and at least one of the source electrode and the drain electrode has an aperture to expose the oxide semiconductor layer.

Abstract: A thin film transistor includes a gate electrode formed on a substrate, a semiconductor pattern overlapped with the gate electrode, a source electrode overlapped with a first end of the semiconductor pattern and a drain electrode overlapped with a second end of the semiconductor pattern and spaced apart from the source electrode. The semiconductor pattern includes an amorphous multi-elements compound including a II B element and a VI A element or including a III A element and a V A element and having an electron mobility no less than 1.0 cm2/Vs and an amorphous phase, wherein the VI A element excludes oxygen. Thus, a driving characteristic of the thin film transistor may be improved.

Abstract: Provided is a display device that includes: a gate line disposed on a substrate, the gate line including a protruding gate electrode; a data line extending across the gate line, the data line having first and second segments spaced apart from each other; a semiconductor pattern overlapping with the gate electrode; a drain electrode that contacts a drain region of the semiconductor pattern and connects the first and second segments; a source electrode that contacts a source region of the semiconductor pattern; and a storage electrode overlapping with the data line.

Abstract: Provided is a structure for improved electrical signal isolation between adjacent devices situated in a top semiconductor layer of the structure and a method for the structure's fabrication. The structure comprises a gate situated on the top semiconductor layer, the top semiconductor layer situated over a base oxide layer, and the base oxide layer situated over a handle wafer. The top surface of the handle wafer is amorphized by an inert implant of Xenon or Argon to reduce carrier mobility in the handle wafer and improve electrical signal isolation between the adjacent devices situated in the top semiconductor layer.

Abstract: A semiconductor device includes: a substrate, a semiconductor layer including an oxide semiconductor disposed on the substrate, a barrier layer disposed on the semiconductor layer and an insulating layer disposed on the barrier layer. The semiconductor layer includes an oxide semiconductor, and the barrier layer includes a material having a lower standard electrode potential than a semiconductor material of the oxide semiconductor, a lower electron affinity than the semiconductor material of the oxide semiconductor, or a larger band gap than the semiconductor material of the oxide semiconductor. The insulating layer includes at least one of a silicon-based oxide or a silicon-based nitride, and the insulating layer includes a portion which contacts with an upper surface of the barrier layer.

Abstract: An organic light-emitting display apparatus comprises: a substrate in which a pixel region is defined; a thin film transistor (TFT) disposed on the substrate and spaced apart from the pixel region; a planarization pattern covering the TFT and spaced apart from the pixel region; a first electrode electrically connected to the TFT and formed so as to correspond to at least the pixel region; a pixel-defining layer formed on the first electrode so as to expose a predetermined region of the first electrode; an intermediate layer connected to the exposed region of the first electrode, including an organic emission layer, and formed to correspond to at least the pixel region; and a second electrode electrically connected to the intermediate layer.

Abstract: A pixel structure including a semiconductor layer having at least one source region and at least one drain region; a first insulating layer covering the semiconductor layer; a first conductive layer on the first insulating layer and including at least one gate; a second insulating layer covering the first conductive layer; a second conductive layer on the second insulating layer and including at least one source electrode, at least one drain electrode and at least one bottom electrode, the source region, the source electrode, the drain region, the drain electrode and the gate forming at least one thin film transistor; a third insulating layer covering the second conductive layer; a third conductive layer on the third insulating layer and including at least one top electrode, the top electrode and the bottom electrode forming at least one capacitor; and a pixel electrode electrically connected to the thin film transistor.