Abstract: A method of forming a deposited film according to the present invention includes: introducing a starting gas into a discharge space in a reaction vessel; and applying electric power to generate discharge to decompose the starting gas, wherein, when a self-bias voltage value which is generated at an electrode applied with first electric power reaches a preset threshold, second electric power higher than the first electric power is applied to the electrode to change the self-bias voltage value to another self-bias voltage value larger in absolute value than the threshold, and the deposited film is formed.

Abstract: Methods and systems for growing uniform oxide layers include an example method including growing a first layer of oxide on first and second facets of the substrate, with the first facet having a faster oxide growth rate. The oxide is removed from the first facet and a second oxide layer is grown on the first and second facets. Removing the oxide from the first facet includes shielding the second facet and exposing the substrate to a deoxidizing condition. The second facet is then exposed to receive the second oxide layer. Areas having differing oxide thicknesses are also grown by repeatedly growing oxide layers, selectively shielding areas, and removing oxide from exposed areas.

Abstract: A TFT array panel includes: first and second gate members connected to each other; a gate insulating layer formed on the first and the second gate members; first and second semiconductor members formed on the gate insulating layer opposite the first and the second gate members, respectively; first and second source members connected to each other and located near the first and the second semiconductor members, respectively; first and second drain members located near the first and the second semiconductor members, respectively, and located opposite the first and the second source members with respect to the first and the second gate members, respectively; and a pixel electrode connected to the first and the second drain members. The first gate, semiconductor, source, and drain members form a first TFT, and the second gate, semiconductor, source, and drain members form a second TFT.

Abstract: A sapphire substrate includes a generally planar surface having a crystallographic orientation selected from the group consisting of a-plane, r-plane, m-plane, and c-plane orientations, and having a nTTV of not greater than about 0.037 ?m/cm2, wherein nTTV is total thickness variation normalized for surface area of the generally planar surface, the substrate having a diameter not less than about 9.0 cm.

Abstract: Only a region where TFTs constituting a high-performance circuit will be disposed in a precursor semiconductor film PCS on an insulating substrate GLS with an insulating layer UCL serving as an undercoat is irradiated with a first energy beam LSR so as to be poly-crystallized while growing crystal grains laterally. Further a second rapid thermal treatment is performed all over the panel so as to reduce defects in the crystal grains in a region PSI poly-crystallized by the aforementioned energy beam. Thus, a high-quality polycrystalline semiconductor thin film serving as TFTs for a high-performance circuit and having a high on-current, a low threshold value, a low variation and a sharp leading edge characteristic is obtained.

Abstract: A method of fabricating a polycrystalline silicon thin film transistor is disclosed. One embodiment of the method includes: forming an amorphous silicon layer on a panel; scanning a continuous wave laser beam having a wavelength range of about 600 to about 900 nm between a visible light range of a red color and a near infrared range onto the amorphous silicon layer to preheat the amorphous silicon layer; overlappingly scanning a pulse laser beam having a wavelength range of about 100 to about 550 nm between a visible light range and an ultraviolet range in addition to the continuous wave laser beam on the panel to melt the preheated amorphous silicon layer; and stopping scanning the pulse laser beam to crystallize the molten silicon layer.

Abstract: A process of manufacturing a package base of a power semiconductor device includes the following steps. Firstly, a semiconductor substrate including a first surface and a second surface is provided. Then, a portion of the semiconductor substrate is patterned and removed to form a recess on the first surface of the semiconductor substrate, which serves as a receiving space for receiving a power semiconductor element therein. Then, a conducting layer is overlaid on the first surface including the receiving space. Afterward, a portion of the conducting layer is patterned and removed to form a conducting structure to be electrically connected to the power semiconductor device.

Abstract: A semiconductor package includes a rewiring substrate and a semiconductor chip. The semiconductor chip includes: a first face with an active surface including integrated circuit devices and chip contact pads, a second face lying in a plane essentially parallel to the first face and side faces. Each side face of the semiconductor chip lies in a plane essentially perpendicular to the first and second faces. At least one edge between two mutually essentially perpendicular faces of the semiconductor chip includes a surface.

Abstract: A thin film transistor for a display device includes a substrate, a gate electrode formed on the substrate, a gate insulating layer formed on the gate electrode, a polycrystalline semiconductor formed on the gate insulating layer and overlapping the gate electrode, a source electrode partially overlapping the polycrystalline semiconductor, and a drain electrode partially overlapping the polycrystalline semiconductor. The polycrystalline semiconductor includes a plurality of first polycrystalline semiconductors that are doped with conductive impurities and a plurality of second polycrystalline semiconductors that are not doped with conductive impurities, and the first polycrystalline semiconductors are disposed between and connected in series with adjacent ones of the second polycrystalline semiconductors.

Abstract: A device structure and method for forming graded junction using a implant process. Embodiments of the invention comprise implanting ions into said silicon substrate to form doped regions adjacent to said gate. The orientation of the channel region in the Si crystal structure (channel direction <100>) in combination with the large angle tilt and twist implant process produce doped regions that have a more graded junction. The orientation and implant process creates more channeling of ions. The channeling of ions creates a more graded junction. When implemented on a HV MOS TX, the graded junction of the LDD increases the breakdown voltage. Another embodiment is a FET with an annular shaped channel region.