Comprising Only Group Iii-v Compound (epo) Patents (Class 257/E33.023)
-
Patent number: 8598685Abstract: A GaN single crystal substrate has a main surface with an area of not less than 10 cm2, the main surface has a plane orientation inclined by not less than 65° and not more than 85° with respect to one of a (0001) plane and a (000-1) plane, and the substrate has at least one of a substantially uniform distribution of a carrier concentration in the main surface, a substantially uniform distribution of a dislocation density in the main surface, and a photoelasticity distortion value of not more than 5×10?5, the photoelasticity distortion value being measured by photoelasticity at an arbitrary point in the main surface when light is applied perpendicularly to the main surface at an ambient temperature of 25° C. Thus, the GaN single crystal substrate suitable for manufacture of a GaN-based semiconductor device having a small variation of characteristics can be obtained.Type: GrantFiled: June 17, 2010Date of Patent: December 3, 2013Assignee: Sumitomo Electric Industries, Ltd.Inventors: Shinsuke Fujiwara, Koji Uematsu, Hideki Osada, Seiji Nakahata
-
Patent number: 8597961Abstract: A method for improving internal quantum efficiency of a group-III nitride-based light emitting device is disclosed. The method includes the steps of: providing a group-III nitride-based substrate having a single crystalline structure; forming on the group-III nitride-based substrate an oxide layer, having a plurality of particles, without absorption of visible light, size, shape, and density of the particles are controlled by reaction concentration ratio of nitrogen/hydrogen, reaction time and reaction temperature; and growing a group-III nitride-based layer over the oxide layer; wherein the oxide layer prevents threading dislocation of the group-III nitride-based substrate from propagating into the group-III nitride-based layer, thereby improving internal quantum efficiency of the group-III nitride-based light emitting device.Type: GrantFiled: October 20, 2009Date of Patent: December 3, 2013Assignee: Walsin Lihwa CorporationInventors: Chang-Chi Pan, Ching-hwa Chang Jean, Jang-ho Chen
-
Patent number: 8597967Abstract: The present disclosure relates generally to semiconductor techniques. More specifically, embodiments of the present disclosure provide methods for efficiently dicing substrates containing gallium and nitrogen material. Additionally the present disclosure provide techniques resulting in a optical device comprising a substrate having three or more corners, where at least one of the corners is defined by a dislocation bundle characterized by a diameter of less than 100 microns, the gallium and nitrogen containing substrate having a predefined portion free from dislocation bundle centers, an active region containing one or more active layers, the active region being positioned within the predefined region; and a conductive region formed within the predefined region.Type: GrantFiled: November 17, 2011Date of Patent: December 3, 2013Assignee: Soraa, Inc.Inventors: Michael R. Krames, Tai Margalith, Rafael Aldaz
-
Patent number: 8592822Abstract: Provided are a light emitting device, a light emitting device package, and a lighting apparatus. The light emitting device includes: an n-type semiconductor layer including a first area and a second area in a plane; an n-type contact layer disposed on the n-type semiconductor layer and has a first thickness in the first area and a second thickness in the second area; an undoped semiconductor layer disposed on the n-type contact layer having the first thickness in the first area; an active layer disposed on the undoped semiconductor layer in the first area; a p-type semiconductor layer disposed on the active layer in the first area; a first electrode disposed on the n-type contact layer having the second thickness in the second area; and a second electrode disposed on the p-type semiconductor layer.Type: GrantFiled: February 2, 2012Date of Patent: November 26, 2013Assignee: LG Innotek Co., Ltd.Inventors: Ho Sang Yoon, Sung Hoon Jung
-
Publication number: 20130306964Abstract: A method of fabricating a light emitting diode device comprises providing a substrate, growing an epitaxial structure on the substrate. The epitaxial structure includes a first layer on the substrate, an active layer on the first layer and a second layer on the active layer. The method further comprises depositing a conductive and reflective layer on the epitaxial structure, forming a group of first trenches and a second trench. Each of the first and second trenches extends from surface of the conductive and reflective layer to the first layer to expose part of the first layer. The method further comprises depositing conductive material to cover a portion of the conductive and reflective layer to form a first contact pad, and cover surfaces between adjacent first trenches to form a second contact pad. The second contact pad electrically connects the first layer by filling the conductive material in the first trenches.Type: ApplicationFiled: May 17, 2012Publication date: November 21, 2013Applicant: Starlite LED IncInventor: Chang HAN
-
Publication number: 20130308309Abstract: Solid state transducer (“SST”) devices with selective wavelength reflectors and associated systems and methods are disclosed herein. In several embodiments, for example, an SST device can include a first emitter configured to emit emissions having a first wavelength and a second emitter configured to emit emissions having a second wavelength different from the first wavelength. The first and second emitters can be SST structures and/or converter materials. The SST device can further include a selective wavelength reflector between the first and second emitters. The selective wavelength reflector can be configured to at least substantially transmit emissions having the first wavelength and at least substantially reflect emissions having the second wavelength.Type: ApplicationFiled: May 17, 2012Publication date: November 21, 2013Applicant: Micron Technology, Inc.Inventors: Martin F. Schubert, Vladimir Odnoblyudov
-
Patent number: 8581283Abstract: A photoelectric device having Group III nitride semiconductor includes a conductive layer, a metallic mirror layer located on the conductive layer, and a Group III nitride semiconductor layer located on the metallic mirror layer. The Group III nitride semiconductor layer defines a number of microstructures thereon. Each microstructure includes at least one angled face, and the angled face of each microstructure is a crystal face of the Group III nitride semiconductor layer.Type: GrantFiled: January 28, 2011Date of Patent: November 12, 2013Assignee: Advanced Optoelectronic Technology, Inc.Inventors: Po-Min Tu, Shih-Cheng Huang, Wen-Yu Lin, Chih-Peng Hsu, Shih-Hsiung Chan
-
Publication number: 20130295704Abstract: Provided is a group-III nitride semiconductor laser device with a laser cavity of high lasing yield, on a semipolar surface of a support base in which the c-axis of a hexagonal group-III nitride is tilted toward the m-axis. First and second fractured faces to form the laser cavity intersect with an m-n plane. The group-III nitride semiconductor laser device has a laser waveguide extending in a direction of an intersecting line between the m-n plane and the semipolar surface. In a laser structure, a first surface is opposite to a second surface. The first and second fractured faces extend from an edge of the first surface to an edge of the second surface. The fractured faces are not formed by dry etching and are different from conventionally-employed cleaved facets such as c-planes, m-planes, or a-planes.Type: ApplicationFiled: December 22, 2011Publication date: November 7, 2013Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Yusuke YOSHIZUMI, Shimpei TAKAGI, Yohei ENYA, Takashi KYONO, Masahiro ADACHI, Masaki UENO, Takamichi SUMITOMO, Shinji TOKUYAMA, Koji KATAYAMA, Takao NAKAMURA, Takatoshi IKEGAMI
-
Publication number: 20130292687Abstract: The present invention relates to optoelectronic device layer structures, light emitting devices, and detectors based upon heterostructures formed between hexagonal boron nitride (hNB) and III nitrides, and more particularly, to heterojunction devices capable of emitting and detecting photons in the ultraviolet (UV) and extremely ultraviolet (RUV) spectral range. The present invention also relates to neutron detectors based on epitaxially grown hBN thin films (or epitaxial layers) and hBN stacked thin films (or epitaxial layers) to satisfy the thickness required for capturing all incoming neutrons.Type: ApplicationFiled: May 29, 2012Publication date: November 7, 2013Applicant: TEXAS TECH UNIVERSITY SYSTEMInventors: Hongxing Jiang, Sashikanth Majety, Rajendra Dahal, Jing Li, Jingyu Lin
-
Patent number: 8569085Abstract: A photoelectrochemical (PEC) etch is performed for chip shaping of a device comprised of a III-V semiconductor material, in order to extract light emitted into guided modes trapped in the III-V semiconductor material. The chip shaping involves varying an angle of incident light during the PEC etch to control an angle of the resulting sidewalls of the III-V semiconductor material. The sidewalls may be sloped as well as vertical, in order to scatter the guided modes out of the III-V semiconductor material rather than reflecting the guided modes back into the III-V semiconductor material. In addition to shaping the chip in order to extract light emitted into guided modes, the chip may be shaped to act as a lens, to focus its output light, or to direct its output light in a particular way.Type: GrantFiled: October 9, 2009Date of Patent: October 29, 2013Assignee: The Regents of the University of CaliforniaInventors: Adele Tamboli, Evelyn L. Hu, James S. Speck
-
Patent number: 8563997Abstract: A semiconductor light emitting device comprises a first nitride semiconductor layer comprising a flat top surface and a plurality of concave regions from the flat top surface, a reflector within the concave regions of the first semiconductor layer, and a second semiconductor layer on the first semiconductor layer.Type: GrantFiled: August 13, 2012Date of Patent: October 22, 2013Assignee: LG Innotek Co., Ltd.Inventor: Hung Seob Cheong
-
Patent number: 8552465Abstract: A device and method for making the same are disclosed. The device includes a substrate having a first TEC, a stress relief layer overlying the substrate, and crystalline cap layer. The crystalline cap layer overlies the stress relief layer. The cap layer has a second TEC different from the first TEC. The stress relief layer includes an amorphous material that relieves stress between the crystalline substrate and the cap layer arising from differences in the first and second TECs at a growth temperature at which layers are grown epitaxially on the cap layer. The device can be used to construct various semiconductor devices including GaN LEDs that are fabricated on silicon or SiC wafers. The stress relief layer is generated by converting a layer of precursor material on the substrate after the cap layer has been grown to a stress-relief layer.Type: GrantFiled: November 9, 2011Date of Patent: October 8, 2013Assignee: Toshiba Techno Center Inc.Inventor: Steven D. Lester
-
Publication number: 20130256650Abstract: A semiconductor device and fabrication method thereof are provided, wherein the fabrication method of the semiconductor device includes the following steps. Forming a semiconductor layer on a substrate, wherein the semiconductor layer has a top surface and a bottom surface that is opposite to the top surface. The bottom surface is in contact with the substrate, and the top surface has a plurality of pits, the pits are extended from the top surface toward the bottom surface. Preparing a solution, wherein the solution includes a plurality of nanoparticles. Filling the nanoparticles into the pits. Forming a conducting layer on the semiconductor layer after filling the nanoparticles into the pits.Type: ApplicationFiled: May 27, 2012Publication date: October 3, 2013Applicant: NATIONAL TAIWAN UNIVERSITYInventors: Chih-Chung Yang, Horng-Shyang Chen, Shao-Ying Ting, Che-Hao Liao, Chih-Yen Chen, Chieh Hsieh, Hao-Tsung Chen, Yu-Feng Yao, Dong-Ming Yeh
-
Patent number: 8541253Abstract: A method of fabricating a III-nitride semiconductor laser device includes: preparing a substrate with a semipolar primary surface, the semipolar primary surface including a hexagonal III-nitride semiconductor; forming a substrate product having a laser structure, an anode electrode, and a cathode electrode, the laser structure including a substrate and a semiconductor region, and the semiconductor region being formed on the semipolar primary surface; after forming the substrate product, forming first and second end faces; and forming first and second dielectric multilayer films for an optical cavity of the nitride semiconductor laser device on the first and second end faces, respectively.Type: GrantFiled: March 9, 2012Date of Patent: September 24, 2013Assignee: Sumitomo Electric Industries, Ltd.Inventors: Yusuke Yoshizumi, Yohei Enya, Takashi Kyono, Masahiro Adachi, Shinji Tokuyama, Takamichi Sumitomo, Masaki Ueno, Takatoshi Ikegami, Koji Katayama, Takao Nakamura
-
Patent number: 8525195Abstract: According to one embodiment, a semiconductor light emitting device includes n-type and p-type semiconductor layers, a light emitting portion, a multilayered structural body, and an n-side intermediate layer. The light emitting portion is provided between the semiconductor layers. The light emitting portion includes barrier layers containing GaN, and a well layer provided between the barrier layers. The well layer contains Inx1Ga1-x1N. The body is provided between the n-type semiconductor layer and the light emitting portion. The body includes: first layers containing GaN, and a second layer provided between the first layers. The second layer contains Inx2Ga1-x2N. Second In composition ratio x2 is not less than 0.6 times of first In composition ratio x1 and is lower than the first In composition x1. The intermediate layer is provided between the body and the light emitting portion and includes a third layer containing Aly1Ga1-y1N (0<y1?0.01).Type: GrantFiled: September 1, 2010Date of Patent: September 3, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Hajime Nago, Koichi Tachibana, Toshiki Hikosaka, Shigeya Kimura, Shinya Nunoue
-
Patent number: 8513040Abstract: According to one embodiment, a method is disclosed for manufacturing a display device. A film material layer is formed on a support substrate. A first heating process for the film material layer at a first temperature to form a film layer and a second heating process for a second region surrounding a first region at a second temperature higher than the first temperature are performed. The first region is provided in a central part of the film layer. A display layer is formed in the first region and a peripheral circuit section is formed at least in a part of the second region. A third heating process is performed for at least a part of the film layer at a third temperature higher than the second temperature. In addition, the film layer is peeled off from the support substrate.Type: GrantFiled: May 30, 2012Date of Patent: August 20, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Tatsunori Sakano, Kentaro Miura, Nobuyoshi Saito, Shintaro Nakano, Tomomasa Ueda, Hajime Yamaguchi
-
Patent number: 8513683Abstract: An optical integrated semiconductor light emitting device with improved light emitting efficiency is provided by preventing leak current from flowing through a high defect region of the substrate. The optical integrated semiconductor light emitting device includes: a substrate, in which in a low defect region made of crystal having a first average dislocation density, one or more high defect regions having a second average dislocation density higher than the first average dislocation density are included; and a Group III-V nitride semiconductor layer which is formed on the substrate, has a plurality of light emitting device structures, and has a groove in the region including the region corresponding to the high defect region (high defect region).Type: GrantFiled: January 31, 2006Date of Patent: August 20, 2013Assignee: Sony CorporationInventors: Osamu Maeda, Tsuyoshi Fujimoto, Motonobu Takeya, Toshihiro Hashidu, Masaki Shiozaki, Yoshio Oofuji
-
Publication number: 20130208267Abstract: Disclosed is a photoelectric conversion device which inhibits characteristic degradation caused by crystal defects, and an inspection method for crystal defects in photoelectric conversion devices. The photoelectric conversion device is provided with an active layer, and a deactivator contained in the active layer.Type: ApplicationFiled: March 14, 2011Publication date: August 15, 2013Inventors: Akihiko Yoshikawa, Yoshihiro Ishitani, Kazuhide Kusakabe
-
Patent number: 8507891Abstract: The present invention provides a Group III nitride semiconductor light-emitting device exhibiting improved emission performance and high electrostatic breakdown voltage. The Group III nitride semiconductor light-emitting device has a layered structure in which an n-type contact layer, an ESD layer, an n-type cladding layer, a light-emitting layer, a p-type cladding layer, and a p-type contact layer are deposited on a sapphire substrate. The ESD layer has a pit. The n-type cladding layer and the light-emitting layer are formed without burying the pit. The pit has a diameter of 110 nm to 150 nm at an interface between the n-type cladding layer and the light-emitting layer. The barrier layer of the light-emitting layer is formed of AlGaN having an Al composition ratio of 3% to 7%.Type: GrantFiled: February 6, 2012Date of Patent: August 13, 2013Assignee: Toyoda Gosei Co., Ltd.Inventor: Ryo Nakamura
-
Patent number: 8507305Abstract: A III-nitride semiconductor laser device is provided with a laser structure and an electrode. The laser structure includes a support base which includes a hexagonal III-nitride semiconductor and a semipolar primary surface, and a semiconductor region provided on the semipolar primary surface. The electrode is provided on the semiconductor region. The semiconductor region includes a first cladding layer of a first conductivity type GaN-based semiconductor, a second cladding layer of a second conductivity type GaN-based semiconductor, and an active layer provided between the first cladding layer and the second cladding layer.Type: GrantFiled: April 10, 2012Date of Patent: August 13, 2013Assignee: Sumitomo Electric Industries, Ltd.Inventors: Yusuke Yoshizumi, Yohei Enya, Takashi Kyono, Takamichi Sumitomo, Nobuhiro Saga, Masahiro Adachi, Kazuhide Sumiyoshi, Shinji Tokuyama, Shimpei Takagi, Takatoshi Ikegami, Masaki Ueno, Koji Katayama
-
Patent number: 8507929Abstract: One or more regions of graded composition are included in a III-P light emitting device, to reduce the Vf associated with interfaces in the device. In accordance with embodiments of the invention, a semiconductor structure comprises a III-P light emitting layer disposed between an n-type region and a p-type region. A graded region is disposed between the p-type region and a GaP window layer. The aluminum composition is graded in the graded region. The graded region may have a thickness of at least 150 nm. In some embodiments, in addition to or instead of a graded region between the p-type region and the GaP window layer, the aluminum composition is graded in a graded region disposed between an etch stop layer and the n-type region.Type: GrantFiled: June 16, 2008Date of Patent: August 13, 2013Assignee: Koninklijke Philips Electronics N.V.Inventors: Patrick N. Grillot, Rafael I. Aldaz, Eugene I. Chen, Sateria Salim
-
Patent number: 8494020Abstract: A semiconductor light emitting device downsized by devising arrangement of connection pads is provided. A second light emitting device is layered on a first light emitting device. The second light emitting device has a stripe-shaped semiconductor layer formed on a second substrate on the side facing to a first substrate, a stripe-shaped p-side electrode supplying a current to the semiconductor layer, stripe-shaped opposed electrodes that are respectively arranged oppositely to respective p-side electrodes of the first light emitting device and electrically connected to the p-side electrodes of the first light emitting device, connection pads respectively and electrically connected to the respective opposed electrodes, and a connection pad electrically connected to the p-side electrode. The connection pads are arranged in parallel with the opposed electrodes.Type: GrantFiled: April 13, 2012Date of Patent: July 23, 2013Assignee: Sony CorporationInventors: Yuji Furushima, Abe Hiroaki, Kudou Hisashi, Fujimoto Tsuyoshi, Kentaro Aoshima
-
Patent number: 8492787Abstract: This application discloses alight-emitting diode device, comprising an epitaxial structure having a light-emitting layer, a first-type conductivity layer, and a second-type conductivity layer wherein the thicknesses of the first-type conductivity confining layer is not equal to the second-type conductivity confining layer and the light-emitting layer is not overlapped with the portion of the epitaxial structure corresponding to the peak zone of the wave intensity distribution curve along the direction of the epitaxy growth.Type: GrantFiled: June 17, 2009Date of Patent: July 23, 2013Assignee: Epistar CorporationInventors: Ta-Cheng Hsu, Meng-Lun Tsai
-
Patent number: 8487317Abstract: This invention discloses a GaN semiconductor device comprising a substrate; a metal-rich nitride compound thin film on the substrate; a buffer layer formed on the metal-rich nitride compound thin film, and a semiconductor stack layer on the buffer layer wherein the metal-dominated nitride compound thin film covers a partial upper surface of the substrate. Because metal-rich nitride compound is amorphous, the epitaxial growth direction of the buffer layer grows upwards in the beginning and then turns laterally, and the epitaxy defects of the buffer layer also bend with the epitaxial growth direction of the buffer layer. Therefore, the probability of the epitaxial defects extending to the semiconductor stack layer is reduced and the reliability of the GaN semiconductor device is improved.Type: GrantFiled: March 27, 2009Date of Patent: July 16, 2013Assignee: Epistar CorporationInventors: Yi-Chieh Lin, Cheng-Ta Kuo, Yu-Pin Hsu, Chi-Ming Tsai
-
Patent number: 8486738Abstract: A light emitting device having auto-cloning photonic crystal structures comprises a substrate, a first semiconductor layer, an active emitting layer, a second semiconductor layer and a saw-toothed multilayer film comprising auto-cloning photonic crystal structures. The saw-toothed multilayer film provides a high reflection interface and a diffraction mechanism to prevent total internal reflection and enhance light extraction efficiency. The manufacturing methods of the light emitting device having auto-cloning photonic crystal structures are also presented.Type: GrantFiled: June 1, 2011Date of Patent: July 16, 2013Assignee: National Tsing Hua UniversityInventors: Shiuh Chao, Hao-Min Ku, Chen-Yang Huang
-
Patent number: 8482027Abstract: An epitaxial wafer for a light emitting diode, including a GaAs substrate, a light emitting unit provided on the GaAs substrate, and a strain adjustment layer provided on the light emitting unit, wherein the light emitting unit has a strained light emitting layer having a composition formula of (AlXGa1-X)YIn1-YP (wherein X and Y are numerical values that satisfy 0?X?0.1 and 0.39?Y?0.45 respectively), and the strain adjustment layer is transparent to the emission wavelength and has a lattice constant that is smaller than the lattice constant of the GaAs substrate. The invention provides an epitaxial wafer that enables mass production of a high-output and/or high-efficiency LED having an emission wavelength of not less than 655 nm.Type: GrantFiled: February 24, 2010Date of Patent: July 9, 2013Assignee: Showa Denko K.K.Inventors: Noriyoshi Seo, Atsushi Matsumura, Ryouichi Takeuchi
-
Patent number: 8476649Abstract: Various embodiments of light emitting dies and solid state lighting (“SSL”) devices with light emitting dies, assemblies, and methods of manufacturing are described herein. In one embodiment, a light emitting die includes an SSL structure configured to emit light in response to an applied electrical voltage, a first electrode carried by the SSL structure, and a second electrode spaced apart from the first electrode of the SSL structure. The first and second electrode are configured to receive the applied electrical voltage. Both the first and second electrodes are accessible from the same side of the SSL structure via wirebonding.Type: GrantFiled: December 16, 2010Date of Patent: July 2, 2013Assignee: Micron Technology, Inc.Inventors: Martin F. Schubert, Vladimir Odnoblyudov
-
Publication number: 20130161643Abstract: A method is provided for fabricating three-dimensional gallium nitride (GaN) pillar structures with planar surfaces. After providing a substrate, the method grows a GaN film overlying a top surface of the substrate and forms cavities in a top surface of the GaN film. The cavities are formed using a laser ablation, ion implantation, sand blasting, or dry etching process. The cavities in the GaN film top surface are then wet etched, forming planar sidewalls extending into the GaN film. More explicitly, the cavities are formed into a c-plane GaN film top surface, and the planar sidewalls are formed perpendicular to a c-plane, in the m-plane or a-plane family.Type: ApplicationFiled: December 27, 2011Publication date: June 27, 2013Inventors: Mark Albert Crowder, Changqing Zhan, Paul J. Schuele
-
Publication number: 20130163628Abstract: A process for forming a microstructure of a nitride semiconductor including (1) preparing a semiconductor structure which has a second semiconductor layer formed of a group III nitride semiconductor containing at least Al formed on a principal plane of a first semiconductor layer formed of a group III nitride semiconductor containing no Al, and which has a hole that penetrates through the second semiconductor layer and is formed in the first semiconductor layer; (2) subjecting the semiconductor structure to heat treatment under a gas atmosphere including a nitrogen element after step (1) to form a crystal plane of the group III nitride semiconductor containing no Al, on at least a part of a side wall of the hole; and (3) forming a third semiconductor layer formed of a group III nitride semiconductor on the second semiconductor layer after step (2) to cover the upper part of the hole.Type: ApplicationFiled: September 7, 2012Publication date: June 27, 2013Applicant: CANON KABUSHIKI KAISHAInventors: Katsuyuki Hoshino, Yasuhiro Nagatomo, Shoichi Kawashima, Takeshi Kawashima
-
Patent number: 8470626Abstract: Exemplary embodiments of the present invention relate to a method of fabricating a light emitting diode (LED). According to an exemplary embodiment of the present invention, the method includes growing a first GaN-based semiconductor layer on a substrate at a first temperature by supplying a chamber with a nitride source gas and a first metal source gas, stopping the supply of the first metal source gas and maintaining the first temperature for a first time period after stopping the supply of the first metal source gas, decreasing the temperature of the substrate to the a second temperature after the first time period elapses, growing an active layer of the first GaN-based semiconductor layer at the second temperature by supplying the chamber with a second metal source gas.Type: GrantFiled: June 1, 2011Date of Patent: June 25, 2013Assignee: Seoul Opto Device Co., Ltd.Inventors: Kwang Joong Kim, Chang Suk Han, Seung Kyu Choi, Ki Bum Nam, Nam Yoon Kim, Kyung Hae Kim, Ju Hyung Yoon
-
Publication number: 20130153918Abstract: A III-N on silicon LED constructed to emit light in the visible range includes a layer of single crystal III-N with a light emitting diode formed therein and designed to emit light at a first wavelength through a lower surface, a REO-Si template mated to the layer of single crystal III-N and designed to approximately crystal lattice match a silicon substrate, and a light emission layer of rare earth oxide selected to receive and absorb light at the first wavelength, up-convert the absorbed light, and re-emit light at a second wavelength in the visible range. The lower surface of the REO-Si template is either mated to the upper surface of a crystalline silicon substrate with the light emission layer integrated into the REO-Si template or mated to an upper surface of the light emission layer with a lower surface of the light emission layer mated to the crystalline silicon substrate.Type: ApplicationFiled: December 16, 2011Publication date: June 20, 2013Inventors: Andrew Clark, Michael Lebby
-
Publication number: 20130153920Abstract: According to an embodiment, a semiconductor light emitting device includes a light emitting body including a semiconductor light emitting layer, a support substrate supporting the light emitting body, and a bonding layer provided between the light emitting body and the support substrate, the bonding layer bonding the light emitting body and the support substrate together. The device also includes a first barrier metal layer provided between the light emitting body and the bonding layer, and an electrode provided between the light emitting body and the first barrier metal layer. The first barrier layer includes a first layer made of nickel and a second layer made of a metal having a smaller linear expansion coefficient than nickel, and the first layer and the second layer are alternately disposed in a multiple-layer structure. The electrode is electrically connected to the light emitting body.Type: ApplicationFiled: May 15, 2012Publication date: June 20, 2013Applicant: Kabushiki Kaisha ToshibaInventor: Yasuharu SUGAWARA
-
Patent number: 8455882Abstract: A light emitting device and method of fabricating the same is disclosed that comprises at least one light emitter comprising an active region which emits light. The device further comprising a submount arranged such that the at least one light emitter is mounted to the submount such that the active region is angled in relation to the submount.Type: GrantFiled: September 30, 2011Date of Patent: June 4, 2013Assignee: Cree, Inc.Inventor: Zhimin Jamie Yao
-
Patent number: 8450748Abstract: A light emitting device comprises: an LED chip array comprising a plurality of LEDs formed on a single die (monolithic chip array) and at least one discrete LED that is separate from the LED chip array connected in series with the LED chip array. In an AC-drivable device the LED chip array is AC-drivable and two or more discrete LEDs are configured to be AC-drivable. The device can further comprise a package in which the LED chip array and discrete LED(s) are mounted. The discrete LEDs are configured such that positive and negative half wave periods of an AC drive voltage are mapped onto oppositely connected LED such that oppositely connected LED chips are alternately operable on a respective half wave period.Type: GrantFiled: July 8, 2010Date of Patent: May 28, 2013Assignee: InterLight Optotech CorporationInventors: Hwa Su, Hsi-Yan Chou, Yu-Min Li, Yu-Chou Hu, Chih Wei Huang, Tzu-Chi Cheng
-
Patent number: 8450767Abstract: This disclosure discloses a light-emitting device. The light-emitting device comprises: a substrate; and a first light-emitting unit comprising a plurality of light-emitting diodes electrically connected to each other on the substrate. A first light-emitting diode in the first light-emitting unit comprises a first semiconductor layer with a first conductivity-type, a second semiconductor layer with a second conductivity-type, and a light-emitting stack formed between the first and second semiconductor layers. The first light-emitting diode in the first light-emitting unit further comprises a first connecting layer on the first semiconductor layer for electrically connecting to a second light-emitting diode in the first light-emitting unit; a second connecting layer, separated from the first connecting layer, formed on the first semiconductor layer; and a third connecting layer on the second semiconductor layer for electrically connecting to a third light-emitting diode in the first light-emitting unit.Type: GrantFiled: January 12, 2011Date of Patent: May 28, 2013Assignee: Epistar CorporationInventors: Huang-Chien Fu, Shih-I Chen, Yi Ming Chen, Tzu Chieh Hsu, Jhih-Sian Wang
-
Patent number: 8435880Abstract: In a method for manufacturing a semiconductor device, the method includes the step of growing a nitride-based III-V compound semiconductor layer, which forms a device structure, directly on a substrate without growing a buffer layer, the substrate being made of a material with a hexagonal crystal structure and having a principal surface that is oriented off at an angle of not less than ?0.5° and not more than 0° from an R-plane with respect to a direction of a C-axis.Type: GrantFiled: October 18, 2010Date of Patent: May 7, 2013Assignee: Sony CorporationInventors: Akira Ohmae, Kota Tokuda, Masayuki Arimochi, Nobuhiro Suzuki, Michinori Shiomi, Tomonori Hino, Katsunori Yanashima
-
Publication number: 20130099277Abstract: A method of selective dry etching of N-face (Al,In,Ga)N heterostructures through the incorporation of an etch-stop layer into the structure, and a controlled, highly selective, etch process. Specifically, the method includes: (1) the incorporation of an easily formed, compatible etch-stop layer in the growth of the device structure, (2) the use of a laser-lift off or similar process to decouple the active layer from the original growth substrate, and (3) the achievement of etch selectivity higher than 14:1 on N-face (Al,In,Ga)N.Type: ApplicationFiled: October 25, 2012Publication date: April 25, 2013Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIAInventor: The Regents of the University of California
-
Publication number: 20130095591Abstract: A manufacturing method of a solid state light emitting element is provided. A plurality of protrusion structures separated to each other are formed on a first substrate. A buffer layer is formed on the protrusion structures and fills the gaps between protrusion structures. An epitaxial growth layer is formed on the buffer layer to form a first semiconductor stacking structure. The first semiconductor stacking structure is inverted to a second substrate, so that the first semiconductor epitaxial layer and the second substrate are connected to form a second semiconductor stacking structure. The buffer layer is etched by a first etchant solution to form a third semiconductor stacking structure. A second etchant solution is used to permeate through the gaps between the protrusion structures, so that the protrusion structures are etched completely. The first substrate is removed from the third semiconductor stacking structure to form a fourth semiconductor stacking structure.Type: ApplicationFiled: April 10, 2012Publication date: April 18, 2013Applicant: Lextar Electronics CorporationInventors: Chang-Chin Yu, Mong-Ea Lin
-
Publication number: 20130087780Abstract: A group III nitride semiconductor light emitting diode is revealed. A layered structure composed of group III nitrides is formed on the substrate through epitaxy growth of a hexagonal wurtzite crystal structure. The layered structure includes a n-type semiconductor layer, a light emitting layer on the n-type semiconductor layer, and a p-type semiconductor layer on the light emitting layer. A first electrode metal pad is formed on the p-type semiconductor layer and a second electrode metal pad on the n-type semiconductor layer. A direction from the first electrode metal pad to the second electrode metal pad is the same with that of C-axis [0001] of the hexagonal wurtzite crystal structure so as to speed up the movement of electron-hole and improve the combination efficiency of electron-hole by the electric field along the direction of C-axis [0001] in the hexagonal wurtzite crystal structure.Type: ApplicationFiled: October 7, 2011Publication date: April 11, 2013Applicant: SOUTHERN TAIWAN UNIVERSITY OF TECHNOLOGYInventor: YU-ZUNG CHIOU
-
Patent number: 8415707Abstract: A Group III nitride semiconductor device has a semiconductor region, a metal electrode, and a transition layer. The semiconductor region has a surface comprised of a Group III nitride crystal. The semiconductor region is doped with a p-type dopant. The surface is one of a semipolar surface and a nonpolar surface. The metal electrode is provided on the surface. The transition layer is formed between the Group III nitride crystal of the semiconductor region and the metal electrode. The transition layer is made by interdiffusion of a metal of the metal electrode and a Group III nitride of the semiconductor region.Type: GrantFiled: July 13, 2010Date of Patent: April 9, 2013Assignee: Sumitomo Electric Industries, Ltd.Inventors: Shinji Tokuyama, Masaki Ueno, Masahiro Adachi, Takashi Kyono, Takamichi Sumitomo, Koji Katayama, Yoshihiro Saito
-
Patent number: 8415654Abstract: A low resistance light emitting device with an ultraviolet light-emitting structure having a first layer with a first conductivity, a second layer with a second conductivity; and a light emitting quantum well region between the first layer and second layer. A first electrical contact is in electrical connection with the first layer and a second electrical contact is in electrical connection with the second layer. A template serves as a platform for the light-emitting structure. The ultraviolet light-emitting structure has a first layer having a first portion and a second portion of AlXInYGa(1-X-Y)N with an amount of elemental indium, the first portion surface being treated with silicon and indium containing precursor sources, and a second layer. When an electrical potential is applied to the first layer and the second layer the device emits ultraviolet light.Type: GrantFiled: March 27, 2009Date of Patent: April 9, 2013Assignee: Nitek, Inc.Inventors: Asif Khan, Qhalid Fareed, Vinod Adivarahan
-
Patent number: 8415690Abstract: Provided is an epitaxial substrate using a silicon substrate as a base substrate. An epitaxial substrate, in which a group of group-III nitride layers are formed on a (111) single crystal Si substrate such that a (0001) crystal plane of the group of group-III nitride layers is substantially in parallel with a surface of the substrate, includes: a first group-III nitride layer made of AlN with many defects configured of at least one kind from a columnar or granular crystal or domain; a second group-III nitride layer whose interface with the first group-III nitride layer is shaped into a three-dimensional concave-convex surface; and a third group-III nitride layer epitaxially formed on the second group-III nitride layer as a graded composition layer in which the proportion of existence of Al is smaller in a portion closer to a fourth group-III nitride.Type: GrantFiled: April 27, 2012Date of Patent: April 9, 2013Assignee: NGK Insulators, Ltd.Inventors: Makoto Miyoshi, Shigeaki Sumiya, Mikiya Ichimura, Mitsuhiro Tanaka
-
Publication number: 20130082280Abstract: A light emitting device comprises a first layer of an n-type semiconductor material, a second layer of a p-type semiconductor material, and an active layer between the first layer and the second layer. A light coupling layer is disposed adjacent to one of the first layer and the second layer. In some cases, the light coupling layer is formed by roughening a buffer layer of the light emitting device. The light emitting device includes an electrode in electrical communication with one of the first layer and the second layer through a portion of the light coupling layer.Type: ApplicationFiled: September 29, 2011Publication date: April 4, 2013Inventors: Chao-Kun Lin, Li Yan, Chih-Wei Chuang
-
Publication number: 20130082237Abstract: Light emitting devices having an enhanced degree of polarization, PD, and methods for fabricating such devices are described. A light emitting device may include a light emitting region that is configured to emit light having a central wavelength, ?, and a degree of polarization, PD, where PD>0.006??b for 200 nm???400 nm, wherein b?1.5.Type: ApplicationFiled: December 16, 2011Publication date: April 4, 2013Applicant: PALO ALTO RESEARCH CENTER INCORPORATEDInventors: John E. Northrup, Christopher L. Chua, Michael Kneissl, Thomas Wunderer, Noble M. Johnson
-
Publication number: 20130070798Abstract: A semiconductor laser includes a semiconductor laser portion including an active layer portion having a p-type cladding layer, an active layer, and an n-type cladding layer on a p-type InP semiconductor substrate; and current confining structures that fill spaces on both sides of the semiconductor laser portion. Each of the current confining structures includes a first p-type InP layer, a Ru-doped InP layer, and a second p-type InP layer. The Ru-doped InP layer is in contact only with the first and second p-type InP layers. To obtain the structure, timing of introduction of a halogen-containing gas is adjusted.Type: ApplicationFiled: August 16, 2012Publication date: March 21, 2013Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Go Sakaino, Harunaka Yamaguchi, Takashi Nagira
-
Patent number: 8399876Abstract: A semiconductor die includes at least one first region and at least one second region. The at least one first region is configured to emit light having at least a first wavelength. The at least one second region is configured to emit light having at least a second wavelength, which is different from the first wavelength.Type: GrantFiled: May 31, 2011Date of Patent: March 19, 2013Assignee: Samsung Electronics Co., Ltd.Inventor: Taek Kim
-
Publication number: 20130065337Abstract: A method for fabricating a group-III nitride semiconductor laser device having a semi-polar surface provides a laser cavity mirror which can reduce lasing threshold current. A support plate H tilts at an angle THETA from an m-axis toward a reference plane Ab defined by a direction PR of travel of the blade 5g and an a-axis in a c-m plane while the direction PR is being orthogonal to the front surface Ha of the support plate H. The blade 5g is positioned so as to be aligned to a plane which includes an intersection P1 between the endmost scribe mark 5b1 among a plurality of scribe marks 5b and the front surface 5a of the substrate product 5 and extends along the direction PR. In the case where the angle ALPHA defined ranges either from 71 to 79 degrees or from 101 to 109 degrees, the angle THETA then ranges from 11 to 19 degrees, and thereby the reference plane Ab along the direction PR extends along the c-plane orthogonal to the c-axis.Type: ApplicationFiled: August 6, 2012Publication date: March 14, 2013Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventor: Shimpei TAKAGI
-
Publication number: 20130062660Abstract: A group 13 nitride crystal has a hexagonal crystal structure and at least contains nitrogen atom and at least a kind of metal atoms selected from a group consisting of B, Al, Ga, In, and Tl. The group 13 nitride crystal includes a first region located at an inner side of a cross section intersecting a c-axis, and a second region surrounding at least a part of an outer periphery of the first region, having a thickness larger than a maximum diameter of the first region, and having a carrier density higher than that of the first region.Type: ApplicationFiled: September 5, 2012Publication date: March 14, 2013Applicant: RICOH COMPANY, LTD.Inventors: Masahiro HAYASHI, Seiji Sarayama, Takashi Satoh, Hiroshi Nambu, Chiharu Kimura, Naoya Miyoshi
-
Publication number: 20130062613Abstract: According to one embodiment, a light emitting device includes a first lead, a light emitting element, a second lead and a molded body. The light emitting element is fixed on the first lead. The second lead is provided away from the first lead and electrically connected to the light emitting element via a metal wire. The, molded body made of a sealing resin covers the light emitting element, end portions of the first lead and the second lead, the light emitting element being fixed on the end portion of the first read, and the metal wire being bonded on the end portion of the second lead. The first groove is provided between first and second portions in a front surface of the second lead, the first portion being in contact with an outer edge of the molded body and the metal wire being bonded on the second portion.Type: ApplicationFiled: March 28, 2012Publication date: March 14, 2013Applicant: Kabushiki Kaisha ToshibaInventors: Atsushi Takeshita, Yuichi Ikedo, Tetsuya Muranaka
-
Patent number: 8395263Abstract: According to one embodiment, a semiconductor light emitting device includes a stacked structural body, a first, a second and a third conductive layer. The stacked structural body includes first and second semiconductors and a light emitting layer provided therebetween. The second semiconductor layer is disposed between the first conductive layer and the light emitting layer. The first conductive layer is transparent. The first conductive layer has a first major surface on a side opposite to the second semiconductor layer. The second conductive layer is in contact with the first major surface. The third conductive layer is in contact with the first major surface and has a reflectance higher than a reflectance of the second conductive layer. The third conductive layer includes an extending part extending in parallel to the first major surface. At least a portion of the extending part is not covered by the second conductive layer.Type: GrantFiled: February 17, 2011Date of Patent: March 12, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Taisuke Sato, Toshiyuki Oka, Koichi Tachibana, Shinya Nunoue