Abstract: Provided is a test apparatus that tests a device under test, comprising a power supply section that generates a power supply voltage to be supplied to the device under test; an inductive load section provided in a path between the power supply section and the device under test; a plurality of semiconductor switches connected in series in a path between the inductive load section and the device under test; and a control section that turns OFF the semiconductor switches when a supply of voltage to the device under test is stopped.

Abstract: Provided is a method for performing a burn-in test on an object under test in which a plurality of electrodes are provided in positions at different heights. The method comprising steps of: preparing an object under test in which an electrode in a higher position have a higher surface roughness among the plurality of electrodes; bringing a plurality of sheet-type probes into contact with the plurality of electrodes, respectively; and supplying an electric current with the plurality of electrodes through the plurality of sheet-type probes. By implementing the method, the sheet-type probes can be kept in stable contact with the electrodes because electrodes in a higher position have a higher surface roughness Ra than electrodes in a lower position. Consequently, stable and reliable burn-in test can be performed.

Abstract: A semiconductor device that can be manufactured with reduced costs and that includes a first connecting terminal, a second connecting terminal, a third connecting terminal, and a first circuit module configured to operate in response a first signal and a second signal. When a mode signal is in a first state, the first circuit module receives the first signal from the first connecting terminal and receives the second signal from the second connecting terminal. Otherwise, when the mode signal is in a second state, the first circuit module receives the first signal from the first connecting terminal and receives the second signal from the third connecting terminal. A memory module including at least one such memory device may also be provided.

Abstract: Provided is a switching apparatus that switches a connection state between two terminals, comprising a switch that switches the connection state between the two terminals according to a control voltage supplied thereto; a driving section that provides the switch with the control voltage corresponding to a control signal supplied thereto; and a changing section that changes the control voltage output from the driving section, according to a designated switching time. The changing section may change power supplied as a power supply to the driving section, according to the designated switching time. The changing section may change the control voltage output from the driving section prior to switching of the switch.

Abstract: A plasma damage detection test structure is disclosed. The plasma damage detection test structure includes a first antenna, a voltage source, a ground reference, a first transistor comprising a first source, a first gate, and a first drain. The plasma damage detection test structure further includes a second transistor comprising a second source, a second gate, and a second drain. The first gate is conductively coupled to said first antenna, said first drain and said second drain are conductively coupled to said voltage source, and said first source and said second source are conductively coupled to said ground reference. In various embodiments multiple antennas may be used. The antennas may be multiple configurations, such as a symmetric arrangement or asymmetric arrangement. In various embodiments, multiple transistors in parallel or cross-couple arrangements may be used.

Abstract: Provided is a test apparatus comprising a plurality of testing sections and a synchronizing section that synchronizes operation of at least two testing sections among the plurality of testing sections. Each testing section transmits a synchronization standby command to the synchronizing section when a predetermined condition is fulfilled during execution of the corresponding program and the testing section enters a synchronization standby state, and on a condition that the synchronization standby commands have been received from all of one or more predetermined testing sections among the plurality of testing sections, the synchronizing section supplies a synchronization signal, which ends the synchronization standby state, in synchronization to two or more predetermined testing sections among the plurality of testing sections.

Abstract: The invention relates to a method and a device for monitoring the insulation of an ungrounded DC and/or AC voltage network. The method comprises the following steps: (a) generating a measurement DC voltage Umess= that is connected to a ground on one side for a predeterminable measuring time frame tvar; (b) generating and superposing at least one measurement AC voltage Umess˜ connected to a ground and having a measurement duration tcons with the measurement DC voltage Umess? for forming a total measurement voltage Umess; (c) feeding the total measurement voltage Umess into the voltage network to be monitored; and (d) determining an insulating resistance R= from the measurement DC voltage Umess? and an insulating impedance Z from the measurement AC voltage Umess˜. The devise is configured to carry out the above method. The method and the device are suited in particular for monitoring the insulation in electric and hybrid vehicles.

Abstract: Various embodiments of a test mode control circuit of a semiconductor apparatus and related methods are disclosed. In one exemplary embodiment, the test mode control circuit may include: a test mode control block configured to generate a plurality of control signal sets in response to a first address signal set and a second address signal set which are sequentially inputted; a test mode transfer block configured to transfer a plurality of test mode signals, which are generated according to a combination of the plurality of control signal sets, to a plurality of circuit blocks of the semiconductor apparatus; and a plurality of global lines configured to transmit the plurality of control signal sets to the test mode transfer block.

Abstract: A battery emulation device for simulating a battery cell voltage at a terminal of a battery control unit in accordance with a setpoint value includes a control unit configured to determine the setpoint value and provide the determined setpoint value via a galvanically isolated interface; and at least one emulation channel, each including: a voltage source; an amplifier unit; connection lines for connecting the emulation channel; measurement lines; and a fault simulation device configured to simulate fault states.

Abstract: Apparatus for optically testing LEDs or other light-emitting components in a wide variety of test environments and to the degree necessary pertinent to the type(s) of faults encountered. In one embodiment, the present invention includes one or more fiber optic probes coupled to a multi-mode sensor unit, incorporating a photo-sensor coupled to a processor which may be programmed to provide a variety of test modes including simple on/off testing, color determination, color matching, wavelength and relative intensity among others. An extremely high sensitivity test mode is also provided for testing LEDs which emit very low intensity light in the microcandela range in products such as automobile/aircraft cockpit control panel lighted push-buttons for night-time viewing. The multi-mode sensor unit operates over a wide dynamic range and is capable of accurately testing LEDs that may be very dim to very bright without adjustment.

Abstract: An object of the present invention is to obtain a clear absorbed current image without involving the difference in gain of amplifier between inputs, from absorbed currents detected by using a plurality of probes and to improve measurement efficiency. In the present invention, a plurality of probes are brought in contact with a specimen. While irradiating the specimen with an electron beam, currents flowing in the probes are measured. Signals from at least two probes are input to a differential amplifier. An output of the differential amplifier is amplified. On the basis of the amplified output and scanning information of the electron beam, an absorbed current image is generated. According to the invention, a clear absorbed current image can be obtained without involving the difference in gain of amplifier between inputs. Thus, measurement efficiency in a failure analysis of a semiconductor device can be improved.

Abstract: An evaluation method and apparatus is provided for evaluating a displacement between patterns of a pattern image by using design data representative of a plurality of patterns superimposed ideally. A first distance is measured for an upper layer pattern between a line segment of the design data and an edge of the charged particle radiation image, a second distance is measured for a lower layer pattern between a line segment of the design data and an edge of the charged particle radiation image; and an superimposition displacement is detected between the upper layer pattern and lower layer pattern in accordance with the first distance and second distance.

Abstract: Providing reliable testing of a device under test (DUT) by compensating for a reduced voltage inside the device without changing the internal circuitry of the device. The DUT has multiple connection terminals for connecting to the test equipment including at least first and second power connection terminals that both connect to an internal power bus of the DUT. An adapter board connects to the multiple connection terminals of the DUT via a removably attachable socket which holds the DUT. A tester supplies power to the DUT through the adapter board. The adapter board is configured to supply power from the tester to the DUT through the first power connection terminal and to monitor voltage at the second power connection terminal. The tester includes a compensation unit which controls power based on the voltage monitored at the second power connection terminal.

Abstract: An apparatus and method corrects for zero ampere level current fluctuations in a current signal. First and second acquisition circuitry generate respective current and voltage data samples of the current signal. Current fluctuation data samples representative of zero ampere level deviations of the current signal are extracted corresponding to Off-periods of the current signal. The current fluctuation data samples of the Off-periods are interpolated to generate current fluctuation data samples representative of zero ampere level deviations of the On-periods of the current signal. The Off-period and On-period current fluctuation data samples are subtracted from the current data samples of the current signal to generate corrected zero ampere level current data samples.

Abstract: Provided is a modulation apparatus that outputs an output signal having a designated amplitude and a designated phase, comprising a first variable delay section that outputs a first delayed signal obtained by delaying a periodic signal by a set delay time; a second variable delay section that outputs a second delayed signal obtained by delaying the periodic signal by a set delay time; an adding section that adds together the first delayed signal and the second delayed signal, and outputs the result as the output signal; and a setting section that sets the delay times for the first variable delay section and the second variable delay section according to the designated amplitude and the designated phase.

Abstract: Provided is a test structure for testing an unpackaged semiconductor wafer. The test structure includes a force-application component that is coupled to an interconnect structure of the semiconductor wafer. The force-application component is operable to exert a force to the semiconductor wafer. The test structure also includes first and second test portions that are coupled to the interconnect structure. The first and second test portions are operable to measure an electrical performance associated with a predetermined region of the interconnect structure. The first and second test portions are operable to measure the electrical performance while the force is exerted to the semiconductor wafer.

Abstract: Systems and methods are provided for optimizing operation of an integrated circuit. In one implementation, a system is provided for optimizing operation of an integrated circuit by adjusting an operational parameter of the integrated circuit based on a reference count stored in non-volatile memory fabricated on the integrated circuit. In another implementation, a method is provided for optimizing operation of an integrated circuit by generating, during operation of the integrated circuit, a first oscillator count of an oscillator, comparing the first oscillator count with at least one reference count stored on the integrated circuit, and activating, a control circuit to adjust an operational parameter of the integrated circuit based on a result of the comparison.

Abstract: A water detection assembly having an electronic fluid-sensing probe located in-line within a primary drain line associated with a fluid-producing unit via probe connection to an access port used for clearing and removing clog-causing debris from the primary drain line. The probe has no moving parts and quick-disconnect connection to a signal-generating unit. The access port is configured for vertical or horizontal installation and introduction of chemicals to clean the drain without retrograde backflow into the fluid-producing unit. The probe is inserted into the access port through a longitudinal opening when vertically installed, and alternatively through a lateral opening in a horizontal installation. When the probe detects fluid, the connected signal-generating unit sends an electronic signal that shuts off fluid production, activates an alarm or pump, and/or provides remote notification.

Abstract: A testing method is described of at least one device provided with an integrated testing circuit and in communication with at least one tester where messages/instructions/test signals/information are exclusively sent from the tester to the device . A testing architecture is also described for implementing this testing method.

Abstract: A CMOS-controlled printhead sense circuit includes a CMOS control circuit module operable as a transmission gate switchable between first and second signal levels and a CMOS sense circuit module operable in a printhead sense mode in response to the CMOS control circuit module being switched to the first level and in a transparent mode in response to the control circuit module being switch to the second level. The CMOS control circuit module includes a combination of PMOS and NMOS FETs which define a CMOS switchable transmission gate. The CMOS sense circuit module includes a combination of PMOS and NMOS FETs which define respectively a switch device switchable between high and low states corresponding to the sense and transparent modes and a load enhancement device for the switch device.

Abstract: A test circuit is capable of easily testing the standby function of an interface block. The test circuit is used for the interface block disposed on a semiconductor integrated circuit which is switched between a standby mode and a non-standby mode and conducting interfacing between the semiconductor integrated circuit and the outside in the non-standby mode, generating a fixed voltage and outputting the same to a corresponding signal line in the standby mode. The test circuit is disposed on the semiconductor integrated circuit and generates a current in accordance with the voltage level of the signal line in the standby mode.

Abstract: Aspects of the disclosure provide a method for testing an electronic device. The method includes supplying a first voltage output from a voltage regulator to a first power connection terminal of the electronic device to provide power to the electronic device, providing to the voltage regulator a second voltage on a second power connection terminal of the electronic device that is in connection with the first power connection terminal by a first circuit of the electronic device, regulating, using the voltage regulator, the first voltage based on a comparison of the second voltage and a target voltage, and determining whether the electronic device meets a performance requirement while the first voltage is regulated.

Abstract: A full duplex, high speed test interface comprises a tester side circuit and a device under test side circuit, each comprising balancing circuits. The balancing circuit of the test side circuit is configured to cancel its own transmitted data at the test side circuit such that the transmitted data does not influence any other signal generated at the test side circuit. Similarly, the balancing circuit of the device under test side circuit is configured to cancel its own transmitted data at the device under test side circuit such that the transmitted data does not influence any other signal generated at the device under test side circuit.

Abstract: Techniques for self-calibration of transceivers are described herein.

Abstract: There is described a method and a system for evaluating damage of a plurality of cells in an electrolyser. The method comprises acquiring a voltage for each one of the cells; comparing the voltage to at least two threshold voltage levels; classifying the cells as one of: severely damaged cells, non-severely damaged cells and undamaged cells, based on the comparison of the voltage with the at least two threshold voltage levels; and deactivating the cells classified as severely damaged cells from the electrolyser.

Abstract: Characteristics of partially assembled photovoltaic modules can be determined using electrical connection apparatuses and methods.

Abstract: Defects in components in ICs which may cause circuit failures during operation of the IC are often difficult to detect during and immediately after fabrication of the IC by DC test methods. A method of testing components to detect such defects using AC Impedance Spectroscopy is disclosed. Data may be analyzed using Nyquist plots and Bode plots. Nyquist plots of typical defect types are disclosed. Components may include MOS transistor gate structures, contacts, vias and metal interconnect lines. Components tested may be contained in integrated circuits or in test circuits. Integrated circuits containing components tested by AC Impedance Spectroscopy may be partially fabricated or deprocessed after fabrication.

Abstract: A DUT is connected to an I/O terminal. An AC test unit performs an AC test operation for the DUT. A DC test unit performs a DC test operation for the DUT. An optical semiconductor switch is arranged such that a first terminal thereof is connected to the AC test unit and a second terminal thereof is connected to the I/O terminal. The optical semiconductor switch 10 is configured to be capable of switching states, according to control signals input to control terminals, between a connection state in which the first terminal and the second terminal are connected to each other, and a disconnection state in which they are disconnected from each other. A first impedance circuit is arranged on a signal line for the control signal to be input to the positive-electrode control terminal. Furthermore, a second impedance circuit is arranged on a signal line for the control signal to be input to the negative-electrode control terminal.

Abstract: A sampling apparatus for sampling a fluid from a fluid source includes a first fluid passage device, a second fluid passage device and a fluid by-pass. The first fluid passage device is disposed downstream of and in fluid communication with the fluid source. The second fluid passage device is disposed downstream of and is in fluid communication with the first fluid passage device. The fluid by-pass is disposed downstream of the fluid source and upstream of the second fluid passage device. The fluid by-pass being in fluid communication with and disposed between the fluid source and the second fluid passage device is operative to cause a first portion of the fluid to flow through the first fluid passage device and to cause a second portion of the fluid to by-pass the first fluid passage device and to flow to the second fluid passage device.

Abstract: An internal voltage test circuit of a semiconductor memory apparatus includes a comparing unit for comparing a level of internal voltage with a level of external voltage to output a comparison result as an output signal during a test mode, and an output selecting unit for outputting the output signal to a data output pad during the test mode, and outputting a data signal to the data output pad during a normal operation mode.

Abstract: An apparatus and method for preventing access to calibration controls includes a primary cover including a connection device, an access opening and a first through hole. The primary cover is configured to exclude access to an underlying area. The access opening is located on the primary cover to permit access to the underlying area when securing the primary cover. A shield is configured to fit over the primary cover and prevent access to the access opening. The shield includes a latch portion configured to latch on a first end portion of the primary cover and a second through hole located at a second end portion and corresponding to the first through hole of the primary cover. A security mechanism is configured to be received in the first and second through holes such that the security mechanism shows signs of tampering when unauthorized access to the underlying area is attempted.

Abstract: Disclosed is an apparatus for driving a placing table that contributes to saving a space and reducing the weight of an inspecting apparatus. The apparatus for driving a placing table according to an exemplary embodiment of the present disclosure includes a horizontal driving mechanism that horizontally moves a placing table in an inspecting chamber, a base that supports horizontal driving mechanism, a placing table lifting mechanism (for example, air bearing) that lifts placing table from support, using compressed air in inspecting chamber, a connecting mechanism that connects horizontal driving mechanism with placing table, and a case that accommodates the horizontal driving mechanism and the base.

Abstract: A tester includes a device under test (DUT) power supply (DPS) with and input and output includes an amplifier configured to set an output voltage of the DPS output equal to an input voltage for the DPS. The DPS has a first output stage coupled to the amplifier and configured to source and sink current at the output of the DPS between a first voltage rail and a third voltage rail. The DPS has a second output stage coupled to the amplifier and configured to source and sink current to the output of the DPS between a second voltage rail and the third voltage rail. A selection device is configured to enable the first and second output stages based on a selection input signal. The selection device is situated outside of the first and the second output stages.

Abstract: A method of testing integrated circuits is provided. The method includes establishing at least one first physical communication channel between a test equipment and a respective group of integrated circuits under test by having probes of the test equipment contacting at least one corresponding physical contact terminal of each integrated circuit of the respective group. The method further includes having the test equipment exchanging, over the at least one first physical communication channel, the same test stimuli with each integrated circuit of the group. The method still further includes having each integrated circuit of the group establishing a corresponding second physical communication channel with the test equipment by having at least one physical contact terminal of the integrated circuit contacted by a corresponding probe of the test equipment.

Abstract: To verify robustness with respect to electrical overstresses of an electronic circuit under test, the latter is exposed to electrical overstresses, and the behavior thereof is monitored. In particular, both the testing of the electronic circuit in dynamic conditions is performed by causing it to be traversed by the currents that characterize operation thereof, and by exposing at least one supply line of the electronic circuit under test to electrical overstresses and the testing of the electronic circuit under test in static conditions, without causing it to be traversed by the currents that characterize operation thereof, and by exposing to electrical overstresses both the supply and the input and/or output lines of the electronic circuit under test. The device for generating the overstresses can be mounted on a circuit board, which can be coupled as daughter board to a mother board, on which the electronic circuit under test is mounted.

Abstract: A method for adjusting an output signal produced by a device under test from an input variable by: a) positioning the device under test at a first test device with a physical disturbance variable and a known input variable value, b) acquiring at least one measured value for the output signal, c) changing the adjustment state, d) acquiring a further measured value for the output signal, e) positioning the device under test at a further test device having a further disturbance variable value and the input variable value, f) acquiring a further measured value for the output signal, g) changing the adjustment state, h) acquiring a further measured value for the output signal, i) comparing the measured values acquired at the test devices for each adjustment state and determining a first adjustment state in which the correlation between the measured values is larger than in a second adjustment state.

Abstract: A method for detecting component defects of an analog signal processing circuit, especially for a measurement transmitter. A test signal TS is generated at a first test point TP1 and an associated response signal RS tapped at a second test point TP2 and evaluated in a digital unit. In the evaluation, individual amplitude values of the response signal RS are compared with predetermined, desired values. In the case of significant deviations, a defect report is generated.

Abstract: There are provided an inspection apparatus and method that can locally perform sample temperature regulation, so that the sample drift can be suppressed. There are included a sample stage 109 that holds a semiconductor sample 118, multiple probes 106 used to measure electrical characteristics of a semiconductor device on the semiconductor sample 118, a power source that applies voltage and/or current to the probe 106, a detector that measures electrical characteristics of the semiconductor device on the sample with which the probe is brought into contact, and an electromagnetic wave irradiating mechanism that irradiates electromagnetic wave on a measurement section of the semiconductor sample 118.

Abstract: A test apparatus that tests a device under test having a plurality of blocks operating asynchronously, based on a signal received from outside, the test apparatus comprising a plurality of domain test units corresponding respectively to the blocks; and a main body unit that controls the domain test units. The main body unit includes a reference operation clock generating section that generates a reference operation clock supplied to each domain test unit, and a test start signal generating section that generates a test start signal instructing each domain test unit to start the testing. Each domain test unit includes a test clock generating section that generates a test clock based on the reference operation clock, and generates a test signal for testing the corresponding block based on the test clock obtained by the test clock generating section, and each domain test unit starts generating the test signal on a condition that the test start signal is received.

Abstract: What is disclosed is an apparatus for determining the cooling characteristics of a cooling device used for transferring heat from an electronic device. The apparatus comprising a cooling device thermally coupled to a heat pipe. The heat pipe having an exposed surface for the selective application of heat thereon. A localized heat source is selectively applied to at least one region of the exposed surface. The heat source preferably capable of being varied both positionally relative to the exposed surface and in heat intensity. A heat shield is preferably positioned around the exposed surface of the heat pipe to isolate the operational cooling device from the localized heat source. A temperature detector repeatedly measures a temperature distribution across the exposed surface while the cooling device is in a heat transfer mode. The temperature distribution is then used to thermally characterize the cooling device.

Abstract: Embodiments of the invention are generally directed to fault testing for interconnections. An embodiment of a fault analysis apparatus includes a test pattern source to provide a test pattern for an interconnection between a transmitter and a receiver, the interconnection having a transmitter end and a receiver end, the interconnection including a first wire and a second wire, the transmitter transmitting the test pattern on the first wire to the receiver. The apparatus further includes a first switch to open and close a first connection for the first wire, and a second switch to open and close a second connection for the second wire. The first switch and the second switch are to be set according to a configuration to set at least a portion of a test path for the detection of one or more faults in the interconnection.

Abstract: The present invention relates to a method and an arrangement of facilitating through-line mismatch RF testing using an air-isolated coaxial line (1) having an inner conductor (2) surrounded by a coaxial shielding (3). At least one opening (4) is provided through the shielding (3). A radially adjustable piston (5) is provided in each opening (4) such that it is electrically connected to the shielding (3) and such that its protrusion from an inside of the shielding (3) towards the inner conductor (2) may be varied. Hereby is provided for an adjustable and easy characterized mismatch, which does not have to be disconnected after use, but simply set to zero.

Abstract: A device for analyzing defects, particularly for items made of plastics, such as battery casings and the like, comprising at least one probe, which is adapted to be moved closer to, or to come into contact with, the item made of plastics to be tested, the probe being provided with a plurality of elements to which a high voltage is applied.

Abstract: A semiconductor wafer analysis system is provided. In an embodiment, the semiconductor wafer analysis system includes a tester to test semiconductor wafers manufactured by at least one manufacturing facility, a wafer map generation module to generate wafer maps on the basis of the test results from the tester, and a wafer analysis module. The wafer analysis module may include a data generation module that divides each wafer map into a plurality of defect analysis regions and generates feature vectors representing the semiconductor wafers, and an operation module that statistically analyzes the feature vectors.

Abstract: A method and a system for three-phase detection of a three-phase electric device are provided. The system includes a testing circuit and a comparison module. The testing circuit generates two reference voltages by using the three phase voltages of the three-phase electric device. The two reference voltages are the first and second phase voltages with reference to the third phase voltage, respectively. Three-phase detection is performed by comparing the two reference voltages for a determined number of times. After testing is completed, the testing circuit is switched off by the comparison module, to save power.

Abstract: Low loss current and voltage probes are integrated in parallel plate airlines (slablines) to be used either as separate modules inserted between tuner and DUT in load pull test setups, or integrated in the impedance tuners themselves. The probes are inserted orthogonally at exactly the same reference plane relative to the DUT, maximizing bandwidth and the minimizing deformation of the detected electric and magnetic fields. The probes are used to detect the actual voltage and current waveforms and feed into an amplitude-and-phase calibrated high speed oscilloscope, including several harmonic frequencies. The actual real time voltage and current time domain waves are transformed into the frequency domain using fast Fourier transformation (FFT), de-embedded to the DUT reference plane and inverse transformed into the time domain using inverse Fourier transformation (FFT?1). The result of this real-time operation is the actual dynamic load line of the DUT at its terminals.

Abstract: A chuck for supporting and retaining a test substrate includes a device for supporting and retaining a calibration substrate. The chuck comprises a first support surface for supporting a test substrate and a second support surface, which is laterally offset to the first support surface, for supporting a calibration substrate The calibration substrate has planar calibration standards for calibration of a measuring unit of a prober, and dielectric material or air situated below the calibration substrate at least in the area of the calibration standard. In order to be able to take the actual thermal conditions on the test substrate and in particular also on known and unknown calibration standards and thus the thermal influence on the electrical behavior of the calibration standard used into consideration, the second support surface is equipped for temperature control of the calibration substrate.

Abstract: A calibration substrate includes a plurality of input terminals, a detector coupled to the input terminals, and an output terminal. The calibration substrate can be used for calibrating and/or deskewing communications channels.

Abstract: The present invention provides a method for measuring the PN-junction temperature of a light-emitting diode (LED), which uses a reference voltage to establish the function of current, real power, power factor, or driving-time interval on temperature. The initial and thermal-equilibrium values of current, real power, power factor, or driving-time interval are measured, and hence the variations thereof are calculated. Referring to the pre-established function, the temperature change is given. By the temperature change and the initial temperature, the PN-junction temperature of the LED is thereby deduced.

Abstract: A test apparatus includes: a driver circuit that supplies, to a device under test, a test signal corresponding to an input signal; and a judging section that judges pass/fail of the device under test, based on the load voltage or the load current supplied to the device under test when supplying a test signal of a constant current or a constant voltage to the device under test from the driver circuit, where the driver circuit includes: a driver section that outputs the test signal; a supply current detecting section that detects a supply current supplied to the driver section; and an output control section that controls a voltage or a current of the test signal outputted from the driver section to the predetermined value, based on the supply current detected by the supply current detecting section.