Abstract: A test apparatus and a test method with which a circuit size can be decreased are provided. A recovered clock generating circuit generates a recovered clock of which phase is approximately the same as a phase of output data output by a device under test (DUT). The recovered clock generating circuit includes a phase comparator that compares a phase of the output data of the DUT to a phase of the recovered clock to generate a phase difference signal, a binary counter of which output value is incremented or decremented based on the phase difference signal, a control signal generating section that generates a control signal based on an output value of the binary counter, and a phase shifter that shifts the phase of the reference clock based on the control signal.

Abstract: A measurement apparatus that measures a signal under measurement, including a strobe timing generator that sequentially generates strobes arranged at substantially even time intervals, a level comparing section that detects a signal level of the signal under measurement at a timing of each sequentially provided strobe, a capture memory that stores therein a data sequence of the signal levels sequentially detected by the level comparing section, a frequency domain converting section that converts the data sequence into a spectrum in the frequency domain, and a jitter calculating section that calculates jitter of the signal under measurement based on a value obtained by integrating levels of frequency components in a predetermined frequency range of the spectrum.

Abstract: An internal voltage test circuit of a semiconductor memory apparatus includes a comparing unit for comparing a level of internal voltage with a level of external voltage to output a comparison result as an output signal during a test mode, and an output selecting unit for outputting the output signal to a data output pad during the test mode, and outputting a data signal to the data output pad during a normal operation mode.

Abstract: Apparatus for optically testing LEDs or other light-emitting components in a wide variety of test environments and to the degree necessary pertinent to the type(s) of faults encountered. In one embodiment, the present invention includes one or more fiber optic probes coupled to a multi-mode sensor unit, incorporating a photo-sensor coupled to a processor which may be programmed to provide a variety of test modes including simple on/off testing, color determination, color matching, wavelength and relative intensity among others. An extremely high sensitivity test mode is also provided for testing LEDs which emit very low intensity light in the micro-candela range in products such as automobile/aircraft cockpit control panel lighted push-buttons for night-time viewing. The multi-mode sensor unit operates over a wide dynamic range and is capable of accurately testing LEDs that may be very dim to very bright without adjustment.

Abstract: A circuit for simulating an electrical load at a terminal of a test circuit having at least one first switch and at least one second switch includes a third switch connected to the first switch of the test circuit via a first external connection point. A fourth switch is connected to the second switch of the test circuit via a second external connection point. The first switch and the second switch are connected via a shared, first internal connection point to the terminal of the test circuit and the third switch and the fourth switch are connected via a shared, second internal connection point such that that the first switch, the second switch, the third switch and the fourth switch form an H-bridge circuit. A voltage source is configured to provide the first and second external connection points with a supply voltage. A controllable voltage source is connected in a transverse bridge branch between the terminal and the second internal connection point. An inductance is active in the transverse bridge branch.

Abstract: Provided is a test apparatus that tests a device under test, comprising a plurality of capacitors that are each charged to a predetermined voltage; a switching section that switches which of the capacitors charged to a predetermined voltage supplies power to the device under test; and a judging section that judges acceptability of the device under test based on an operational result of the device under test. Also provided is a test apparatus that selects one of a plurality of capacitors and a corresponding one of a plurality of power supply units, according to content of a test performed after a test that uses another of the capacitors to supply power to the device under test.

Abstract: Method and apparatus are disclosed related to testing and testability of adaptive equalization circuitry. Where an equalization circuit is provided in an IC, a modified internal loopback provides a testing signal. A local comparator circuit with flexible connectivity offers analog signal testing analysis in conjunction with a low-cost external tester. Flexible use and connectivity of the comparator and external connection points, and block isolation circuitry make accurate, faster, and lower cost testing methods possible.

Abstract: A method for detecting component defects of an analog signal processing circuit, especially for a measurement transmitter. A test signal TS is generated at a first test point TP1 and an associated response signal RS tapped at a second test point TP2 and evaluated in a digital unit. In the evaluation, individual amplitude values of the response signal RS are compared with predetermined, desired values. In the case of significant deviations, a defect report is generated.

Abstract: The invention relates to devices for liquid level detection (LLD). It relates to a laboratory device having an electronic circuit for detecting a liquid level in a liquid container, a feeler, which can be advanced, and which is connected to an input side of the electronic circuit, and having a movement device, which allows the feeler to be advanced in the direction of the liquid in the liquid container. Upon the immersion of the feeler in the liquid, a capacitance change is caused in the electronic circuit, which triggers a signal in the circuit. The laboratory device comprises a reference circuit, which is connected to the input side of the circuit, and which specifies an effective capacitance on the input side of the circuit. A sequence controller is used, which causes the triggering of a test by the application of a control signal to the reference circuit, the control signal causing an increase of the effective capacitance through a switching procedure.

Abstract: An exemplary apparatus for detecting defect is capable of measuring temperature characteristics of a semiconductor sample without restrictions in the movement range of a sample stage and a probe device by a temperature control device. A heater heats a sample stage, and the sample stage is cooled by a refrigerant contained in a refrigerant container through a heat transfer line connected to the sample stage, a first heat receiving portion connected to the heat transfer line, a second heat receiving portion that is detachable from the heat receiving portion, a heat transfer line connected to the heat receiving portion, and a heat transfer rod connected to the heat transfer line, thereby adjusting the temperature of a semiconductor sample held by the sample stage. The heat receiving portions are separated from each other to release the restriction of the sample stage and a probe device such that the sample stage and the, probe device can be moved in a sample chamber.

Abstract: A measuring apparatus including a self test function, the circuit comprising a capacitor; first to fourth switches; a test signal injector; at least one comparator having a signal input and a reference input the first switch being interposed between a first plate of the capacitor and a first input node, the second switch being interposed between a second plate of the capacitor and a second input node, the third switch being interposed between the first plate of the capacitor and the signal input of the comparator and the fourth switch being interposed between the second plate of the capacitor and a voltage reference, wherein the self test function comprises the steps of i) operating the signal injector to produce a first signal representative of an out of range voltage for an expected voltage difference between the first and second input nodes, and using the signal to cause the at least one comparator to place its output in an error state, and to charge the capacitor to the out of range voltage, ii) isolating

Abstract: A system for measuring an optical spectral response of a photoelectric device under test (DUT) includes a spectrally programmable light source including in optically coupled sequence a broadband light source for emitting light, a dispersive element for dispersing light, and a spatial light modulator for controlling an intensity and a spectra of the light to provide a spectrally programmable light beam. A light distributing device having at least one input portion is coupled to receive the spectrally programmable light beam and includes a light distributing structure for distributing the spectrally programmable light beam in a known ratio to a first area and at least a second area. A reference detector having a reference output positioned at the first area, and the DUT is positioned at the second area.

Abstract: In a method of testing a device under test (DUT) using a test device adapted to provide a connection to a central controller, a test procedure activation signal is supplied from the central controller to the test device. A test procedure for testing the DUT is performed on the basis of test procedure data, upon receipt of the test procedure activation signal. The test procedure is adjustable upon receipt of a feedback signal from the DUT. The test procedure is adjusted by 1) receiving a feedback signal from the DUT, 2) determining from the feedback signal properties of a physical connection between the test device and the DUT, and 3) adjusting the test procedure to modify the test signal and compensate for the properties of the physical connection between the test device and the DUT.

Abstract: A circuit testing apparatus for testing a device under test is disclosed. The device under test comprises a first output end and second output end for generating a first output signal and a second output signal, respectively. The circuit testing apparatus determines a test result for the device under test according to the first output signal and the second output signal.

Abstract: An internal voltage test circuit of a semiconductor memory apparatus includes a comparing unit for comparing a level of internal voltage with a level of external voltage to output a comparison result as an output signal during a test mode, and an output selecting unit for outputting the output signal to a data output pad during the test mode, and outputting a data signal to the data output pad during a normal operation mode.

Abstract: A test handler is disclosed. A posture changing unit for changing a posture of a test tray on which semiconductor devices have been loaded changes the posture of the test tray in a soak chamber. While the posture of the test tray is changed, the devices can be pre-heated/pre-cooled, thereby reducing the soak chamber length and the pre-heating/pre-cooling time.

Abstract: A test setup for estimating the critical charge of a circuit under test (CUT) uses a charge injection circuit having a switched capacitor that is selectively connected to a node of the CUT. A voltage measurement circuit measures the voltage at a tap in the charge injection circuit before and after the charge is injected. When the injected charge causes an upset in the logical state of the CUT, the critical charge is calculated as the product of the voltage difference and the known capacitance of the capacitor. In one embodiment, (NMOS drain strike simulation) the amount of charge injected is controlled by a variable pulse width generator gating the switch of the charge injection circuit. In another embodiment (PMOS drain strike simulation) the amount of charge injected is controlled by a variable voltage supply selectively connected to the charge storage node.