Abstract: A body structure and a drift zone are formed in a semiconductor layer, wherein the body structure and the drift zone form a first pn junction. A silicon nitride layer is formed on the semiconductor layer. A silicon oxide layer is formed from at least a vertical section of the silicon nitride layer by oxygen radical oxidation.

Abstract: Memory devices with controlled wordline ramp rates and associated systems and methods are disclosed herein. In one embodiment, a memory device includes at least one voltage regulator and a plurality of wordlines. The memory device is configured, during a programming operation of the memory region, to ramp a selected wordline to a desired programming voltage while ramping one or more adjacent, unselected wordlines electrically coupled to the selected wordline to desired inhibit voltage(s) using the at least one voltage regulator. In some embodiments, the memory device ramps the selected wordline and the one or more adjacent, unselected wordlines such that the one or more adjacent, unselected wordlines reach the desired inhibit voltage(s) when the selected wordline reaches the desired programming voltage. In these and other embodiments, the memory device ramps the selected wordline to the desired programming voltage without floating the selected wordline.

Abstract: Systems and methods presented herein provide for computing read voltages for a storage device. In one embodiment, a controller is controller is operable to soft read data from a portion of the storage device, and to iteratively test the soft read data a predetermined number of times. For example, the controller may test the soft read data a number of times by applying a different probability weight to the soft read data each time the soft read data is tested. The controller may then decode the soft read data based on the probability weight, and determine an error metric of the decoded soft read data. Then, the controller determines a read voltage for the portion of the storage device based on the probability weight and the error metric.

Abstract: A semiconductor memory device includes a first memory cell transistor, a second memory cell transistor, and a third memory cell transistor that are connected in series. A word line is coupled to a gate of the third memory cell transistor. A controller is configured to set a first upper limit value for voltages applied to the word line during writing of data to the first memory cell transistor and a second upper limit value for voltages applied to the word line during writing of data to the second memory cell transistor. The second upper limit value is different from the first upper limit value.

Abstract: A nonvolatile memory device includes a first cell string including a first dummy cell and connected to a selected string select line, a second cell string including a second dummy cell and connected to the selected string select line, a page buffer circuit configured to select one of the first and second cell strings to read data in a read operation, and a control logic circuit configured to apply a first bit line voltage to a bit line connected to the selected one of the first and second cell strings and a second bit line voltage to a bit line connected to an unselected one of the first and second cell strings in the read operation. The control logic circuit turns off the second dummy cell when the first cell string is selected and turns off the first dummy cell when the second cell string is selected.

Abstract: A semiconductor memory cell comprising an electrically floating body having two stable states is disclosed. A method of operating the memory cell is disclosed.

Abstract: A DRAM device with embedded flash memory for redundancy is disclosed. The DRAM device includes a substrate having a DRAM array area and a peripheral area. The peripheral area includes an embedded flash forming region and a first transistor forming region. DRAM cells are disposed within the DRAM array area. Flash memory is disposed in the embedded flash forming region. The flash memory includes an ONO storage structure and a flash memory gate structure. A first transistor is disposed in the first transistor forming region.

Abstract: A memory device comprises a first NAND string that includes a first plurality of memory cells and a first string select switch arranged in series, the first string select switch disposed between a first bit line and a first end of the first plurality, a second NAND string that includes a second plurality of memory cells and a second string select switch arranged in series, the second string select switch disposed between a second bit line and a first end of the second plurality, word lines coupled to memory cells in the first plurality and memory cells in the second plurality, and a string select line coupled to the first and second string select switches. A method of operating such a memory device comprises applying a voltage varying in a manner complementary to absolute temperature to at least one of the word lines and the string select line.

Abstract: The present disclosure relates to novel memristive devices, uses thereof, and processes for their preparation. In a first aspect, the disclosure provides a quantum memristor, including a first quantum dot (QD1) which is capacitively coupled to a second quantum dot (QD2), a source electrode, a drain electrode, and a bath electrode, wherein the source electrode and the drain electrode are coupled via quantum tunneling to QD1 and the bath electrode is coupled via quantum tunneling to QD2, and wherein QD2 is capacitively coupled to either the source electrode or the drain electrode.

Abstract: Apparatuses and techniques are described for programming memory cells with a narrow threshold voltage (Vth) distribution in a memory device. In a first program pass of a multi-pass program operation, pass voltages of the word lines adjacent to a selected word line are adjusted to increase electron injection in a portion of a charge-trapping layer between the selected word line and an adjacent source side unselected word line. In a second, final program pass of the multi-pass program operation, the pass voltages are adjusted to reduce electron injection in the portion of the charge-trapping layer between the selected word line and the adjacent source side unselected word line.

Abstract: Several embodiments of memory devices and systems with read level calibration are disclosed herein. In one embodiment, a memory device includes a controller operably coupled to a main memory having at least one memory region and calibration circuitry. The calibration circuitry is operably coupled to the at least one memory region and is configured to determine a read level offset value corresponding to a read level signal of the at least one memory region. In some embodiments, the calibration circuitry is configured to obtain the read level offset value internal to the main memory. The calibration circuitry is further configured to output the read level offset value to the controller.

Abstract: The various implementations described herein include methods, devices, and systems for performing operations on memory devices. In one aspect, a memory device includes: (1) a first charge storage device having a first gate with a corresponding first threshold voltage, the first charge storage device configured to store charge corresponding to one or more first bits; and (2) a second charge storage device having a second gate with a corresponding second threshold voltage, distinct from the first threshold voltage, the second charge storage device configured to store charge corresponding to one or more second bits; where the second charge storage device is coupled in parallel with the first charge storage device.

Abstract: A spin current assisted magnetoresistance effect device includes: a spin current assisted magnetoresistance effect element including a magnetoresistance effect element part and a spin-orbit torque wiring; and a controller electrically connected to the spin current assisted magnetoresistance effect element. In a portion in which the magnetoresistance effect element part and the spin-orbit torque wiring are bonded, an STT inversion current flowing through the magnetoresistance effect element part and an SOT inversion current flowing through the spin-orbit torque wiring merge or are divided, and the controller is configured to be capable of performing control for applying the STT inversion current to the spin current assisted magnetoresistance effect element at the same time as an application of the SOT inversion current or a time application of the SOT inversion current.

Abstract: A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array and a control circuit. The control circuit executes a first reading operation and a second reading operation. The first reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between a control gate electrode and source of the selected memory cell to a first value. The second reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between the control gate electrode and source of the selected memory cell to a second value lower than the first value. When executing the second reading operation, the control circuit keeps a voltage of the control gate electrode of the selected memory cell to 0 or a positive value.

Abstract: A phase change memory device with memory cells (2) formed by a phase change memory element (3) and a selection switch (4). A reference cell (2a) formed by an own phase change memory element (3) and an own selection switch (4) is associated to a group (7) of memory cells to be read. An electrical quantity of the group of memory cells is compared with an analogous electrical quantity of the reference cell, thereby compensating any drift in the properties of the memory cells.

Abstract: Disclosed are a memory device, including: a memory block including a plurality of cell strings; a peripheral circuit configured to set voltages for a program operation of selected memory cells in the cell strings, and program the selected memory cells by using the set voltages; and a control circuit configured to control the peripheral circuit so that the selected memory cells are programmed in response to a program command, and increase a channel voltage of non-selected cell strings including non-selected memory cells while the selected memory cells are programmed, and an operating method thereof.

Abstract: Failed write handling can be implemented at a memory controller for non-volatile memory. Failure of a write to a storage location in the non-volatile memory may be detected. An indication of the failure may be sent to a microcontroller for the non-volatile memory which may return an instruction to write to a different location in the non-volatile memory. Reads and writes to the storage location of the failed write may still be allowed, in some embodiments, by redirecting the reads and writes to a copy of data of the failed write stored in a copy buffer in the memory controller.

Abstract: A semiconductor memory device includes first and second memory blocks each including conductive and dielectric layers alternately stacked over a semiconductor layer disposed over a substrate, and disposed adjacent to each other in a first direction; a dummy block disposed over the semiconductor layer, and provided between the first and second memory blocks; first pass transistors formed over the substrate below the first memory block, and coupled to conductive layers, respectively, of the first memory block; second pass transistors formed over the substrate below the second memory block, and coupled to conductive layers, respectively, of the second memory block; bottom global row lines between the first and second pass transistors and the semiconductor layer, and each coupled to one of the first pass transistors and one of the second pass transistors; and top global row lines formed over the dummy block, and coupled to the bottom global row lines.

Abstract: A method can be used for writing in a memory location of the electrically-erasable and programmable memory type. The memory location includes a first memory cell with a first transistor having a first gate dielectric underlying a first floating gate and a second memory cell with a second transistor having a second gate dielectric underlying a second floating gate that is connected to the first floating gate. In a first writing phase, an identical tunnel effect is implemented through the first gate dielectric and the second gate dielectric. In a second writing phase, a voltage across the first gate dielectric but not the second gate dielectric is increased.

Abstract: Apparatuses and techniques are described for programming memory cells with a narrow threshold voltage (Vth) distribution in a memory device. In one approach, the final pass of a multi-pass program operation on a word line WLn includes applying a variable voltage to WLn+1 during verify tests on WLn. The variable voltage (Vread) can be an increasing function of the verify voltage on WLn, and thus a function of the data state for which the verify test is performed. In one approach, Vread on WLn+1 is stepped up with each increase in the verify voltage on WLn. The step size in Vread can be the same as, or different than, the step size in the verify voltage. Vread can be different for each different verify voltage, or multiple verify voltages can be grouped for use with a common Vread.

Abstract: A flash memory storage apparatus having a plurality of operation modes is provided. The flash memory storage apparatus includes a memory controller circuit and a memory cell array. The memory controller circuit is configured to control the flash memory storage apparatus to operate in one of the operation modes. The operation modes include a low standby current mode. The memory cell array is coupled to the memory controller circuit. The memory cell array is configured to store data. The data includes read-only memory data. The memory controller circuit controls the flash memory storage apparatus to enter the low standby current mode according to a first command. The memory controller circuit wakes up the flash memory storage apparatus from the low standby current mode according to a second command. When the flash memory storage apparatus operates in the low standby current mode, the read-only memory data is kept.

Abstract: Provided is a non-volatile memory device comprising a plurality of memory cells and memory control logic that when executed performs operations comprising initiating a refresh operation; in response to the refresh operation, performing a read of the memory cells to read values of the memory cells; determining whether the read memory cells have a first value or a second value; and for the memory cells determined to have the first value, rewriting the determined first value to the memory cell, wherein the rewriting operation is not performed with respect to memory cells determined to have the second value.

Abstract: A three-dimensional stacked memory device is configured to provide uniform programming speeds of different sets of memory strings formed in memory holes. In a process for removing sacrificial material from word line layers, a block oxide layer in the memory holes is etched away relatively more when the memory hole is relatively closer to an edge of the word line layers where an etchant is introduced. A thinner block oxide layer is associated with a faster programming speed. To compensate, memory strings at the edges of the word line layers are programmed together, separate from the programming of interior memory strings. A program operation can use a higher initial program voltage for programming the interior memory strings compared to the edge memory strings.

Abstract: The present disclosure includes apparatuses and methods related to selectable trim settings on a memory device. An example apparatus can store a number of sets of trim settings and select a particular set of trims settings of the number of sets of trim settings based on desired operational characteristics for the array of memory cells.

Abstract: Some embodiments include a conductive structure of an integrated circuit. The conductive structure includes an upper primary portion, with the upper primary portion having a first conductive constituent configured as a container. The container has a bottom, and a pair of sidewalls extending upwardly from the bottom. An interior region of the container is over the bottom and between the sidewalls. The upper primary portion includes a second conductive constituent configured as a mass filling the interior region of the container. The second conductive constituent is a different composition than the first conductive constituent. One or more conductive projections join to the upper primary portion and extend downwardly from the upper primary portion. Some embodiments include assemblies comprising memory cells over conductive structures. Some embodiments include methods of forming conductive structures.

Abstract: In one example in accordance with the present disclosure a control circuit is described. The control circuit includes a source following component to receive an input voltage and output a switching voltage. The circuit also includes an input leg of a current mirror coupled to the source following component. The input leg of the current mirror replicates the switching voltage to an output leg of the current mirror of a memristive bit cell. The circuit also includes a number of current control components. At least one of the current control components enforces a constant current through the source following component and other current control components maintain the input leg of the current mirror and the output leg of the current mirror at the same current.

Abstract: A semiconductor memory device includes first and second memory cell transistors between first and second select transistors, third and fourth memory cell transistors between third and fourth select transistors, a first word line for first and third memory cell transistors, a second word line for second and fourth memory cell transistors, first to fourth selection gate lines respectively for first through fourth select transistors, a bit line, and a source line. During a read operation, while a voltage applied to the second word line is boosted, voltages applied to the first word line and the third and fourth selection gate line are also boosted, after which the voltage applied to the first word line is lowered, and the third and fourth selection gate lines are discharged. After the time the third and fourth selection gate lines are discharged, voltages applied to the bit line and the source line are boosted.

Abstract: In one embodiment, a device includes a memory cell for storing “0” or “1” as stored data, and a control circuit for reading out the stored data. The memory cell includes area C1/C3 where a cell current increases as a voltage across the cell increases, area C2/C4 where the current is larger than that in C1/C3 and the voltage decreases while the current increases, and area C5 where the current is larger than that in C2/C4 and increases as the voltage increases. The control circuit performs first processing of reading out the stored data such that the current when the data is “0” and the current when the data is “1” take values in C1/C3, and second processing of reading out the stored data such that the current when the data is “0” or the current when the data is “1” takes a value in C2/C4 or C5.

Abstract: A nonvolatile memory device includes a memory cell array including a plurality of first segments having a write data, and a plurality of second segments having a programmed information defining a programmed segment from the plurality of first segments. A randomizer is configured to randomize the write data. An error correction circuit is configured to perform an error correction operation on the write data. A control logic is configured to determine the programmed information from an address received from a memory controller, and to determine whether to operate the randomizer and the error correction circuit based on the determination of the programmed information during the program operation. A page buffer is configured to store the write data and the programmed information during the randomizing and the error correction operation.

Abstract: Provided herein may be a memory device and a method of operating the same. The memory device may include a memory block including a plurality of pages coupled to word lines, respectively, peripheral circuits configured to, during a program operation, perform program, verify, and discharge operations on memory cells coupled to a word line selected from among the word lines, and a control logic configured to control the peripheral circuits such that, during the discharge operation performed after the verify operation, word lines, included in a region in which the program operation has not completed, and word lines, included in a region in which the program operation has completed, among the word lines, are discharged at different times.

Abstract: A nonvolatile memory device for reducing hot-carrier injection (HCI) and a programming method of the nonvolatile memory device, the programming method of the nonvolatile memory device includes programming memory cells included in a cell string in a direction from an upper memory cell adjacent to a string selection transistor to a lower memory cell adjacent to a ground selection transistor from among a plurality of memory cells; when a selected memory cell is programmed, applying a first inhibition voltage to first non-selected word lines connected to first non-selected memory cells located over the selected memory cell; and applying a second inhibition voltage to second non-selected word lines connected to second non-selected memory cells located under the selected memory cell when a predetermined delay time elapses after the first inhibition voltage is applied.

Abstract: A non-volatile memory includes a page buffer array in which page buffers are arranged in a matrix form. A method of operating the non-volatile memory includes selecting columns from among multiple columns of the page buffer array, and counting fail bits stored in page buffers included in the selected columns.

Abstract: According to one embodiment, a semiconductor memory device comprises a first bank and a second bank. Each of the first bank and the second bank comprises a memory cell having a variable resistor element, a reference cell, a sense amplifier having a first input terminal electrically coupled to the memory cell and a second input terminal electrically coupled to the reference cell, and a first transistor electrically coupling the memory cell and the first input terminal of the sense amplifier. A gate of the first transistor of the first hank and a gate of the first transistor of the second bank are independently supplied with a voltage.

Abstract: Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage of a memory cell can shift depending on when the read operation occurs. A memory cell is sensed by discharging a sense node into a bit line and detecting an amount of discharge at two sense times relative to a trip voltage. A bit of data is stored in first and second latches based on the two sense times, to provide first and second pages of data. The pages are evaluated using parity check equations and one of the pages which satisfies the most equations is selected. In another option, word line voltages are grounded and then floated to prevent coupling up of the word line. A weak pulldown to ground can gradually discharge a coupled up voltage of the word lines.

Abstract: A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.

Abstract: A semiconductor memory device includes a memory cell array coupled to a plurality of word lines, a voltage generator generating a program voltage and first and second pass voltages in response to voltage generation control signals, an address decoder selectively applying the program voltage and the first and second pass voltages to the plurality of word lines in response to address decoder control signals, and a control logic controlling the voltage generator and the address decoder to perform a program operation.

Abstract: A nonvolatile memory device includes a voltage generator that sequentially provides a first setup voltage and second setup voltage to a word line of a memory cell array, and control logic including a time control unit that determines a word line setup time for the word line in relation to the second setup voltage based on a difference between the first and second setup voltages.

Abstract: Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage of a memory cell can shift depending on when the read operation occurs. A memory cell is sensed by discharging a sense node into a bit line and detecting an amount of discharge at two sense times relative to a trip voltage. A bit of data is stored in first and second latches based on the two sense times, to provide first and second pages of data. The pages are evaluated using parity check equations and one of the pages which satisfies the most equations is selected. In another option, word line voltages are grounded and then floated to prevent coupling up of the word line. A weak pulldown to ground can gradually discharge a coupled up voltage of the word lines.

Abstract: Apparatus, systems, methods, and computer program products for adaptive power balancing in memory device operations are disclosed. One apparatus includes a power balancing component for the memory device. A power balancing component is configured to determine a first amount of power consumed by each respective operation in a set of operations for a memory device for at least one previous iteration of each respective operation. A power balancing component utilizes a second amount of power to perform a next iteration of each respective operation based on a first amount of power consumed by each respective operation in at least one previous iteration.

Abstract: A semiconductor memory device includes a cell string and a peripheral circuit. The cell string includes a plurality of memory cells coupled between a common source line and a bit line. The peripheral circuit controls a voltage supplied to the cell string to program a selected memory cell of the cell string by performing a program loop including a program section, a detrap section, and a verify section. Also, the peripheral circuit is configured to supply a program voltage to a word line coupled to the selected memory cell among the plurality of memory cells during the program section. The peripheral circuit further supplies a detrap voltage to the cell string during the detrap section and supplies a verify voltage to the word line during the verify section.

Abstract: Apparatuses and methods for providing a program voltage responsive to a voltage determination are described. An example apparatus includes a memory array comprising a plurality of access lines. The example apparatus further includes a memory access circuit coupled to the memory array. The memory access circuit is configured to, during a memory program operation, provide an inhibit voltage to the plurality of access lines. The memory access circuit is further configured to, during the memory program operation, provide a program voltage to a target access line of the plurality of access lines responsive to a determination that an access line of the plurality of access lines has a voltage equal to or greater than a threshold voltage. The threshold voltage is less than the inhibit voltage.

Abstract: A storage device includes a data memory unit and a status memory unit. The data memory unit includes a pair of flash memory cells to be read by a complementary read mode, and 1-bit data is stored therein by the pair of flash memory cells. The status memory unit includes a flash memory cell to be read by a reference read mode, and a status flag is stored therein by the flash memory cell.

Abstract: In a method of programming a three-dimensional nonvolatile memory device, a program loop is executed at least one time. The program loop includes a programming step for programming selected memory cells among memory cells and a verifying step for verifying whether the selected memory cells are program-passed or not. In programming the selected memory cells, a level of a voltage being applied to a common source line connected to the memory cells in common may be changed. Thus, in a program operation, power consumption which is needed to charge-discharge the common source line can be decreased while increasing boosting efficiency.

Abstract: Systems, apparatuses, and methods are provided that refresh data in a memory. Data is programmed into the memory. After which, part or all of the data may be refreshed. The refresh of the data may be different from the initial programming of the data in one or more respects. For example, the refresh of the data may include fewer steps than the programming of the data and may be performed without erasing a section of memory. Further, the refresh of the data may be triggered in one of several ways. For example, after programming the data, the data may be analyzed for errors. Based on the number of errors found, the data may be refreshed.

Abstract: A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section.

Abstract: Systems and methods for internal copy-back with read-verify are described. In one embodiment, a storage device includes a controller to select a first single level cell (SLC) page of a plurality of SLC pages on the storage device to transfer to a triple level cell (TLC) page. The controller, in conjunction with an error correcting code (ECC) decoder, read-verifies the first SLC page. Read-verifying the first SLC page includes reading the first SLC page to an internal page buffer, decoding the first SLC page read into the internal page buffer, determining a number of errors contained in the first SLC page based at least in part on the decoding, and verifying whether the number of errors contained in the first SLC page satisfies an error threshold. The controller transfers the first SLC page to the TLC page according to a result of read-verifying the first SLC page.

Abstract: A memory array and a method for reading, programming and erasing the same are provided. The memory array includes flash memory cells arranged in an array, each flash memory cell includes a first and a second split-gate flash memory cell; a first control gate of the first split-gate flash memory cell is connected with a first control gate of the second split-gate flash memory cell and a first control gate line, a second control gate of the first split-gate flash memory cell is connected with a second control gate of the second split-gate flash memory cell and a second control gate line; a word line gate of the first split-gate flash memory cell is connected with a word line gate of the second split-gate flash memory cell and a word line; two drains of the first and second split-gate flash memory cells share a same bit line.

Abstract: According to an embodiment, a semiconductor memory, on receiving a first command, applies a voltage within a first range and a voltage within a second range to a word line and reads a first bit from a memory cell, and, on receiving a second command, applies a voltage within a third range to the word line and reads a second bit from the memory cell. The controller issues the first command a plurality of times and changes the voltages to be applied to the word line within the first range and the second range in accordance with the plurality of first commands, specifies a first and second voltage within the first and the second range, respectively, and estimates a third voltage within the third range. The voltage applied to read the second bit is the estimated third voltage.

Abstract: The disclosed technology relates to a memory device configured to perform multiple access operations in response to a single command received through a memory controller and a method of performing the multiple access operations. In one aspect, the memory device includes a memory array comprising a plurality of memory cells and a memory controller. The memory controller is configured to receive a single command which specifies a plurality of memory access operations to be performed on the memory array. The memory controller is further configured to cause the specified plurality of memory access operations to be performed on the memory array.

Abstract: The present disclosure includes apparatuses and methods related to accessing data in memory. One example method comprises storing data associated with a first operation in a first sense amplifier responsive to receiving a request to perform a second operation, and performing the second operation associated with a row of memory cells while the data associated with the first operation is being stored in the first sense amplifier.