Particular Biasing Patents (Class 365/185.18)
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Patent number: 9818760Abstract: A memory structure includes stacks, memory layers, channel layers, dielectric layers, and first conductive lines. Each stack includes a group of alternating conductive strips and insulating strips. The memory layers are conformally disposed on the stacks. The channel layers are conformally disposed on the memory layers. The dielectric layers are disposed on portions of the channel layers at first sides of the stacks and portions of the channel layers at second sides of the stacks. The first conductive lines are disposed along sidewalls of the stacks. The first conductive lines are isolated from the channel layers by the dielectric layers. One first conductive line disposed at the first side of one stack is isolated from one first conductive line disposed at the second side of the same stack and isolated from one first conductive line disposed at the second side of an adjacent stack.Type: GrantFiled: March 20, 2017Date of Patent: November 14, 2017Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Erh-Kun Lai, Hsiang-Lan Lung
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Patent number: 9805795Abstract: A non-volatile data retention circuit, which is configured to store complementary volatile charge states of an external latch, comprises a coupled giant spin hall latch configured to generate and store complementary non-volatile spin states corresponding to the complementary volatile charge states of the external latch in response to receiving a charge current from the external latch, and to generate a differential charge current signal corresponding to the complementary non-volatile spin states in response to application of a read voltage, a write switch coupled to the coupled giant spin hall latch and configured to selectively enable flow of the charge current from the external latch to the coupled giant spin hall latch in response to a sleep signal, and a read switch coupled to the coupled giant spin hall latch and to selectively enable the application of the read voltage to the coupled giant spin hall latch.Type: GrantFiled: September 14, 2016Date of Patent: October 31, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Titash Rakshit, Borna Obradovic
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Patent number: 9786380Abstract: A semiconductor memory device includes a memory cell includes a charge storage layer, a word line that is connected to a gate of the memory cell, and a controller that performs a write operation on the memory cell by applying a write voltage to the word line, and a verify operation to verify a threshold voltage of the memory cell after the write operation. The verify operation includes a first verify operation using a first verify voltage, and a second verify operation using a second verify voltage higher than the first verify voltage.Type: GrantFiled: August 10, 2016Date of Patent: October 10, 2017Assignee: Toshiba Memory CorporationInventor: Shinji Suzuki
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Patent number: 9779815Abstract: A method can be used for writing in a memory location of the electrically-erasable and programmable memory type. The memory location includes a first memory cell with a first transistor having a first gate dielectric underlying a first floating gate and a second memory cell with a second transistor having a second gate dielectric underlying a second floating gate that is connected to the first floating gate. In a first writing phase, an identical tunnel effect is implemented through the first gate dielectric and the second gate dielectric. In a second writing phase, a voltage across the first gate dielectric but not the second gate dielectric is increased.Type: GrantFiled: July 27, 2016Date of Patent: October 3, 2017Assignee: STMICROELECTRONICS (ROUSSET) SASInventor: François Tailliet
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Patent number: 9779833Abstract: A method of programming a flash memory device, which is a nonvolatile memory device including a plurality of pages, includes executing an Nth program loop of a program operation by applying an Nth selected program voltage to a selected word line from among the plurality of pages, and performing a program verify operation by applying a program verify voltage to the selected word line, counting the number of memory cells having a threshold voltage which is greater than or equal to the program verify voltage, from among memory cells connected to the selected word line, generating a program voltage revision value based on a result of the counting and an operational condition of the Nth program loop, and adding the program voltage revision value to an Mth preset program voltage of an Mth program loop executed after the Nth program loop where M>N.Type: GrantFiled: October 12, 2016Date of Patent: October 3, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-Hyun Joo, Jae-Woo Im
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Patent number: 9779817Abstract: A method for programming a non-volatile memory device includes concurrently boosting channels of memory cells in a selected memory string and an unselected memory string of the memory device, discharging the boosted channels of the memory cells in the selected memory string, and programming a selected memory cell in the selected memory string after discharging the boosted channels in the selected memory string.Type: GrantFiled: June 16, 2015Date of Patent: October 3, 2017Assignee: Micron Technology, Inc.Inventors: Violante Moschiano, Akira Goda, Mason A. Jones
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Patent number: 9779820Abstract: A non-volatile memory and a programming method thereof are provided. The programming method for the non-volatile memory includes: setting at least one first isolation cell between a first side cell and at least one first pass cell of an inhibited memory string; cutting off the at least one first isolation cell and providing a pre-boosting voltage to a word line of the first side cell and at a first time point; turning on the at least one first isolation cell at a second time point for transporting the pre-boosting potential to channels of the at least one first pass cell and a primary cell at a second time period; and providing a boosting voltage to word lines of the at least one first pass cell during a boosting time period.Type: GrantFiled: February 23, 2017Date of Patent: October 3, 2017Assignee: MACRONIX International Co., Ltd.Inventors: Ya-Jui Lee, Kuan-Fu Chen
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Patent number: 9767407Abstract: Provided are a weighting device that may be driven at a low voltage and is capable of embodying multi-level weights, a neural network, and a method of operating the weighting device. The weighting device includes a switching layer that may switch between a high resistance state and a low resistance state based on a voltage applied thereto and a charge trap material layer that traps or discharges charges according to a resistance state of the switching layer. The weighting device may be used for controlling a weight in a neural network.Type: GrantFiled: September 16, 2016Date of Patent: September 19, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Seongho Cho, Inkyeong Yoo, Hojung Kim
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Patent number: 9761318Abstract: A memory device capable of narrowing the threshold voltage distribution thereof includes word lines, bit lines, memory cells, a word line driver configured to apply voltage to a selected word line, a sense amplifier circuit configured to detect data of the memory cell, and a controller configured to control the word line driver and the sense amplifier. A write sequence includes a write operation in which write voltage is applied to the selected word line by the word line driver, and a verify operation in which, when a threshold voltage of the selected memory cell reaches a reference voltage, writing to the selected memory cell is completed. Based on second data that is written later than the first data to an adjacent memory cell adjacent to the selected memory cell, the controller changes the reference voltage used for completing the writing to the selected memory cell.Type: GrantFiled: August 31, 2016Date of Patent: September 12, 2017Assignee: Toshiba Memory CorporationInventor: Shigeo Kondo
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Patent number: 9761320Abstract: A memory device and associated techniques for reducing read disturb of memory cells during the last phase of a sensing operation when all voltage signals are ramped down to a steady state voltage. In one aspect, the voltages of the source side word line, WL0, and an adjacent dummy word line, WLDS1, are ramped down after the voltages of remaining word lines are ramped down. This can occur regardless of whether WL0 is the selected word line which is programmed or read. The technique can be applied after the sensing which occurs in a read or program-verify operation. Another option involves elevating the voltage of the selected word line so that all word lines are ramped down from the same level, such as a read pass level. The techniques are particularly useful when the memory device includes an interface in the channel between epitaxial silicon and polysilicon.Type: GrantFiled: December 19, 2016Date of Patent: September 12, 2017Assignee: SanDisk Technologies LLCInventors: Hong-Yan Chen, Ching-Huang Lu, Wei Zhao
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Patent number: 9761308Abstract: Reading requested data from flash memory using a first read level voltage. A number of first bit-value errors and a number of second bit-value errors is determined from the read requested data. An error ratio of the number of first bit-value errors and the number of second bit-value errors is compared to an error-ratio range. The first level voltage is adjusted based on the comparison of the error ratio to the error-ratio range.Type: GrantFiled: March 11, 2016Date of Patent: September 12, 2017Assignee: Western Digital Technologies, Inc.Inventor: Aldo G. Cometti
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Patent number: 9740609Abstract: A technique for garbage collection in a data storage system includes determining a dirty physical byte count for each of a plurality of candidate garbage collection units. The dirty physical byte count provides a total amount of dirty bytes. At least one of a dirty physical codeword container count and a dirty physical page count is determined for each of the candidate garbage collection units. The dirty physical codeword container count provides an amount of physical codeword containers that are completely dirty and the dirty physical page count provides an amount of physical pages that are completely dirty. A garbage collection unit, included in the candidate garbage collection units, is selected for garbage collection based on the dirty physical byte count and at least one of the dirty physical codeword container count and the dirty physical page count.Type: GrantFiled: February 19, 2016Date of Patent: August 22, 2017Assignee: International Business Machines CorporationInventors: Razik S. Ahmed, Timothy J. Fisher, Aaron D. Fry, Nikolas Ioannou, Jason Ma, Matthew R. Orr, Roman A. Pletka, Lincoln T. Simmons, Sasa Tomic
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Patent number: 9741427Abstract: Apparatuses and methods for performing logical operations using sensing circuitry are disclosed. An apparatus comprises an array of memory cells, sensing circuitry coupled to the array of memory cells via a sense line, and a controller coupled to the array of memory cells and the sensing circuitry. The sensing circuitry includes a sense amplifier and does not include an accumulator. The controller is configured to perform logical operations using the array of memory cells as an accumulator without transferring data out of the memory array and sensing circuitry.Type: GrantFiled: September 9, 2016Date of Patent: August 22, 2017Assignee: Micron Technology, Inc.Inventor: Glen E. Hush
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Patent number: 9735167Abstract: A semiconductor memory device according to one embodiment, includes a plurality of first interconnects extending in a first direction and arrayed along a second direction crossing the first direction, a plurality of semiconductor pillars arrayed in a row along the first direction in each of spaces among the first interconnects and extending in a third direction crossing the first direction and the second direction, a first electrode disposed between one of the semiconductor pillars and one of the first interconnects, a first insulating film disposed between the first electrode and one of the first interconnects, a first insulating member disposed between the semiconductor pillars in the first direction and extending in the third direction and opposed the first interconnects not via the first insulating film.Type: GrantFiled: August 31, 2015Date of Patent: August 15, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Tatsuya Kato, Fumitaka Arai, Satoshi Nagashima, Katsuyuki Sekine, Yuta Watanabe, Keisuke Kikutani, Atsushi Murakoshi
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Patent number: 9728550Abstract: According to one embodiment, a method for manufacturing a semiconductor memory device includes forming a stacked body by alternately stacking an insulating film and a conductive film. The method includes forming a trench in the stacked body. The trench extends in one direction and divides the conductive film. The method includes burying a diblock copolymer in the trench. The method includes phase-separating the diblock copolymer into a plurality of first blocks and an insulative second block extending in a stacking direction of the insulating film and the conductive film. The method includes forming a plurality of holes by removing the first blocks. The method includes forming charge accumulation layers on inner surfaces of the holes. And, the method includes forming a plurality of semiconductor pillars extending in the stacking direction by burying a semiconductor material in the holes.Type: GrantFiled: December 28, 2015Date of Patent: August 8, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventor: Mitsuhiro Omura
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Patent number: 9728262Abstract: Non-volatile memory systems with multi-write direction memory units are disclosed. In one implementation an apparatus comprises a non-volatile memory and a controller in communication with the non-volatile memory. The controller is configured to select an empty memory block of the non-volatile memory for the storage of data; examine an identifier associated with the memory block to determine a write direction for the storage of data; and write data to the memory block beginning with an initial word line of the memory block or a last word line of the memory block dependent on the write direction. The controller is further configured to erase the memory unit and, in response to erasing the memory unit, modify the identifier to change the write direction for a subsequent write of data to the memory block.Type: GrantFiled: October 30, 2015Date of Patent: August 8, 2017Assignee: SanDisk Technologies LLCInventors: Ivan Baran, Aaron Lee, Mrinal Kochar, Mikhail Palityka, Dennis Ea, Yew Yin Ng, Abhijeet Bhalerao
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Patent number: 9720754Abstract: A table of error counts is generated based on reading wordlines of a flash memory device, the table storing an error count for each combination of wordline and respective read level voltage used to read the wordlines. A plurality of offset wordline groups are generated based on the table of error counts, with each group associating a different read level offset voltage with a plurality of wordline addresses. A storage device is configured to read memory cells using a read level offset voltage of a generated offset wordline group associated with a wordline address of the memory cells to be read. After a predetermined point in a life cycle of a respective memory block, the table is regenerated and plurality of offset wordline groups are regenerated based the regenerated table of error counts.Type: GrantFiled: March 20, 2015Date of Patent: August 1, 2017Assignee: Western Digital Technologies, Inc.Inventors: Seyhan Karakulak, Anthony Dwayne Weathers, Richard David Barndt
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Patent number: 9715939Abstract: Systems and methods disclosed herein are used to efficiently manage low read data. In one aspect, a method includes, in response to detecting occurrence of a first event (e.g., PFail), writing low read data to non-volatile memory of a storage device with a fast SLC programming mode, distinct from a default SLC programming mode. Writing the low read data with the fast SLC programming mode: (i) includes using one or more memory programming parameters distinct from a default set of memory programming parameters used for writing data with the default SLC programming mode and (ii) takes less time per predefined unit of data than writing data with the default SLC programming mode. The method also includes: in response to detecting occurrence of a second event (e.g., host write command), writing data corresponding to the second event with the default SLC programming mode using the default set of memory programming parameters.Type: GrantFiled: October 28, 2015Date of Patent: July 25, 2017Assignee: SANDISK TECHNOLOGIES LLCInventors: Robert W. Ellis, James M. Higgins
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Patent number: 9711197Abstract: Provided herein is a memory device including a plurality of memory blocks comprising a plurality of memory blocks each comprising a plurality of memory cells; a peripheral circuit coupled to the memory cells through bit lines, and suitable for sensing currents of the bit lines varying according to threshold voltages of the memory cells; and a control logic suitable for controlling the peripheral circuit so that the current amount of the bit lines vary during a program operation of the memory cells.Type: GrantFiled: August 17, 2016Date of Patent: July 18, 2017Assignee: SK Hynix Inc.Inventor: Jae Woong Kim
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Patent number: 9711520Abstract: A semiconductor memory device includes a semiconductor substrate including a common source region and a drain region, a lower structure provided on the semiconductor substrate and including a plurality of lower transistors connected in series between the common source region and the drain region, a stack including a plurality of word lines stacked on the lower structure, and semiconductor pillars penetrating the stack and controlling gate electrodes of respective ones of the lower transistors.Type: GrantFiled: June 10, 2015Date of Patent: July 18, 2017Assignee: Samsung Electronics Co., LtdInventors: Etienne Nowak, Xia Zhiliang, Daesin Kim, Young-Gu Kim, Narae Jeong
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Patent number: 9711212Abstract: A system includes a cross-point memory array and a decoder circuit coupled to the cross-point memory array. The decoder circuit includes a predecoder having predecode logic to generate a control signal and a level shifter circuit to generate a voltage signal. The decoder circuit further includes a post-decoder coupled to the predecoder, the post-decoder including a first stage and a second stage coupled to the first stage, the control signal to control the first stage and the second stage to route the voltage signal through the first stage and the second stage to a selected conductive array line of a plurality of conductive array lines coupled to a memory array.Type: GrantFiled: April 4, 2016Date of Patent: July 18, 2017Assignee: Unity Semiconductor CorporationInventors: Christophe Chevallier, Chang Hua Siau
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Patent number: 9704586Abstract: A flash memory device. The flash memory device comprises a controller, a plurality of flash memories, and a voltage control circuit. The voltage control circuit comprises a boost converter, a buck converter, and a voltage controller. The boost converter receives a system voltage to generate a first high voltage. The buck converter receives the first high voltage and provides an output voltage to the controller and the flash memories. The voltage controller detects the output voltage generated by the buck converter, and therefore generates a feedback signal. When the voltage controller receives a physical destruction control signal from a host computer, the buck converter will generate an output signal with high level according to the control of the feedback signal. Afterwards, semiconductor physical elements of the controller and the flash memories will be burned by the output signal with high level.Type: GrantFiled: November 11, 2016Date of Patent: July 11, 2017Assignee: INNODISK CORPORATIONInventor: Chih-Chieh Kao
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Patent number: 9704589Abstract: A nonvolatile memory device includes a nonvolatile memory cell coupled to a bit line. The nonvolatile memory device may include a sensing circuit configured to output a sensing output signal for sensing a status of the nonvolatile memory cell based on a sensing input signal inputted to the sensing circuit through a sensing input line. The nonvolatile memory device may include a folding circuit coupled to the bit line to output the sensing input signal having a voltage low level or a voltage high level according to a voltage level of the bit line.Type: GrantFiled: August 8, 2016Date of Patent: July 11, 2017Assignee: SK hynix Inc.Inventor: Hoe Sam Jeong
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Patent number: 9697906Abstract: A controlling block for a non-volatile memory device including a switching element coupling a bit-line with the corresponding page buffer, includes: a look-up table configured to store a plurality of address zones; and a matching logic configured to match one address zone among the plurality of address zones based on an inputted row address and generate a bias voltage, based on the address zone, to the switching element for reading operation of the non-volatile memory, wherein the plurality of address zones are defined by grouping word-lines having a I-V characteristic which differs for a current value different from a prefixed value.Type: GrantFiled: July 19, 2016Date of Patent: July 4, 2017Assignee: SK Hynix Inc.Inventor: Alessandro Sanasi
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Patent number: 9698233Abstract: Tunnel insulation layer structures and methods of manufacturing the same are disclosed. The tunnel insulation layer structures may include a first tunnel insulation layer, a second tunnel insulation layer, a third tunnel insulation layer, a fourth tunnel insulation layer and a fifth tunnel insulation layer. The first tunnel insulation layer on a substrate has a first band gap energy. The second tunnel insulation layer on the first tunnel insulation layer has a second band gap energy which is lower than the first band gap energy. The third tunnel insulation layer on the second tunnel insulation layer has a third band gap energy which is higher than the second band gap energy. The fourth tunnel insulation layer on the third tunnel insulation layer has a fourth band gap energy which is lower than the third band gap energy. The fifth tunnel insulation layer on the fourth tunnel insulation layer has a fifth band gap energy which is higher than the fourth band gap energy.Type: GrantFiled: March 11, 2015Date of Patent: July 4, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Eun-Yeoung Choi, Young-Jin Noh, Bi-O Kim, Kwang-Min Park, Jae-Young Ahn, Ju-Mi Yun, Jae-Ho Choi, Ki-Hyun Hwang
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Patent number: 9691489Abstract: A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array and a control circuit. The control circuit executes a first reading operation and a second reading operation. The first reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between a control gate electrode and source of the selected memory cell to a first value. The second reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between the control gate electrode and source of the selected memory cell to a second value lower than the first value. When executing the second reading operation, the control circuit keeps a voltage of the control gate electrode of the selected memory cell to 0 or a positive value.Type: GrantFiled: September 13, 2016Date of Patent: June 27, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Yasuhiro Shiino, Eietsu Takahashi, Koki Ueno
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Patent number: 9691980Abstract: A method for forming a memory device is provided. The method includes forming a plurality of memory cells. The method also includes performing a first baking on the memory cells. The method further includes setting a specified current, and after performing the first baking, performing a test process on the memory cells. The test process includes reading the current of the memory cells. When the read current of the memory cells is larger than or equal to the specified current, the test process of the memory cell is done. When the read current of the memory cells is smaller than the specified current, a re-forming process is performed on the memory cells to form a plurality of re-formed memory cells, and then the test process is performed on the re-formed memory cells.Type: GrantFiled: October 24, 2016Date of Patent: June 27, 2017Assignee: WINBOND ELECTRONICS CORP.Inventors: Chia-Hung Lin, Lih-Wei Lin, I-Hsien Tseng, Tsung-Huan Tsai
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Patent number: 9691879Abstract: Disclosed is a semiconductor device. The semiconductor device may include a first pipe gate including a trench extended in a first direction. The semiconductor device may include a second pipe gate formed in the first direction and spaced apart from the surface of the trench, and configured to divide the trench into a first space and a second space. The semiconductor device may include a partition pipe gate extended in a second direction crossing the first direction, and configured to divide the first space into first areas, and divide the second space into second areas. The semiconductor device may include a first pipe channel formed inside each of the first areas, and a second pipe channel formed inside each of the second areas.Type: GrantFiled: August 4, 2015Date of Patent: June 27, 2017Assignee: SK hynix Inc.Inventor: Nam Jae Lee
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Patent number: 9691484Abstract: A semiconductor memory device includes a memory cell unit, word lines, a driver circuit, and first transistors. The word lines are connected to the control gates of 0-th to N-th memory cells. The (N+1) number of first transistors transfer the voltage to the word lines respectively. Above one of the first transistors which transfers the voltage to an i-th (i is a natural number in the range of 0 to N) word line, M (M<N) of the word lines close to the i-th word line pass through a region above the gate electrode by a first level interconnection without passing over the impurity diffused layers.Type: GrantFiled: April 4, 2016Date of Patent: June 27, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Takatoshi Minamoto, Toshiki Hisada, Dai Nakamura
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Patent number: 9685339Abstract: A split gate memory array includes a first row having memory cells; a second row having memory cells, wherein the second row is adjacent to the first row; and a plurality of segments. Each segment includes a first plurality of memory cells of the first row, a second plurality of memory cells of the second row, a first control gate portion which forms a control gate of each memory cell of the first plurality of memory cells, and a second control gate portion which forms a control gate of each memory cell of the second plurality of memory cells. The first control gate portion and the second control gate portion converge to a single control gate portion between neighboring segments of the plurality of segments.Type: GrantFiled: April 30, 2013Date of Patent: June 20, 2017Assignee: NXP USA, Inc.Inventors: Jane A. Yater, Cheong Min Hong, Sung-Taeg Kang, Ronald J. Syzdek
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Patent number: 9679657Abstract: A method of operating a semiconductor memory device including a plurality of cell strings coupled to dummy word lines and normal word lines includes performing a first sub-program operation on selected normal memory cells by sequentially applying first program pulses to a selected normal word line and performing a second sub-program operation on the selected normal memory cells by sequentially applying second program pulses greater than the first program pulses to the selected normal word line, wherein at least one of the dummy word lines is biased in a same manner as the selected normal word line whenever each of the first program pulses is applied to the selected normal word line.Type: GrantFiled: January 5, 2016Date of Patent: June 13, 2017Assignee: SK hynix Inc.Inventors: Kyoung Jin Park, Sung Ho Bae, Byeong Il Han
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Patent number: 9672915Abstract: A storage device includes a nonvolatile memory device and a memory controller configured to control the nonvolatile memory device in response to a request from a host. The memory controller is configured to employ state information related to the confidence level of a power supply to determine a reliability level with respect to an access operation of the memory device and to perform a reliability guarantee operation corresponding to the determined reliability level.Type: GrantFiled: January 14, 2016Date of Patent: June 6, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Hyunchul Park, Se-Wook Na, Young-Jae Jung, Durina Park
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Patent number: 9666299Abstract: According to one embodiment, there is provided a non-volatile semiconductor storage device including a non-volatile memory, a monitoring section, a determining section, and a notification processing section. The non-volatile memory includes a plurality of memory cells driven by word lines and a voltage generating section that generates a read voltage to be applied to the word lines. The monitoring section monitors a change in a threshold distribution of the plurality of memory cells upon performing a read processing to read data from the plurality of memory cells by applying the read voltage to the word lines. The determining section determines a degree of deterioration of the non-volatile memory in accordance with a monitoring result by the monitoring section. The notification processing section notifies a life of the non-volatile memory in accordance with a determining result by the determining section.Type: GrantFiled: September 6, 2016Date of Patent: May 30, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventor: Naoki Matsunaga
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Patent number: 9658789Abstract: A storage module and method are provided for optimized power utilization. In one embodiment, a storage module is provided comprising a storage controller and a plurality of memory dies in communication with the storage controller. The storage controller determines if sufficient power is available to perform an operation on one of the memory dies. In response to determining that sufficient power is not available to perform the operation on one of the memory dies, the storage controller determines if suspending an in-progress operation on another one of the memory dies would provide enough power to perform the operation. In response to determining that suspending the in-progress operation would provide enough power to perform the operation, the storage controller suspends the in-progress operation and performs the operation. Instead of suspending an in-progress operation, the storage controller can instead use a reduced power version of the operation or the in-progress operation.Type: GrantFiled: August 5, 2014Date of Patent: May 23, 2017Assignee: SanDisk Technologies LLCInventor: Eran Erez
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Patent number: 9653143Abstract: Apparatuses, memory section control circuits, and methods of refreshing memory are disclosed. An example apparatus includes a plurality of memory sections and a plurality of memory section control circuits. Each memory section control circuit is coupled to a respective one of the plurality of memory sections and includes a plurality of access line drivers, each of which includes a plurality of transistors having common coupled gates. During an operation of the apparatus a first voltage is provided to the commonly coupled gates of the transistors of at least some of the access line drivers of the memory section control circuit coupled to an active memory section and a second voltage is provided to the commonly coupled gates of the transistors of the access line drivers of the memory section control circuit coupled to an inactive memory section control circuit, wherein the first voltage is greater than the second voltage.Type: GrantFiled: June 1, 2016Date of Patent: May 16, 2017Assignee: Micron Technology, Inc.Inventors: John David Porter, Gi-Hong Kim
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Patent number: 9627974Abstract: A voltage regulator circuit includes: a comparator configured to have a first input coupled to an output voltage of the voltage regulator circuit; a second input coupled to a reference voltage and an output signal; a first transistor; a second transistor, a drain of the first transistor connected to a drain of the second transistor; an inductor connected to the drain of the first transistor and the drain of the second transistor; a capacitor and a resistor connected in parallel, between the output node and a source of the second transistor; a peak-current detector unit configured to detect peak current in the inductor; a zero-crossing detector unit configured to detect a zero-crossing current in the inductor; and a control unit configured to receive a plurality of input signals including at least an input voltage and a clock signal.Type: GrantFiled: October 30, 2015Date of Patent: April 18, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ruopeng Wang, Alan Roth, Eric Soenen
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Patent number: 9627075Abstract: A semiconductor memory device may include: a memory cell array comprising a plurality of memory cells coupled to a plurality of bit line pairs and a plurality of word lines; and an operation circuit suitable for setting a parameter corresponding to an input command, and performing an operation corresponding to the input command on the memory cell array based on the set parameter, wherein, when the input command is of the same type as a previous input command, the operation circuit skips setting the parameter for each of preset word line groups.Type: GrantFiled: May 5, 2016Date of Patent: April 18, 2017Assignee: SK Hynix Inc.Inventor: Won-Sun Park
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Patent number: 9613706Abstract: A method includes sending a number of program/erase cycles from a memory of control logic of a memory device to a counter of the control logic, where the number of program/erase cycles has been previously applied to one or more memory cells of an array of memory cells of the memory device, using the counter to increment the number of program/erase cycles each time an additional program/erase cycle is applied to the one or more memory cells, using compare logic of the control logic to compare the incremented number of program/erase cycles to a numerical value, and using starting-voltage level control logic of the control logic to adjust a program starting voltage level and/or an erase starting voltage level based on the comparison of the incremented number of program/erase cycles to the numerical value.Type: GrantFiled: March 3, 2016Date of Patent: April 4, 2017Assignee: Micron Technology, Inc.Inventors: June Lee, Fred Jaffin, III
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Patent number: 9613980Abstract: A semiconductor memory device includes a substrate, a plurality of first control gate electrodes, a plurality of second control gate electrodes, first to second select gate electrodes, first to second gate electrodes, a bit line, first to second semiconductor pillars, and a controller. The controller applies a first potential to the first select gate electrode, a third potential lower than the first potential to the second select gate electrode, a second potential to the first gate electrode and the second gate electrode, a selecting potential not less than the third potential to one of the plurality of the first control gate electrodes, and an unselecting potential higher than the selecting potential to other than the one of the plurality of first control gate electrodes in a reading operation.Type: GrantFiled: March 14, 2016Date of Patent: April 4, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Kenta Yamada, Yasuhiro Uchiyama
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Patent number: 9613973Abstract: The present disclosure includes memory having a continuous channel, and methods of processing the same. A number of embodiments include forming a vertical stack having memory cells connected in series between a source select gate and a drain select gate, wherein forming the vertical stack includes forming a continuous channel for the source select gate, the memory cells, and the drain select gate, and removing a portion of the continuous channel for the drain select gate such that the continuous channel is thinner for the drain select gate than for the memory cells and the source select gate.Type: GrantFiled: August 20, 2015Date of Patent: April 4, 2017Assignee: Micron Technology, Inc.Inventors: Luan C. Tran, Hongbin Zhu, John D. Hopkins, Yushi Hu
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Patent number: 9608566Abstract: When a voltage difference between a raised output voltage vcp and an input voltage vin is larger than a set voltage value, based on a added-on voltage vup detected by a voltage monitor 3 or a current iu passing through the voltage monitor 3, the clock generator controller 4 is activated. Then the clock generator controller 4 draws in a frequency control current iw from a clock generator 1 side, switches the frequency Fclk of a clock signal CLK generated by the clock generator 1 from a first frequency, which is comparatively high, to a second frequency, which is one or more digits lower than the first frequency, and applies the clock signal CLK to the voltage raiser 2. The voltage raiser 2 saves power by performing voltage raising (charge pumping) at the second frequency.Type: GrantFiled: March 18, 2016Date of Patent: March 28, 2017Assignee: Rohm Co., Ltd.Inventor: Tadashi Akaho
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Patent number: 9601502Abstract: A recessed region can be formed on a semiconductor substrate, and peripheral semiconductor devices can be formed on a recessed horizontal surface of the semiconductor substrate. An alternating stack of insulating layers and sacrificial material layers are formed over the semiconductor substrate, and memory stack structures are formed therethrough. Contact openings extending to sacrificial material layers located at different depths can be formed by sequentially exposing a greater number of openings in a mask layer by iterative alternation of trimming of a slimming layer over the mask layer and an anisotropic etch that recesses pre-existing contact openings by one level. Electrically conductive via structures extending to electrically conductive electrodes located at different level can be provided with self-aligned insulating liners.Type: GrantFiled: July 15, 2016Date of Patent: March 21, 2017Assignee: SANDISK TECHNOLOGIES LLCInventors: Michiaki Sano, Keisuke Izumi
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Patent number: 9601191Abstract: To improve the write performance of PCM, the disclosed technology, in certain embodiments, provides a new write scheme, referred to herein as two-stage-write, which leverages the speed and power asymmetries of writing a zero bit and a one bit. Writing a data block to PCM is divided into two separated stages, i.e., write-0 stage and write-1 stage. Without violating power constraints, during the write-0 stage, all zero bits in this data block are written to PCM at an accelerated speed; during the write-1 stage, all one bits are written to PCM, with more bits being written concurrently. In certain embodiments, the disclosed technology provides a new coding scheme to improve the speed of the write-1 stage by further increasing the number of bits that can be written to PCM in parallel.Type: GrantFiled: December 20, 2013Date of Patent: March 21, 2017Assignee: UNIVERSITY OF MAINE SYSTEM BOARD OF TRUSTEESInventors: Yifeng Zhu, Jianhui Yue
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Patent number: 9595318Abstract: Apparatuses, systems, methods, and computer program products are disclosed for reduced level cell solid-state storage. A method includes determining that an erase block of a non-volatile storage device is to operate in a reduced level cell (RLC) mode. The non-volatile storage device may be configured to store at least three bits of data per storage cell. A method includes instructing the non-volatile storage device to program first and second pages of the erase block with data. A method includes instructing the non-volatile storage device to program a third page of the erase block with a predefined data pattern. Programming of a predefined data pattern may be configured to adjust which abodes of the erase block are available to represent stored user data values.Type: GrantFiled: December 30, 2015Date of Patent: March 14, 2017Assignee: SANDISK TECHNOLOGIES LLCInventors: Jea Hyun, Ryan Haynes, Charla Mosier, Rick Lucky, Robert Wood
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Patent number: 9594516Abstract: A memory device comprising a memory array comprising a plurality of memory cells, two or more fuses coupled to the memory array, wherein each of the two or more fuses contains trim data for the memory array and a mode register for selecting one of the two or more fuses to be enabled.Type: GrantFiled: February 14, 2014Date of Patent: March 14, 2017Assignee: Sony Semiconductor Solutions CorporationInventors: Makoto Kitagawa, Takafumi Kunihiro, Wataru Otsuka, Tomohito Tsushima
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Patent number: 9595306Abstract: A control signal generation circuit may include: a counting unit suitable for generating counting information; a first signal generation unit suitable for activating/deactivating a first signal based on the counting information, first rising information, and first falling information; a second signal generation unit suitable for activating/deactivating a second signal based on the counting information, second rising information, second falling information, and the first falling information; and a control signal driving unit suitable for driving a control signal in response to the first and second signals.Type: GrantFiled: September 18, 2015Date of Patent: March 14, 2017Assignee: SK Hynix Inc.Inventor: Byung-Ryul Kim
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Patent number: 9595342Abstract: Techniques are provided for periodically monitoring and adjusting the threshold voltage levels of memory cells in a charge-trapping memory device. When a criterion is met, such as based on the passage of a specified time period, the memory cells are read to classify them into different subsets according to an amount of downshift in threshold voltage (Vth). Two or more subsets can be used per data state. A subset can also comprise cells which are corrected using Error Correction Code (ECC) decoding. The subsets of memory cells are refresh programmed, without being erased, in which a Vth upshift is provided in proportion to the Vth downshift. The refresh programming can use a fixed or adaptive number of program pulses per subset. Some cells will have no detectable Vth downshift or a minor amount of Vth downshift which can be ignored. These cells need not be refresh programmed.Type: GrantFiled: January 20, 2015Date of Patent: March 14, 2017Assignee: SanDisk Technologies LLCInventors: Liang Pang, Yingda Dong, Jian Chen
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Patent number: 9589646Abstract: A page buffer circuit includes a plurality of page buffers including a first page buffer. The first page buffer is configured to load input data of the first page buffer, and input data of at least one neighboring page buffer. The first page buffer is also configured to apply a bias corresponding to the input data of the first page buffer, and the input data of the at least one neighboring page buffer to a bit line.Type: GrantFiled: November 26, 2014Date of Patent: March 7, 2017Assignee: Macronix International Co., Ltd.Inventors: Chung-Kuang Chen, Han-Sung Chen, Chun-Hsiung Hung
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Patent number: 9589652Abstract: A method of performing an operation on a non-volatile memory (NVM) cell of a memory device is disclosed. The pass transistor of the NVM cell is an asymmetric transistor including a source with a halo implant. The source of the pass transistor is coupled to a common source line (CSL) that is shared among NVM cells of a sector of NVM cells. The operation may be performed by applying a first signal to a word line (WLS) coupled to a gate of a memory transistor of the NVM cell and applying a second signal to a bit line (BL) coupled to a drain of the memory transistor of the NVM cell.Type: GrantFiled: March 23, 2016Date of Patent: March 7, 2017Assignee: CYPRESS SEMICONDUCTOR CORPORATIONInventors: Sungkwon Lee, Venkatraman Prabhakar
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Patent number: 9583197Abstract: A nonvolatile memory device includes memory cells stacked in a direction perpendicular to a substrate and further includes a first memory cell string connected between a selected bit line and a selected string selection line, a second memory cell string connected between the selected bit line and an unselected string selection line, and a third memory cell string connected to an unselected bit line. During a bit line setup section of a program operation, a ground voltage is provided to the selected bit line and a power supply voltage provided to the unselected string selection line is changed to the ground voltage.Type: GrantFiled: March 11, 2016Date of Patent: February 28, 2017Assignee: Samsung Electronics Co., Ltd.Inventor: Ji-Sang Lee