Integrated Circuit, Printed Circuit, Or Circuit Board Patents (Class 427/96.1)
  • Patent number: 7833427
    Abstract: Methods and devices for selective etching in a semiconductor process are shown. Chemical species generated in a reaction chamber provide both a selective etching function and concurrently form a protective coating on other regions. An electron beam provides activation to selective chemical species. In one example, reactive species are generated from a halogen and carbon containing gas source. Addition of other gasses to the system can provide functions such as controlling a chemistry in a protective layer during a processing operation.
    Type: Grant
    Filed: August 14, 2006
    Date of Patent: November 16, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Neal R. Rueger, Mark J. Williamson, Gurtej S. Sandhu
  • Patent number: 7829159
    Abstract: A method of forming an organosilicon oxide film by plasma CVD includes: (i) adjusting a temperature of a susceptor on which a substrate is placed to lower than 300° C.; (ii) introducing at least tetraethylorthosilicate (TEOS) and oxygen into a reactor in which the susceptor is disposed; (iii) applying high-frequency RF power and low-frequency RF power; and (iv) thereby depositing an organosilicon oxide film on the substrate.
    Type: Grant
    Filed: January 4, 2006
    Date of Patent: November 9, 2010
    Assignee: ASM Japan K.K.
    Inventor: Ryu Nakano
  • Patent number: 7824579
    Abstract: The present invention is directed to a thick film conductor composition comprised of (a) aluminum-containing powder; (b) one or more glass frit compositions; dispersed in (c) organic medium wherein at least one of said glass frit compositions has a softening point of less than 400° C.
    Type: Grant
    Filed: May 31, 2006
    Date of Patent: November 2, 2010
    Assignee: E. I. du Pont de Nemours and Company
    Inventors: Richard John Sheffield Young, Michael Rose, Julie Ann Raby
  • Patent number: 7820232
    Abstract: The present invention provides a process for forming a copper fine particle sintered product type of a fine-shaped electric conductor showing superior electroconductivity, which comprises steps of drawing a fine pattern with the use of a dispersion containing the copper fine particles having a surface oxide film layer, conducting a treatment for reducing the copper fine particles with the surface oxide film layer or copper oxide fine particles included in the pattern at a comparatively low temperature, and baking the resultant copper fine particles. Specifically, the process carries out the processes of; applying a dispersion containing the copper fine particles having the surface oxide film layer thereon or the copper oxide fine particles with an average particle diameter of 10 ?m or smaller onto a substrate; and then performing a series of the heat treatment steps of heating the particles in the coated layer at temperature of 350° C.
    Type: Grant
    Filed: May 13, 2004
    Date of Patent: October 26, 2010
    Assignee: Harima Chemicals, Inc.
    Inventors: Daisuke Itoh, Akihito Izumitani, Noriaki Hata, Yorishige Matsuba
  • Publication number: 20100255286
    Abstract: A method for manufacturing a resin substrate includes heating a resin sheet including fibers and a resin containing incompletely polymerized molecules to a temperature lower than a polymerization initiation temperature of the resin in order to soften the resin; applying a first pressure to the resin sheet to discharge air bubbles between the fibers outside the resin sheet; decreasing the pressure applied to the resin sheet from the first pressure to a second pressure lower than the first pressure; and heating the resin sheet to the polymerization initiation temperature of the resin or higher to polymerize the molecules of the resin and to discharge a gas generated by the polymerization outside the resin sheet.
    Type: Application
    Filed: March 26, 2010
    Publication date: October 7, 2010
    Applicant: Kyocera Corporation
    Inventors: Keisaku MATSUMOTO, Katsura Hayashi
  • Patent number: 7807073
    Abstract: A conductor composition being able to easily secure the conductivity at the same level as an Ag bulk at low temperature process, a mounting substrate utilizing the conductor composition and a mounting structure utilizing the conductor composition are provided. In a mounting structure, wherein one or more electrodes (11) of a mounting substrate (10) and one or more surface mounting components (20) are connected through a conductor composition (30), and one or more surface wirings (14) of the mounting substrate (10), one or more inner-layer wirings (13) and one or more via conductors (12) are formed with the conductor composition, the conductor composition contains conductive particles with electrical conductivity, and the conductive particles are composed of low crystallized Ag fillers with the crystal size of 10 ?m or less.
    Type: Grant
    Filed: May 17, 2007
    Date of Patent: October 5, 2010
    Assignee: DENSO CORPORATION
    Inventors: Masashi Totokawa, Yuji Ootani, Hirokazu Imai, Akira Shintai
  • Patent number: 7809460
    Abstract: A coating and developing apparatus comprises a washing section for washing the surface of a substrate after it has been subjected to a dipping exposure process in an exposing apparatus, and a first substrate carrying means adapted to transfer the substrate carried out from the exposing apparatus after the dipping exposure process to the washing section. The first substrate carrying means is controlled by a control means. Namely, the control means controls the first substrate carrying means such that the substrate can be washed in the washing section in a period of time prior to a time zone in which the size of liquid drops remaining on the substrate due to the dipping exposure process becomes smaller quite rapidly, based on a carrying-out ready signal for the substrate from the exposing apparatus, by using a relationship between the time elapsed from the end of the dipping exposure process and the size of liquid drops remaining on the substrate due to the dipping exposure process.
    Type: Grant
    Filed: December 8, 2006
    Date of Patent: October 5, 2010
    Assignee: Tokyo Electron Limited
    Inventors: Seiki Ishida, Taro Yamamoto
  • Patent number: 7799370
    Abstract: Provided is a method of manufacturing an electronic circuit. The method includes the steps of: forming a nucleus comprising thermo-expandable particles on a conductive layer provided on an insulating substrate; forming an insulating film on the conductive layer having the nucleus-formed thereon; forming an opening by heating the substrate to expand the thermo-expandable particles and form a cleavage in the insulating film; and forming another conductive layer comprising a conductive material on the opening and the insulating film such that the upper and lower conductive layers are electrically connected to each other via the conductive material through the insulating film. This allows formation of a through hole in an electric circuit with ease without photolithographic processes such as exposure, development, and etching.
    Type: Grant
    Filed: February 28, 2006
    Date of Patent: September 21, 2010
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hiroyuki Tokunaga, Osamu Kanome
  • Publication number: 20100231543
    Abstract: A display device with a touch sensor function includes: a first substrate; a second substrate which is disposed opposite the first substrate and has a touch surface at an opposite side of the first substrate; a display unit provided between the first and second substrates; display electrodes which are provided on both a surface of the first substrate facing the display unit and a surface of the second substrate facing the display unit and which control display of the display unit; and touch electrodes for detecting the touch position on the touch surface which are provided on both the surface of the first substrate facing the display unit and the surface of the second substrate facing the display unit and which come in contact with each other by a touch operation on the touch surface, the touch electrodes provided on at least one of both the surfaces being provided to protrude toward the display unit side, wherein each of the touch electrodes provided on the one surface has a contact surface, which is a curve
    Type: Application
    Filed: March 4, 2010
    Publication date: September 16, 2010
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Seigo Momose
  • Patent number: 7789285
    Abstract: In one embodiment, a method is provided. The method comprises filling a microvia formed in a bond pad with solder paste comprising solder balls of the first size; and coating the bond pad with solder paste comprising solder balls of the second size, wherein the second size is greater than the first size.
    Type: Grant
    Filed: October 17, 2007
    Date of Patent: September 7, 2010
    Assignee: Intel Corporation
    Inventors: Cheng Siew Tay, Pek Chew Tan, Swee Kian Cheng, Eng Hooi Yap
  • Patent number: 7790269
    Abstract: To produce an ultra-thin copper foil with a carrier foil that microscopic crystal grains can be deposited without being affected by the surface roughness of a carrier foil, etching can be performed until an ultra-fine width such that line/space is 15 mum or less, and the microscopic line and a wiring board have large peel strength even after line of 15 mum is etched. An ultra-thin copper foil wherein a carrier foil, a peeling layer, an ultra-thin copper foil are laminated in this order, the ultra-thin copper foil (before roughening treatment is performed) is an electrolytic copper foil that surface roughness of 2.5 mum as ten point height of roughness profile, and the minimum distance between peaks of salients of a based material is 5 mum or more. Moreover, the surface of the ultra-thin copper foil is performed roughening treatment.
    Type: Grant
    Filed: September 5, 2008
    Date of Patent: September 7, 2010
    Assignee: The Furukawa Electric Co., Ltd.
    Inventors: Akitoshi Suzuki, Shin Fukuda
  • Publication number: 20100215839
    Abstract: A method for making an integrated circuit is disclosed comprising depositing alternating regions of electrically conductive material and hybrid organic inorganic dielectric material on a substrate, wherein an area of dielectric material is formed by hydrolyzing a plurality of precursors to form a hybrid organic inorganic material comprised of a silicon oxide backbone and having an organic substituent bound to the backbone, and depositing the hybrid organic inorganic material on a substrate, removing the hybrid organic-inorganic material in selected areas, and depositing an electrically conductive material in the selected areas, wherein one of the precursors is a compound of the general formula R1R2R3SiR4, wherein R1, R2, R3 are each bound to the Si and are independently an aryl group, a cross linkable group, or an alkyl group having from 1-14 carbons, and wherein R4 is selected from the group consisting of an alkoxy group, an acyloxy group, an —OH group or a halogen.
    Type: Application
    Filed: October 13, 2009
    Publication date: August 26, 2010
    Inventors: Juha T. Rantala, Jason S. Reid, T. Teemu Tormanen, Nungavram Viswanathan
  • Publication number: 20100215843
    Abstract: An electric circuit is applied to an object having a curved surface. The curved surface of the object is divided into sections, and the circuit is applied one section at a time. The circuit is formed between layers of dielectric material. The dielectric is applied by a computer-controlled device, which controls the position of a spray head and the rotation of the object, such that the spray head is held substantially perpendicular to the surface of the object at all times, and such that a controlled thickness of dielectric material can be deposited. The fine-featured circuits formed by the invention are rugged, and can be used on objects intended to be exposed to harsh environments.
    Type: Application
    Filed: April 29, 2010
    Publication date: August 26, 2010
    Applicant: MAX LEVY AUTOGRAPH, INC.
    Inventors: Donald C. Sedberry, Derek S. Rollins, David S. Metzger
  • Publication number: 20100206618
    Abstract: The present invention relates to a coreless substrate and a method for making the same. The method for making the coreless substrate includes: (a) providing a carrier and a first conductive layer, wherein the carrier has a first surface and a second surface, and the first conductive layer is disposed on the first surface of the carrier; (b) forming a first embedded circuit on the first conductive layer; (c) forming a first dielectric layer so as to cover the first embedded circuit; (d) removing the carrier; (e) removing part of the first conductive layer so as to form at least one first pad; and (f) forming a first solder mask so as to cover the first embedded circuit and the first dielectric layer and to expose the first pad. Therefore, the coreless substrate of the present invention has high density of layout and involves low manufacturing cost.
    Type: Application
    Filed: January 21, 2010
    Publication date: August 19, 2010
    Inventors: Chien-Hao Wang, Ming-Chiang Lee
  • Patent number: 7775417
    Abstract: A method of producing a conductive circuit board including imparting tackiness through the use of a tackiness-imparting compound to the surface of the conductive circuit on a printed wiring board, attaching a solder powder to the tacky area and then heating the printed wiring board to melt the solder to form a solder circuit. The characteristic feature of this method is that the tackiness-imparted printed wiring board is kept in a liquid, etc at not more than 10° C. before attaching the solder powder.
    Type: Grant
    Filed: December 17, 2007
    Date of Patent: August 17, 2010
    Assignee: Showda Denko K.K.
    Inventors: Takashi Shoji, Takekazu Sakai
  • Patent number: 7773365
    Abstract: One embodiment of a dielectric material may include a metal containing cation and a polyatomic anion.
    Type: Grant
    Filed: April 30, 2004
    Date of Patent: August 10, 2010
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Gregory S. Herman, Peter Mardilovich, Douglas Keszler, Jeremy Anderson
  • Patent number: 7771778
    Abstract: This invention relates to a fabricating method of a plastic substrate adapted to improve the stability of a display device fabrication process. The fabrication process utilizes the plastic substrate, which is inexpensive and easy to obtain. A fabricating method according to an embodiment of the present invention includes providing a plastic substrate; spreading an organic film on the plastic substrate; and applying heat to the plastic substrate over which the organic film is spread to conduct heat to the plastic substrate and to harden the organic film at the same time.
    Type: Grant
    Filed: December 20, 2006
    Date of Patent: August 10, 2010
    Assignee: LG Display Co., Ltd.
    Inventors: Kyoung Mook Lee, Sung Hwan Kim
  • Patent number: 7771623
    Abstract: The present invention is directed to a thick film conductor composition comprised of (a) aluminum-containing powder; (b) at least one glass frit composition; dispersed in (c) organic medium wherein said glass frit composition upon firing undergoes a recrystallization process and liberates both a glass and a crystalline phase and wherein said glass phase of said recrystallization process comprises a glass that has a lower softening point than the original softening point of said glass frit composition.
    Type: Grant
    Filed: May 31, 2006
    Date of Patent: August 10, 2010
    Assignee: E.I. du Pont de Nemours and Company Dupont (UK) Limited
    Inventors: Richard John Sheffield Young, Michael Rose, Julie Ann Raby, Kenneth Warren Hang
  • Patent number: 7765692
    Abstract: A solder resist comprising a thermosetting resin is printed on a surface of an insulating board (7) having a conductor circuit (6). The solder resist is then heat-cured to form an insulating film (1) having a low thermal expansion coefficient. A laser beam (2) is then applied to the portion of the insulating film in which an opening is to be formed, to burn off the same portion for forming an opening (10), whereby the conductor circuit (6) is exposed. This opening may be formed as a hole for conduction by forming a metal plating film on an inner surface thereof. It is preferable that an external connecting pad be formed so as to cover the opening. The film of coating of a metal is formed by using an electric plating lead, which is preferably cut off by a laser beam after the electric plating has finished.
    Type: Grant
    Filed: September 25, 2008
    Date of Patent: August 3, 2010
    Assignee: Ibiden Co., Ltd.
    Inventors: Masaru Takada, Hiroyuki Kobayashi, Kenji Chihara, Hisashi Minoura, Kiyotaka Tsukada, Mitsuhiro Kondo
  • Patent number: 7767254
    Abstract: In a paste for a solar cell light-receiving surface electrode including silver particles, glass frit, resin binder, and thinner, silver particles with a specific surface of 0.20-0.60 m2/g are used as the silver particles. The silver particles are preferably included at 80 mass % or more to the total amount of silver particles being included in the paste.
    Type: Grant
    Filed: August 26, 2009
    Date of Patent: August 3, 2010
    Assignee: E. I. du Pont de Nemours and Company
    Inventors: Takuya Konno, Takashi Kitagaki, Hiroki Kojo
  • Publication number: 20100163630
    Abstract: An antenna built-in module which incorporates an antenna, is thin and excellent in antenna characteristics, a card type information device and a method for manufacturing the same are provided. A wiring board (110) which has a wiring pattern (120) and in which an electronic component is mounted on at least one surface thereof, a magnetic substance (160) embedded in the other surface of the wiring board (110), an antenna pattern (170) provided on the magnetic substance (160), the wiring pattern (120) of the wiring board (110) and the antenna terminal electrode of the antenna pattern (170) are connected by a conductive via (200).
    Type: Application
    Filed: November 8, 2006
    Publication date: July 1, 2010
    Applicant: Matsushita Electric Industrial Co., Ltd
    Inventors: Shozo Ochi, Norihito Tsukahara, Yutaka Nakamura, Hirohisa Tanaka
  • Publication number: 20100164890
    Abstract: A flexible input device having a bendability and an electrode that may be formed using a printing process is provided. The input device comprises a flexible and transparent substrate and a printed electrode on the substrate.
    Type: Application
    Filed: December 22, 2009
    Publication date: July 1, 2010
    Inventors: Kyubok Lee, Jaeyoung Lee, Jinsup Kim, Sehwan Choi
  • Patent number: 7743493
    Abstract: A photo-resist of a dry film patterned to form opening portions and non-opening portions is provided on a release film. An electrically conductive paste is applied by a doctor blade and thereafter is dried. Then, the release film of the dry film is removed and thereafter the dry film is adhered to a ceramic green sheet. The photo-resist is removed from the ceramic green sheet to form an electrically conductive film on the ceramic green sheet. The ceramic electronic component is manufactured by sintering the ceramic green sheet having the electrically conductive film formed.
    Type: Grant
    Filed: September 22, 2005
    Date of Patent: June 29, 2010
    Assignee: Nihon University
    Inventor: Fumio Uchikoba
  • Patent number: 7744946
    Abstract: The present invention relates to organic siloxane resins and insulating films using the same. The insulating films are manufactured by using organic siloxane resins, wherein organic siloxane resins are hydrolysis-condensation polymers of silane compounds comprising one or more kinds of hydrosilane compounds. They have superior mechanical properties and a low electric property, and therefore, are properly usable for highly integrated semiconductor devices.
    Type: Grant
    Filed: April 16, 2004
    Date of Patent: June 29, 2010
    Assignee: LG Chem, Ltd.
    Inventors: Bum-gyu Choi, Min-jin Ko, Byung-ro Ko, Myung-sun Moon, Jung-won Kang, Hye-yeong Nam, Gwi-gwon Kang
  • Publication number: 20100155115
    Abstract: Methods of forming a microelectronic structure are described. Those methods include doping a lead free solder material with nickel, wherein the nickel comprises up to about 0.2 percent by weight of the solder material, and then applying the solder material to a substrate comprising a copper pad.
    Type: Application
    Filed: December 23, 2008
    Publication date: June 24, 2010
    Inventors: Mengzhi Pang, Charan Gurumurthy
  • Patent number: 7736545
    Abstract: An electrode paste for a solar cell comprising electrically conductive particles, lead-free glass frit, a resin binder and zinc oxide particles, wherein zinc oxide particles having a specific surface area of 6 m2/g or less are contained at 10% by weight or more based on the total amount of zinc oxide.
    Type: Grant
    Filed: January 19, 2009
    Date of Patent: June 15, 2010
    Assignee: E.I. du Pont de Nemours and Company
    Inventor: Takuya Konno
  • Patent number: 7731868
    Abstract: The present invention is directed to a thick film conductive composition comprising: a) electrically conductive silver powder; b) ZnO powder; c) lead-free glass frits wherein based on total glass frits: Bi2O3: >5 mol %, B2O3: <15 mol %, BaO: <5 mol %, SrO: <5 mol %, Al2O3: <5 mol %; and d) organic medium, wherein (the content of ZnO/the content of the silver powder)×100 is more than 2.5.
    Type: Grant
    Filed: April 12, 2007
    Date of Patent: June 8, 2010
    Assignee: E.I. du Pont de Nemours and Company
    Inventor: Takuya Konno
  • Patent number: 7727424
    Abstract: Disclosed is an electrically conducting paste comprising a silver powder, a glass frit, a resin binder and a sintering inhibitor. The paste is used in the manufacture of solar cell electrodes by applying the electrically conducting paste to a substrate and then firing of the coated substrate.
    Type: Grant
    Filed: December 15, 2006
    Date of Patent: June 1, 2010
    Assignee: E.I. du Pont de Nemours and Company
    Inventor: Takuya Konno
  • Patent number: 7722920
    Abstract: Described are methods of making an electronic device, such as an RFID tag, including fabricating an antenna by depositing an electrically conductive polymer onto a substrate. The electrically conductive polymer is electrically connected to an electronic component, such as an IC chip or a diode. The electronic component may be placed on the substrate before or after the electrically conductive polymer is deposited. Once deposited, the electrically conductive polymer is cured. The electrically conductive polymer may be deposited in a number of ways, such using a mask having a desired pattern and applying the electrically conductive polymer to the mask, by screen printing the electrically conductive polymer or by printing the electrically conductive polymer using ink jet printing techniques.
    Type: Grant
    Filed: May 9, 2006
    Date of Patent: May 25, 2010
    Assignee: University of Pittsburgh-Of the Commonwealth System of Higher Education
    Inventors: Marlin H. Mickle, James T. Cain, Michael R. Lovell, Jungfeng Mei
  • Publication number: 20100123675
    Abstract: A touch sensor includes a substrate having a first surface and a second surface opposite the first surface, and a transparent conductive layer disposed on the second surface of the substrate. The transparent conductive layer is disposed in a pattern so that the transparent conductive layer includes a plurality of discrete conductive pads, with the pads being conductively connected to at least one connecting region of the substrate via respective conductive traces. The pads are associated with respective buttons of a display device disposed at the substrate, such that the user may touch or approach the substrate and pads at selected areas in response to the displayed buttons as viewed by the user through the pads and substrate.
    Type: Application
    Filed: November 17, 2009
    Publication date: May 20, 2010
    Applicant: OPTERA, INC.
    Inventor: Scott C. Ippel
  • Patent number: 7718216
    Abstract: A method for low temperature bumping is disclosed. A resin capable of being cross-linked by free-radical or cationic polymerization at low temperature is provided. Electrically conductive particles are then added to the resin to form a mixture. The mixture is then activated by heat or exposure to light to polymerize the mixture. In an alternative embodiment, a vinyl ether resin is used, to which electrically conductive particles are added. The mixture is polymerized by exposure to light.
    Type: Grant
    Filed: March 12, 2007
    Date of Patent: May 18, 2010
    Assignee: Intel Corporation
    Inventors: Terry Lee Sterrett, Tian-An Chen, Saikumar Jayaraman
  • Patent number: 7704416
    Abstract: A conductor paste for a ceramic substrate contains a) a conductive metal powder comprising a silver powder and a palladium powder; b) a glass powder; and c) an organic solvent, wherein the conductive metal powder has an average particle diameter of not more than 1.2 ?m, and the glass powder is a Bi2O3—SiO2—B2O3 type glass powder, and the content of the glass powder is in a range of from 1 to 6 wt % based on the weight of the paste.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: April 27, 2010
    Assignee: E.I. du Pont de Nemours and Company
    Inventors: Akira Inaba, Naoto Nakajima
  • Patent number: 7704548
    Abstract: A method for manufacturing a wiring board which can simplify a manufacturing step. In a preparation step, a core board and an electronic component are prepared. In an insulating layer formation and fixing step, after accommodating the electronic component in an accommodation hole, a lowermost resin insulating layer is formed, and a gap between the electronic component and the core board is filled with a part of the lowermost resin insulating layer so as to fix the electronic component to the core board. In an opening portion formation step, a portion of the lowermost resin insulating layer located directly above the gap between the electronic component and the core board is removed so as to form an opening portion exposing a part of a core board main surface side conductor and a component main surface side electrode.
    Type: Grant
    Filed: April 25, 2007
    Date of Patent: April 27, 2010
    Assignee: NGK Spark Plug Co., Ltd.
    Inventors: Tadahiko Kawabe, Masao Kuroda, Yasuhiro Sugimoto, Hajime Saiki, Shinji Yuri, Makoto Origuchi
  • Patent number: 7691433
    Abstract: The invention relates to a method for a structured application of molecules on a strip conductor and to a molecular memory matrix. The inventive method makes it possible, for the first time, to economically and simply apply any number of molecular memory elements on the strip conductor in a structured and targeted way, thereby making available, also for the first time, a memory matrix at a molecular level.
    Type: Grant
    Filed: November 30, 2005
    Date of Patent: April 6, 2010
    Assignee: Forschungszentrum Julich GmbH
    Inventors: Stephan Kronholz, Silvia Karthäuser
  • Patent number: 7682652
    Abstract: The present invention relates to a method of surface treatment, a method for forming circuit lines, a printed circuit board formed thereby, and an apparatus for forming circuit lines on a substrate, wherein fine circuit lines are formed simply, rapidly, and economically. The method for forming circuit lines of the present invention comprises: (a) selectively applying a surface treatment solution which includes an alkali metal compound on a base film in accordance with circuit patterns by a discharging method; (b) applying a conductive ink which includes metal nanoparticles in accordance with the surface-treated circuit pattern; and (c) curing the base film on which the conductive ink is applied under a reduction atmosphere lines.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: March 23, 2010
    Assignee: Samsung Electro-Mechanics Co., Ltd
    Inventors: Yoon-Ah Baik, Hyun-Chul Jung
  • Patent number: 7678411
    Abstract: The invention provides a method of forming a wiring pattern in which a conductive material layer is formed in a pattern formation region having a first region, which is bordered by a bank pattern and has a first width, and a second region, which touches the first region and has a second width smaller than the first width, on a substrate, by discharging a droplet of a conductive material in a liquid phase using a droplet discharge device. The method includes forming the conductive material layer to cover the first region and the second region, by discharging the droplet having a diameter smaller than the first width and greater than the second width toward the first region. In this case, the droplet is discharged such that the droplet lands at a position that faces a boundary line between the first region and the second region.
    Type: Grant
    Filed: August 19, 2005
    Date of Patent: March 16, 2010
    Assignee: Seiko Epson Corporation
    Inventors: Toshimitsu Hirai, Shinri Sakai
  • Publication number: 20100062148
    Abstract: An electrically responsive composite material is disclosed, along with a method of producing an electrically responsive composite material, a transducer having a substrate for supporting a flowable polymer liquid and a method of fabricating a transducer. The electrically responsive composite material produced is configurable for application in a transducer. The method includes the steps of receiving the flowable polymer liquid and introducing electrically conductive acicular particles (1501, 1502) to facilitate the conduction of electricity by quantum tunneling. Dielectric particles (1505, 1506) are added of a size relative to the acicular particles such that a plurality of these dielectric particles are dispersed between adjacent acicular particles.
    Type: Application
    Filed: August 26, 2009
    Publication date: March 11, 2010
    Applicant: PERATECH LIMITED
    Inventors: David Lussey, David Bloor, Paul Jonathan Laughlin, Adam Graham, Cyril Hilsum
  • Patent number: 7674403
    Abstract: A composition for forming an electrode including a conductive composite of a first material coated with a metal that has a higher electrical conductivity, wherein the first material is at least one selected from the group consisting essentially of nickel, carbon, and copper.
    Type: Grant
    Filed: July 26, 2006
    Date of Patent: March 9, 2010
    Assignee: Samsung SDI Co., Ltd.
    Inventor: Chul-Hong Kim
  • Publication number: 20100051329
    Abstract: Disclosed are a printed circuit board and a method of manufacturing the same. The method in accordance with an embodiment of the present invention includes: forming an electroless plated layer on an insulation layer; and forming a circuit pattern by applying conductive ink on the electroless plated layer through an inkjet method.
    Type: Application
    Filed: April 23, 2009
    Publication date: March 4, 2010
    Inventors: Tae-Hoon KIM, Dong-Hoon Kim, Young-Il Lee, Sang-Gyun Lee, Byung-Ho Jun, Da-Mi Shim
  • Publication number: 20100044087
    Abstract: The invention relates to a prepreg, obtained by impregnating a base material with an epoxy resin composition containing an epoxy resin(A), a curing agent (B), an accelerator (C), a phenoxy resin (D), and an inorganic filler (E) and semi-hardening the impregnated material, wherein the inorganic filler (E) has an average particle diameter of 3 ?m or less. When a circuit with a narrow wire distance is formed on a surface of a insulator substrate composed of such a prepreg by using a method of forming the circuit by plating process, an amount of the plating remaining on the insulator substrate surface at the circuit contour periphery can be reduced. As a result, it leads to stabilization of inter-circuit insulation resistance and increase in a yield during production of printed wiring boards.
    Type: Application
    Filed: January 25, 2007
    Publication date: February 25, 2010
    Applicant: PANASONIC ELECTRIC WORKS CO., LTD.
    Inventors: Yasuo Fukuhara, Tomoaki Watanabe, Mao Yamaguchi, Yuki Kitai, Hiroaki Fujiwara
  • Publication number: 20100044072
    Abstract: The embodiments disclosed herein relate to the fabrication of complex two-dimensional conductive silicide nanostructures, and methods of fabricating the nanostructures. In an embodiment, a conductive silicide includes a plurality of connected and spaced-apart nanobeams linked together at an about 90-degree angle, the plurality of nanobeams forming a two-dimensional nanostructure having a mesh-like appearance. In an embodiment, a method of fabricating a two-dimensional conductive silicide includes performing chemical vapor deposition, wherein one or more gas or liquid precursor materials carried by a carrier gas stream react to form a nanostructure having a mesh-like appearance and including a plurality of connected and spaced-apart nanobeams linked together at an about 90-degree angle.
    Type: Application
    Filed: August 25, 2009
    Publication date: February 25, 2010
    Inventors: Dunwei Wang, Sa Zhou
  • Publication number: 20100038119
    Abstract: Systems and methods include depositing one or more materials on a voltage switchable dielectric material. In certain aspects, a voltage switchable dielectric material is disposed on a conductive backplane. In some embodiments, a voltage switchable dielectric material includes regions having different characteristic voltages associated with deposition thereon. Some embodiments include masking, and may include the use of a removable contact mask. Certain embodiments include electrografting. Some embodiments include an intermediate layer disposed between two layers.
    Type: Application
    Filed: October 29, 2009
    Publication date: February 18, 2010
    Inventor: Lex Kosowsky
  • Patent number: 7651723
    Abstract: A process chamber is provided which includes a gate configured to align barriers with an opening of the gate and an opening of the process chamber such that the two openings are either sealed or provide an air passage to the chamber. A method is provided and includes sealing an opening of a chamber with a gate latch and exposing a topography to a first set of process steps, opening the gate latch such that an air passage is provided to the process chamber, and exposing the topography to a second set of process steps without allowing liquids within the chamber to flow through the air passage. A substrate holder comprising a clamping jaw with a lever and a support member coupled to the lever is also contemplated herein. A process chamber with a reservoir arranged above a substrate holder is also provided herein.
    Type: Grant
    Filed: January 10, 2005
    Date of Patent: January 26, 2010
    Assignee: Lam Research Corporation
    Inventors: Igor C. Ivanov, Weiguo Zhang
  • Publication number: 20100014146
    Abstract: Methods and devices used for the encapsulation of MEMS devices, such as an interferometric modulator, are disclosed. Encapsulation is provided to MEMS devices to protect the devices from such environmental hazards as moisture and mechanical shock. In addition to the encapsulation layer providing protection from environmental hazards, the encapsulation layer is additionally planarized so as to function as a substrate for additional circuit elements formed above the encapsulation layer.
    Type: Application
    Filed: July 17, 2008
    Publication date: January 21, 2010
    Applicant: QUALCOMM MEMS Technologies, Inc.
    Inventor: Je-Hsiung Lan
  • Patent number: 7648730
    Abstract: In a paste for a solar cell light-receiving surface electrode including silver particles, glass frit, resin binder, and thinner, silver particles with a specific surface of 0.20-0.60 m2/g are used as the silver particles. The silver particles are preferably included at 80 mass % or more to the total amount of silver particles being included in the paste.
    Type: Grant
    Filed: August 1, 2006
    Date of Patent: January 19, 2010
    Assignee: E.I. du Pont de Nemours and Company
    Inventors: Takuya Konno, Takashi Kitagaki, Hiroki Kojo
  • Publication number: 20100009070
    Abstract: A method for forming a solder layer on the surface of a conductive circuit on a printed-wiring board includes discharging slurry containing solder powder onto the surface and heating the substrate. The slurry is discharged by dint of the pressure in a tank for the slurry. In a discharging device to be used in the method, the tank for storing the slurry is provided with a discharge pipe (2) for the slurry and a delivery pipe (1) for gas or solvent to be used for adjusting the pressure in the tank. In this device, one common pipe may be used both for discharging the slurry from the tank and delivering the slurry to the tank and one common pipe may be used for both delivering gas into the tank and sucking the gas from the tank.
    Type: Application
    Filed: October 12, 2007
    Publication date: January 14, 2010
    Applicant: SHOWA DENKO K.K.
    Inventors: Takashi Shoji, Takekazu Sakai
  • Patent number: 7641934
    Abstract: There are provided a process for the production of an entry sheet for drilling, comprising preparing a water-soluble resin composition solution by using a mixed solvent containing water and isopropyl alcohol in a specific ratio as a solvent of a water-soluble resin composition, then applying the solution to a sheet-like base material and drying the resultant base material to form a resin layer on the base material, and a method of drilling a printed wiring board material using the above entry sheet. According to the present invention, the problems of remaining bubbles in the resin layer and a decrease in surface flatness and smoothness due to the occurrence of a ridge, which are caused because the melting point of the water-soluble resin is lower than the boiling point of water, are overcome, and an entry sheet for drilling excellent in hole position accuracy is provided.
    Type: Grant
    Filed: May 29, 2007
    Date of Patent: January 5, 2010
    Assignee: Mitsubishi Gas Chemical Company, Inc.
    Inventors: Reiki Akita, Shinya Komatsu, Takuya Hasaki
  • Patent number: 7642325
    Abstract: A non-sticky water-based coating material in the form of a film applied to the face of a circuit board that is loaded with electronic parts; which comes into contact with the outside environment. The coating material can be formed into the film at room temperature without using a coalescence, does not contain a solvent and forms a membrane having flexibility, low Young's modulus, favorable adhesive properties, moisture resistance and insulating properties. Specifically, the non-sticky water-based conformal coating material includes a resin wherein a flexible acrylic resin having glass transition temperature of at most 0° C. is the main chain and a vinyl polymer having a glass transition temperature of at least 20° C. is grafted to the flexible acrylic resin; the content of the vinyl polymer being 10 to 70% by weight based on the flexible acrylic resin.
    Type: Grant
    Filed: April 7, 2006
    Date of Patent: January 5, 2010
    Assignee: Tohpe Corporation
    Inventors: Masashi Hashimoto, Hideo Maeda
  • Patent number: 7638161
    Abstract: A method and apparatus for controlling dopant concentration during borophosphosilicate glass film deposition on a semiconductor wafer to reduce consumption of nitride on the semiconductor wafer. In one embodiment of the invention, the method starts by placing a substrate having a nitride layer in a reaction chamber and providing a silicon source, an oxygen source and a boron source into the reaction chamber while delaying providing a phosphorous source into the reaction chamber to form a borosilicate glass layer over the nitride layer. The method continues by providing the silicon, oxygen, boron and phosphorous sources into the reaction chamber to form a borophosphosilicate film over the borosilicate glass layer.
    Type: Grant
    Filed: July 20, 2001
    Date of Patent: December 29, 2009
    Assignee: Applied Materials, Inc.
    Inventors: Kevin Mukai, Shankar Chandran
  • Patent number: 7632428
    Abstract: A method of synthesizing doped semiconductor nanocrystals.
    Type: Grant
    Filed: April 25, 2006
    Date of Patent: December 15, 2009
    Assignee: The Board of Trustees of the University of Arkansas
    Inventors: Xiaogang Peng, Narayan Pradhan