Integrated Circuit, Printed Circuit, Or Circuit Board Patents (Class 427/96.1)
  • Publication number: 20080259106
    Abstract: A method for manufacturing a patterned layer (106) on a substrate (100) includes the following steps: providing a substrate having a plurality of banks (102) formed thereon, the substrate and the banks cooperatively defining a plurality of accommodating spaces (104), wherein each of the accommodating spaces has a first edge (110) and a second edge (112) parallel to the first edge, a distance between the first edge and the second edge is b; the first nozzle (302) moving along a first path (306), and the first path is parallel to the first edge, a distance between the first path and the first edge is a; the first nozzle jetting ink into the accommodating space; the second nozzle (304) moving along a second path (310), a distance between the first path and the second path is c, and the distance c satisfies one of the two equations: 0<c<b?a, and 0<c<a.
    Type: Application
    Filed: December 26, 2007
    Publication date: October 23, 2008
    Applicant: ICF TECHNOLOGY LIMITED
    Inventors: CHING-YU CHOU, YU-NING WANG, JIH-JENN HUANG, YI-MING LIAO
  • Publication number: 20080257201
    Abstract: A continuous film of desired electrical characteristics is obtained by successively printing and annealing two or more dispersions of prefabricated nanoparticles.
    Type: Application
    Filed: April 17, 2008
    Publication date: October 23, 2008
    Inventors: James Harris, Nigel Pickett
  • Patent number: 7429401
    Abstract: The process of this invention involves first adsorbing a catalyst on the surface of a specimen by immersion in a catalyst-containing solution, followed by electrolytic deposition in a second solution that need not contain catalyst. This two-step superconformal process produces a seam-free and void-free metal microelectronic conductor.
    Type: Grant
    Filed: May 23, 2003
    Date of Patent: September 30, 2008
    Assignee: The United States of America as represented by the Secretary of Commerce, the National Insitiute of Standards & Technology
    Inventors: Daniel Josell, Thomas P. Moffat, Daniel Wheeler
  • Publication number: 20080230259
    Abstract: A method and structure are provided for implementing flexible circuits of various electronic packages and circuit applications. A meshed reference plane includes a variable mesh pitch arranged for control of mechanical flexibility. A dielectric core separates a signal layer from the variable pitch meshed reference plane. An electrically conductive coating covers the surface of the variable pitch meshed reference plane yielding substantially constant signal impedance for the signal layer.
    Type: Application
    Filed: March 22, 2007
    Publication date: September 25, 2008
    Inventors: Roger Allen Booth Jr., Matthew Stephen Doyle
  • Publication number: 20080230357
    Abstract: Provided herein are new methods for the fabrication of gold (Au) alloys and films containing metal or semimetal oxides such as oxides of vanadium (V), for example, Au—V2O5 for use in electrical, mechanical, and microelectromechanical systems (“MEMS”). An example embodiment provides a thin film of an alloy comprising Au—V2O5 in a MEMS for a contact switch. Also described herein are gold-metal oxide thin films for use in, e.g. wear-resistant MEMS. Measurements of contact force and electrical contact resistance between pairs of Au or Au—V films show that increased hardness and resistivity in the alloy films results in higher contact resistance and less adhesion than in pure Au.
    Type: Application
    Filed: March 21, 2008
    Publication date: September 25, 2008
    Applicant: LEHIGH UNIVERSITY
    Inventors: Richard P. Vinci, Walter L. Brown, Thirumalesh Bannuru
  • Patent number: 7427423
    Abstract: A method of fabricating solder assemblies for forming solder connections that include a dielectric base having a non solder-wettable surface, a plurality of solder-wettable pads exposed to said surface, and an electrically conductive potential plane element having a non solder-wettable surface overlying the surface of the base in proximity to the pads but spaced from said pads. The non-wettable surface of the potential plane element may include a metal such as nickel or a metal oxide. The potential plane element thus performs the functions of a solder mask to prevent solder from forming short circuits between adjacent pads, and may also act as a ground plane, power plane or shielding element.
    Type: Grant
    Filed: August 30, 2001
    Date of Patent: September 23, 2008
    Assignee: Tessera, Inc.
    Inventors: Masud Beroz, Belgacem Haba
  • Patent number: 7425350
    Abstract: A method for making a Si-containing material comprises transporting a pyrolyzed Si-precursor to a substrate and polymerizing the pyrolyzed Si-precursor on the substrate to form a Si-containing film. Polymerization of the pyrolyzed Si-precursor may be carried out in the presence of a porogen to thereby form a porogen-containing Si-containing film. The porogen may be removed from the porogen-containing Si-containing film to thereby form a porous Si-containing film. Preferred porous Si-containing films have low dielectric constants and thus are suitable for various low-k applications such as in microelectronics and microelectromechanical systems.
    Type: Grant
    Filed: April 29, 2005
    Date of Patent: September 16, 2008
    Assignee: ASM Japan K.K.
    Inventor: Michael A. Todd
  • Publication number: 20080203972
    Abstract: A method and apparatus for a unitary battery and charging circuit that includes a first substrate having integrated-circuit battery-charging circuitry thereon, and a cathode material, an anode material, and an electrolyte layer separating the cathode material from the anode material deposited on the substrate to form a battery, wherein the charging circuit is connected to the battery and encapsulated to form a surface-mount unitary package. Also, a power conversion system includes a variable charging source and an energy storage device. The power conversion circuit also includes a charging circuit coupled to the variable charging source and the energy storage device, the energy storage device being charged by the variable charging source. Further, the circuit includes an energy storage device isolation circuit configured to isolate the energy storage device from discharging when power from the variable charging source is below a predetermined threshold.
    Type: Application
    Filed: February 8, 2008
    Publication date: August 28, 2008
    Inventors: Jeffrey S. Sather, Roger L. Roisen, Jeffrey D. Mullin
  • Publication number: 20080202587
    Abstract: Disclosed are a system and method for supplying chemical during a semiconductor device fabrication process. The system includes a tank to store the chemical, a dispensing unit to hold the chemical, a refill line connected between the tank and the dispensing unit to supply the chemical from the tank to the chemical liquid dispensing unit, and a dispensing line connected between the chemical dispensing unit and a semiconductor substrate to supply the chemical from the chemical dispensing unit to the semiconductor substrate.
    Type: Application
    Filed: April 17, 2008
    Publication date: August 28, 2008
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong-kil KANG, Dae-yong CHOI
  • Publication number: 20080206516
    Abstract: A surface mount circuit board includes: an insulating substrate having through holes each extending from front to rear surfaces of the insulating substrate; high thermal conductive members each filing a different one of the though holes; lands each disposed to cover an end surface of a different one of the high thermal conductive members and also cover part of the front surface around the peripheral edge of the corresponding through hole; and heat receiving members each disposed to cover an end surface of a different one of the high thermal conductive members and also cover part of the rear surface around the peripheral edge of the corresponding through hole. Each land may be made of solder cream filled into and flashed out of the through hole. Alternatively to the high thermal conductive members, wire rods may be fitted into the respective through holes.
    Type: Application
    Filed: February 18, 2008
    Publication date: August 28, 2008
    Inventor: Yoshihiko Matsushima
  • Patent number: 7404981
    Abstract: A method is provided for printing electronic and opto-electronic circuits. The method comprises: (a) providing a substrate; (b) providing a film-forming precursor species; (c) forming a substantially uniform and continuous film of the film-forming precursor species on at least one side of the substrate, the film having a first electrical conductivity; and (d) altering portions of the film with at least one conductivity-altering species to form regions having a second electrical conductivity that is different than the first electrical conductivity, the regions thereby providing circuit elements. The method employs very simple and continuous processes, which make the time to produce a batch of circuits very short and leads to very inexpensive products, such as electronic memories (write once or rewriteable), electronically addressable displays, and generally any circuit for which organic electronics or opto-electronics are acceptable.
    Type: Grant
    Filed: April 21, 2003
    Date of Patent: July 29, 2008
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Xiao-An Zhang, R. Stanley Williams, Yong Chen
  • Patent number: 7399399
    Abstract: A method for manufacturing a semiconductor package is proposed. A circuit board with a circuit layer on at least one surface thereof is provided. The circuit board has at least one free area, and the circuit layer has a plurality of electrically connecting pads distributed on the periphery of the free area. A metal protecting layer is plated on the electrically connecting pads by non-plating line. The free area is removed, to form a cavity penetrating the circuit board. The present invention prevents burrs which may otherwise form on the periphery of a cavity, to increase the yield and throughput.
    Type: Grant
    Filed: September 18, 2006
    Date of Patent: July 15, 2008
    Assignee: Phoenix Precision Technology Corporation
    Inventors: E-Tung Chou, Che-Wei Hsu, Tzu-Sheng Tseng
  • Publication number: 20080160251
    Abstract: A MEMS (Microelectromechanical system) device is described. The device includes a first layer on a substrate, and a sacrificial layer on or over the first layer, the first sacrificial layer being configured to be removed in a removal procedure. The device also includes a second layer on or over the first sacrificial layer, where the second layer is spaced apart from the first layer, and a shorting element electrically connecting the first and second layers, where at least a portion of the shorting element is removable in the removal procedure.
    Type: Application
    Filed: December 29, 2006
    Publication date: July 3, 2008
    Inventor: William J. Cummings
  • Publication number: 20080145689
    Abstract: Provided is an adhesion assisting agent fitted metal foil, comprising an adhesion assisting agent layer having a thickness of 0.1 to 10 ?m on a metal whose surface has a ten-point average roughness Rz of 2.0 ?m or less, wherein the adhesion assisting agent layer is formed from an adhesion assisting agent composition comprising: (A) an epoxy resin selected from the group consisting of a novolak epoxy resin and an aralkyl epoxy resin; and (C) an epoxy resin curing agent.
    Type: Application
    Filed: November 10, 2005
    Publication date: June 19, 2008
    Inventors: Nobuyuki Ogawa, HItoshi Onozeki, Takahiro Tanabe, Kenji Takai, Norio Moriike, Shin Takanezawa, Takako (Formerly Watanabe) Ejiri, Toshihisa Kumakura
  • Publication number: 20080145568
    Abstract: Provided is a method of fabricating a wire grid polarizer. The method includes: forming a photocatalytic layer on a first substrate; forming a patterned resin layer having a plurality of parallel grooves; forming a wire grid by filling the grooves with a metal; and transferring the wire grid and the resin layer to a second substrate.
    Type: Application
    Filed: September 14, 2007
    Publication date: June 19, 2008
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Su-mi LEE, Chang-ho NOH
  • Publication number: 20080131589
    Abstract: To provide a method for forming an outer electrode capable of reducing a tact time when electrode paste is applied to end surfaces of electronic components a plurality of times. A paste tank 4 having a squeegee blade that is vertically slidable is disposed on a flat board 1 having an area being a plurality of times as large as that of a holding plate in a longitudinal direction of the flat board. A paste film is spread on the flat board by moving the flat board 1 by a length corresponding to the length of one holding plate while a predetermined gap is maintained between the squeegee blade and the flat board. The electrode paste is applied to first end surfaces of electronic components C held by the holding plate H by dipping the first end surfaces of the electronic components C in this paste film. The electrode paste is applied to the first end surfaces of the electronic components a plurality of times by repeating the spreading step and the applying step.
    Type: Application
    Filed: November 28, 2007
    Publication date: June 5, 2008
    Inventors: Katsunori OGATA, Kenichi AOKI
  • Patent number: 7381442
    Abstract: The invention relates to the production of nanoporous silica dielectric films and to semiconductor devices and integrated circuits comprising these improved films. The nanoporous films of the invention are prepared using silicon containing pre-polymers and are prepared by a process that allows crosslinking at lowered gel temperatures by means of a metal-ion-free onium or nucleophile catalyst.
    Type: Grant
    Filed: April 10, 2002
    Date of Patent: June 3, 2008
    Assignee: Honeywell International Inc.
    Inventors: Victor Y. Lu, Roger Y. Leung, Eric Deng, Songyuan Xie
  • Patent number: 7381441
    Abstract: The invention relates to the production of nanoporous silica dielectric films and to semiconductor devices and integrated circuits comprising these improved films. The nanoporous films of the invention are prepared using silicon containing pre-polymers and are prepared by a process that allows crosslinking at lowered gel temperatures by means of a metal-ion-free onium or nucleophile catalyst.
    Type: Grant
    Filed: April 10, 2002
    Date of Patent: June 3, 2008
    Assignee: Honeywell International Inc.
    Inventors: Roger Y. Leung, Eric Deng, Songyuan Xie, Victor Y. Lu
  • Publication number: 20080123307
    Abstract: A printed circuit board for mounting an electronic part includes a mounting surface configured so that the electronic part is mounted. A warpage correcting metal pattern is provided on a back surface of the printed circuit board opposite to the mounting surface.
    Type: Application
    Filed: August 20, 2007
    Publication date: May 29, 2008
    Applicant: FUJITSU LIMITED
    Inventor: Yukihiko OHASHI
  • Patent number: 7374977
    Abstract: It is an object of the present invention to improve the usability of a material, and to provide a display device which can be manufactured by simplifying the manufacturing process and a manufacturing technique thereof. It is also an object of the invention to provide a technique in which a pattern of a wiring or the like constituting these display devices can be formed to have a desired shape with favorable controllability. One feature of a droplet discharge device of the invention comprises: a discharge means for discharging a composition including a pattern forming material; and a shape means for shaping the shape of the composition before the composition is attached to a formation region, in which the shape means is provided between the discharge means and the formation region.
    Type: Grant
    Filed: December 13, 2004
    Date of Patent: May 20, 2008
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Keitaro Imai
  • Publication number: 20080095926
    Abstract: There is provided a circuit board including a substrate having a hole. Inside the hole, a metal wiring is formed. The wiring is made of a solder alloy having a melting point of 100 to 600° C., and the metal wiring includes a polycrystalline region of the solder alloy. The metal wiring of the present invention is superior in conductivity.
    Type: Application
    Filed: October 16, 2006
    Publication date: April 24, 2008
    Applicant: NAPRA CO., LTD.
    Inventors: Shigenobu Sekine, Yurina Sekine
  • Patent number: 7356905
    Abstract: Techniques for fabricating high frequency ultrasound transducers are provided herein. In one embodiment, the fabrication includes depositing a copperclad polyimide film, a layer of epoxy on the copperclad polyimide film, and a polyvinylidene fluoride film on the epoxy. The assembly of materials are then pressed to bond the polyvinylidene fluoride film to the copperclad polyimide film and to form an assembly. The polyvinylidene fluoride film being one surface and the copperclad polyimide film being the other surface. The area behind the copperclad polyimide film surface is filled with a second epoxy, and then cured to form an epoxy plug.
    Type: Grant
    Filed: May 24, 2005
    Date of Patent: April 15, 2008
    Assignee: Riverside Research Institute
    Inventors: Jeffrey A. Ketterling, Mary Lizzi, legal representative, Frederic L Lizzi
  • Patent number: 7350297
    Abstract: A first plating foundation layer is formed by printing on a front face of a sheet-shaped insulating substrate. By inserting a punch into the sheet-shaped insulating substrate having the first plating foundation layer, a through hole is formed while leaving a piece having the plating foundation layer in the portion where the punch is inserted. A second plating foundation layer is formed by printing on a rear face of the sheet-shaped insulating substrate. A first and second wiring layers composed of a metal plating layer are formed by performing electroless plating, and at the same time, a metal plating layer connecting between the first and second wiring layers is formed in the through hole using the plating foundation layer on the piece.
    Type: Grant
    Filed: February 17, 2006
    Date of Patent: April 1, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Naoko Yamaguchi, Hideo Aoki
  • Patent number: 7351357
    Abstract: Additives to organic conducting polymers are described which enhance adhesion and resolution of printed films while retaining adequate electrical conductivity. The conductive polymer films are useful in printing conductive portions of thin film transistors such as sources and drains. Additives include surfactants, second macromolecules, plasticizers, and excess sulfonic acids.
    Type: Grant
    Filed: February 26, 2003
    Date of Patent: April 1, 2008
    Assignee: E.I. du Pont de Nemours and Company
    Inventors: Graciela Beatriz Blanchet-Fincher, Feng Gao
  • Publication number: 20080075836
    Abstract: The present invention relates to a method to fabricate a flip chip substrate structure, which comprises: providing a carrier; forming a patterned resist layer on the surface of the carrier; forming sequentially a first metal layer, an etching-stop layer, and a second metal layer; removing the resist layer, forming a patterned first solder mask, and then forming at least one first circuit build up structure thereon; forming additionally a patterned second solder mask on the circuit build up structure; respectively removing the carrier, the first metal layer, and the etching-stop layer; and forming solder bumps on both sides of the circuit build up structure. The method increases integration and achieves the purpose of miniaturization. The method solves the problem of circuit layer multiplicity and process complexity.
    Type: Application
    Filed: September 27, 2006
    Publication date: March 27, 2008
    Applicant: Phoenix Precision Technology Corporation
    Inventors: Bo-Wei Chen, Hsien-Shou Wang, Shih-Ping Hsu
  • Patent number: 7338689
    Abstract: Disclosed herein is a composition for forming a low dielectric thin film, which includes silane monomers having only any one of stereoisomer, or a siloxane polymer produced by polymerizing the monomers, and a method of producing the low dielectric thin film using the same. When using the composition, mechanical properties are excellent because tacticity of a matrix is improved, and formation of pores is increased due to a molecular free volume, thus it is possible to produce a low dielectric thin film having low dielectricity.
    Type: Grant
    Filed: September 6, 2005
    Date of Patent: March 4, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyeon Jin Shin, Hyun Dam Jeong
  • Publication number: 20080044631
    Abstract: Methods for improving adherence of conductive traces, such as in a printed circuit, and circuits having conductive traces formed in accordance with such methods. One such method includes depositing a fluid composition receiving layer adjacent to a substrate, and depositing a gradient layer adjacent to the fluid composition receiving layer. The gradient layer is comprised of a fluid composition providing the fluid composition receiving layer and a fluid composition providing a conductive layer. A conductive layer composition is deposited adjacent to the gradient layer to provide the conductive layer.
    Type: Application
    Filed: August 14, 2007
    Publication date: February 21, 2008
    Applicant: LEXMARK INTERNATIONAL, INC.
    Inventors: Paul Sacoto, Jeanne Marie Saldanha Singh, Rebecca Beth Silveston-Keith
  • Publication number: 20080038528
    Abstract: A circuit material, comprising a conductive metal layer or a dielectric circuit substrate layer and an adhesive layer disposed on the conductive metal layer or the dielectric substrate layer, wherein the adhesive comprises a poly(arylene ether) and a polybutadiene or polyisoprene polymer.
    Type: Application
    Filed: July 27, 2007
    Publication date: February 14, 2008
    Applicant: WORLD PROPERTIES, INC.
    Inventor: Sankar K. Paul
  • Patent number: 7297361
    Abstract: A method for circuit fabrication includes positioning first and second webs of film in proximity to each other, wherein the second web of film defines a deposition mask, and deposition material on the first web of film through the deposition mask pattern defined by the second web of the to create at least a portion of an integrated circuit.
    Type: Grant
    Filed: September 14, 2004
    Date of Patent: November 20, 2007
    Assignee: 3M Innovative Properties Company
    Inventors: Paul F. Baude, Patrick R. Fleming, Michael A. Haase, Tommie W. Kelley, Dawn V. Muyres, Steven Theiss
  • Patent number: 7297360
    Abstract: An insulation film comprising an organosilicon polymer and an organic polymer such as polyarylene, polyarylene ether, polyimide, and fluororesin is disclosed, wherein the organosilicon polymer has a relative dielectric constant of 4 or less and has a dry etching selection ratio of 1/3 or less to silicon oxide, fluorine-doped silicon oxide, organosilicate glass, carbon-doped silicon oxide, methyl silsesquioxane, hydrogen silsesquioxane, a spin-on-glass, or polyorganosiloxane. The insulation film is used as an etching stopper or a hard mask in a dry etching process of interlayer dielectric films for semiconductors and can produce semiconductors having excellent precision with minimal damages.
    Type: Grant
    Filed: December 4, 2003
    Date of Patent: November 20, 2007
    Assignee: JSR Corporation
    Inventors: Mutsuhiko Yoshioka, Eiji Hayashi, Kouji Sumiya, Atsushi Shiota
  • Publication number: 20070261236
    Abstract: The invention is to provide a method of making an electrical connector. The method of making an electrical connector includes the following steps: (1) providing an insulator, which has a plurality of contact portions and a plurality of connecting portions, (2) coating a conducting layer on the insulator by a physical coating method, and (3) cutting the conducting layer between the contact portions and the connecting portions, such that the contact portions are formed as independent conducting areas. According to the method of making an electrical connector of the invention, the method is simple and does not use conducting terminals that have been compressed or bent several times. In this way, the quality is easily ensured, and the electrical connectors made by the method are capable of performing effective contacting with the electrical components.
    Type: Application
    Filed: October 4, 2006
    Publication date: November 15, 2007
    Inventor: Ted Ju
  • Patent number: 7293691
    Abstract: A system for depositing solder paste on a print window of a printed circuit board through a stencil includes a housing providing a printing chamber, a depositor configured to move relative to the housing and to deposit the solder paste, a support device disposed in the printing chamber and configured to receive the circuit board and to selectively hold the circuit board stationary relative to the housing, a loading mechanism configured to receive the circuit board and to transport the circuit board along a second direction to the support device, a controller coupled and configured to control dispensing of the solder paste by the depositor and the transporting of the circuit board by the loading mechanism, and a rotational apparatus coupled to the support device and configured to rotate the support device, where the controller is configured to cause the rotational apparatus to rotate the support device more than about 10° and to cause the depositor to deposit solder paste onto the circuit board after the rotat
    Type: Grant
    Filed: January 17, 2003
    Date of Patent: November 13, 2007
    Assignee: Speedline Technologies, Inc.
    Inventors: Mark Rossmeisl, Frank John Marszalkowski, Jr., Joseph A. Perault
  • Publication number: 20070231469
    Abstract: Compositions and processes for the preparation of printed circuits from epoxy compositions are provided. The epoxy compositions exhibit low viscosity in the uncured state and low coefficient of thermal expansion in the cured state. The low dielectric constant compositions of the invention are well-suited for use in multi-layer printed circuit boards.
    Type: Application
    Filed: April 3, 2007
    Publication date: October 4, 2007
    Inventors: Pui-Yan Lin, Govindasamy Paramasivam Rajendran, George Elias Zahr
  • Patent number: 7276267
    Abstract: A method making possible the production of an injection molded conductor carrying means composed of a first supporting substrate and a second supporting substrate. The first supporting substrate comprises a basically metallizeable plastic material and the second supporting substrate a basically non-metallizeable plastic material. However the plastic material of the second supporting substrate is able to be activated by a laser beam. The laser activation produces a metallization pattern on it and such pattern is connected with uncovered areas of the first supporting substrate, following which a common treatment takes place which results in an electrical conductor arrangement being produced. The invention furthermore relates to a conductor carrying means produced by the method.
    Type: Grant
    Filed: July 11, 2003
    Date of Patent: October 2, 2007
    Assignee: Festo AG & Co.
    Inventor: Stephan Schauz
  • Publication number: 20070218191
    Abstract: A method for manufacturing a wiring substrate by an electroless plating method that precipitates metal without using a plating resist is provided. The method includes the steps of: (a) providing a catalyst layer having a predetermined pattern on a substrate; (b) dipping the substrate in an electroless plating solution to thereby precipitate metal on the catalyst layer to provide a first metal layer; (c) exposing a top surface of the substrate to steam; and (d) dipping the substrate in an electroless plating solution to thereby precipitate metal on the first metal layer to provide a second metal layer.
    Type: Application
    Filed: March 1, 2007
    Publication date: September 20, 2007
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Hidemichi FURIHATA, Satoshi KIMURA, Toshihiko KANEDA, Takeshi KIJIMA
  • Patent number: 7267839
    Abstract: Disclosed is a method, in which when a liquid material is applied to the application surface of an object of application by using a liquid material supply device having a syringe containing the liquid material and equipped with a needle having at its distal end an ejection hole from which the liquid material is ejected, an image of the distal end of the needle is taken laterally by a horizontal camera together with a height reference mark when an ascent/descent drive system of the liquid material supply device is set to a reference height, and the height position of the distal end of the needle is obtained from the difference between the height of the distal end of the needle and the height of the height reference mark.
    Type: Grant
    Filed: August 20, 2004
    Date of Patent: September 11, 2007
    Assignee: TDK Corporation
    Inventors: Koji Tanaka, Hitoshi Nakayama, Shinji Atsuzawa, Youichi Andoh
  • Publication number: 20070207274
    Abstract: A circuit pattern is formed by following steps: forming a light-blocking mask over a major surface of a light-transmitting substrate, forming a first film in a first region over the substrate and the mask, forming a photocatalytic film in at least a part of the first region over the first film, changing wettability of the first film in a second region which is in the first region, being in contact with the photocatalytic film, and not overlapping the mask, by light irradiation from a back surface opposite to the major surface of the substrate, removing the photocatalytic film, and forming a composition including a pattern forming material in the second region.
    Type: Application
    Filed: March 1, 2007
    Publication date: September 6, 2007
    Inventor: Gen Fujii
  • Patent number: 7238306
    Abstract: Tribocharging-reducing conformal coating are provided for a flexible circuit, which reduce tribocharge voltage of a coated flexible circuit to less than about 15V, preferably less than about 10 V. Coating formulations include at least about 1% of a polypyrrole. Flexible circuits having a tribocharge voltage of less than about 15V, preferably less than about a 10V comprise at least one polymeric dielectric substrate, and a conductive layer formed thereon including at least one conductive element such as a trace, bond pad and/or a lead device, and a layer of a conformal coating wherein the conformal coating comprising at least about 1% of a polypyrrole compound.
    Type: Grant
    Filed: August 11, 2004
    Date of Patent: July 3, 2007
    Assignee: Innovex, Inc.
    Inventor: Eric E. Ries
  • Publication number: 20070148420
    Abstract: A printed circuit is made with a via-defining substrate including a microelectronic substrate defining via openings therein. Interconnects are provided on the via-defining substrate according to a predetermined interconnect pattern. The interconnects include a conductive layer having a pattern corresponding to the predetermined interconnect pattern. The conductive layer further being made substantially from a first material. The conductive layer further including a second material that is different from the first material. The second material including a metallic seeding material and is present on the via-defining substrate only at regions corresponding to the interconnects. The interconnects are formed by catalyzing the conductive layer with an activator layer to electrolessly plate the via-defining substrate with the first material.
    Type: Application
    Filed: December 28, 2005
    Publication date: June 28, 2007
    Inventors: Islam A. Salama, Omar J Behir
  • Patent number: 7232496
    Abstract: The present invention provides a method for manufacturing an electronic part that can cope with downsizing, improvement in performance and quality of a multilayer electronic part.
    Type: Grant
    Filed: March 2, 2005
    Date of Patent: June 19, 2007
    Assignee: TDK Corporation
    Inventors: Masayuki Yoshida, Shunji Aoki, Junichi Sutoh, Genichi Watanabe
  • Patent number: 7229502
    Abstract: A method of forming a silicon nitride layer is provided. A deposition furnace having an outer tube, a wafer boat, a gas injector and a uniform gas injection apparatus is provided. The wafer boat is positioned within the outer tube for carrying a plurality of wafers. The gas injector is positioned between the outer tube and the wafer boat. Similarly, the uniform gas injection apparatus is positioned between the outer tube and the wafer boat. Gas injected into the uniform gas injection apparatus is uniformly distributed throughout the entire deposition furnace. To form a silicon nitride layer on each wafer, a silicon-containing gas is passed into the deposition furnace via the gas injector and a nitrogen-mixed carrier gas is passed into the deposition furnace via the uniform gas injection apparatus.
    Type: Grant
    Filed: June 24, 2004
    Date of Patent: June 12, 2007
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Ching-Tang Wang, Chin-Tung Niao, Keng-Hui Su, Huang-Sheng Chiu, Min-Hsin Wang
  • Patent number: 7226634
    Abstract: The plating method comprises the steps of dividing a region, to be plated, into a group of mesh-like zones, measuring a plating area of each of the zones, comparing the measurement values of the plating areas and judging whether or not the plating area has any variance, and conducting a design change, on patterns contained in this zone, to eliminate the variance.
    Type: Grant
    Filed: October 2, 2002
    Date of Patent: June 5, 2007
    Assignee: Fujitsu Limited
    Inventor: Motoharu Nii
  • Patent number: 7213334
    Abstract: A double-sided flexible printed board is manufactured by: (a) forming a polyimide precursor layer on a metal layer; (b) forming an upper circuit layer on the polyimide precursor layer by a semi-additive technique; and (c) imidating the polyimide precursor layer to form a polyimide insulating layer.
    Type: Grant
    Filed: December 16, 2003
    Date of Patent: May 8, 2007
    Assignees: Sony Corporation, Sony Chemical & Information Device Corporation
    Inventors: Hideyuki Kurita, Masanao Watanabe
  • Patent number: 7201022
    Abstract: Methods of reducing the intrusions or migrations of photolithography materials by introducing a sol-gel layer onto a porous thin film prior to applying the photolithography/photoresist material layer. Curing the sol-gel layer results in the sol-gel layer merging or unifying with the underlying porous thin film layer so that the combined sol-gel/thin layer exhibits substantially the same properties as the untreated porous thin film layer before the sol-gel was applied. As a result, a greater etching accuracy is achieved.
    Type: Grant
    Filed: June 17, 2005
    Date of Patent: April 10, 2007
    Assignee: Xerox Corporation
    Inventors: James Charles Zesch, Joost J. Vlassak
  • Patent number: 7189302
    Abstract: A fabricating method for a multi-layer printed circuit board is provided. The method may include attaching a releasing film at upper and lower surfaces of a center layer and attaching a first metal film to each of the releasing films and a resist layer to each of the first metal films to form a base member. A first connection portion may then be formed on each of the first metal films, and a second connection portion may be integrally formed on each of the first connection portions. A second metal film may then be formed on each of the second connection portions so as to be electrically connected to the connection portions, and, in turn, to the first metal films. Specific portions of the second metal films may be etched to form copper patterns. Upper and lower portions may then be separated by the releasing films to form separate multi-layer printed circuit boards.
    Type: Grant
    Filed: November 5, 2004
    Date of Patent: March 13, 2007
    Assignee: LG Electronics Inc.
    Inventors: Jung-Ho Hwang, Sung-Gue Lee, Sang-Min Lee, Joon-Wook Han, Tae-Sik Eo, Yu-Seock Yang
  • Patent number: 7179503
    Abstract: A solution containing a metal component of composite ultrafine metal particles each having a core substantially made of metal component and a covering layer made of an organic compound chemically bonded to the core having an average diameter ranging from 1 to 10 nm, uniformly dispersed in a solvent, forms a thin metal film on the surface of a transfer sheet, after which the transfer sheet, after which the transfer sheet is thermally decomposed to transfer the thin metal film to a substrate.
    Type: Grant
    Filed: June 19, 2003
    Date of Patent: February 20, 2007
    Assignee: Ebara Corporation
    Inventors: Akira Fukunaga, Hiroshi Nagasawa, Takao Kato
  • Patent number: 7175876
    Abstract: Patterned articles can be prepared by applying a release polymer to a substrate in a desired pattern, applying a substrate-adherent polymer over the pattern and substrate, and mechanically removing the substrate-adherent polymer from the pattern without requiring solvent. Suitable mechanical removal methods include applying adhesive tape to the substrate-adherent polymer and peeling the tape and substrate-adherent polymer away from the pattern, and abrading the substrate-adherent polymer from the pattern using impact media.
    Type: Grant
    Filed: June 27, 2003
    Date of Patent: February 13, 2007
    Assignee: 3M Innovative Properties Company
    Inventors: M. Benton Free, Mikhail L. Pekurovsky
  • Patent number: 7172925
    Abstract: There is provided a method for manufacturing a flat printed wiring board in which spaces between circuit patterns are filled with a resin. The method comprises: laminating via a mold release film a plurality of sets of laminated bodies formed by superposing a semi-cured resin sheet on a printed wiring board with circuit patterns formed thereon; placing the laminated plural sets of the laminated bodies interposed between a pair of smoothing plates and collectively pressing the laminated bodies in a reduced pressure atmosphere used for curing the resin; and then polishing the cured resin covering the circuit patterns, thereby exposing the circuit patterns.
    Type: Grant
    Filed: December 12, 2002
    Date of Patent: February 6, 2007
    Assignee: Noda Screen Co., Ltd.
    Inventor: Keiichi Murakami
  • Patent number: 7141184
    Abstract: A resistive composition for screen printing onto a substrate to form a cured film. The resistive composition, based on total composition, has a) 5–30 wt. % of polymer resin, b) 10–30 wt. % conductive particles selected from the group consisting of carbon black, graphite and mixtures thereof and c) 0.1–10 wt. % zirconia particles, wherein all of (a), (b), and (c) are dispersed in a 60–80 wt. % organic solvent. A cured resistive film composition is also disclosed.
    Type: Grant
    Filed: December 8, 2003
    Date of Patent: November 28, 2006
    Assignee: CTS Corporation
    Inventor: Antony P. Chacko
  • Patent number: 7135204
    Abstract: A method of manufacturing a wiring board is provided. The method includes performing a plating process to a land, in a condition that a resist film having an opening for exposing at least the center of the land is formed on a substrate with wires having the land formed thereon, so that a fist portion of an edge of the opening is disposed on the substrate and a second portion of the edge is disposed on the land.
    Type: Grant
    Filed: January 15, 2004
    Date of Patent: November 14, 2006
    Assignee: Seiko Epson Corporation
    Inventor: Fumiaki Karasawa