Abstract: A method and apparatus adapted to calibrate a signal path of a signal analysis system such that loading effects of the system are substantially removed from measurements of a device under test. A signal under test from the device under test is coupled to a test probe in the signal path and used with selectable impedance loads in the test probe to characterize transfer parameters of the device under test. An equalization filter in either the frequency or time domain is computed from the device under test transfer parameters for reducing in signal error attributable to the measurement loading of the device under test.

Abstract: A pre-emphasis filter emphasizes a high-frequency component of an input audio signal. A limiter circuit detects that the output signal from the pre-emphasis filter reaches a predetermined upper limit level. A filter adjusting circuit changes the frequency characteristic of the pre-emphasis filter when a limit operation is generated in the limiter circuit.

Abstract: A method for generating an output sequence of samples in response to a first and a second subsequence of samples, the method comprising—applying a weighted overlap-add procedure to the first and second subsequences so as to generate the output sequence of samples, —optimizing a weighting function involved in the weighted overlap-add procedure in response to a measure of matching between the output sequence of samples and one or more target sequences of samples.

Abstract: A method of optimizing filter performance through monitoring channel characteristics is provided. A signal enters a channel and a receiver receives the signal. The receiver includes a FIR filter to remove near-end transmitted interference and recover a far-end desired signal. The filter has storage elements configured as a shift registers to move the signal, multipliers to multiply the signal by a filter coefficient, an intermittent summer to combine the multiplied results into a replica of an interfering signal, a final summer to remove the replica from the receiver signal to provide direct and indirect monitoring of the signal, where direct monitoring includes time or frequency monitoring, and indirect monitoring includes monitoring signal to noise ratio, error magnitude or bit error rate. The filter is optimized according to monitoring and includes reducing a dynamic range, reducing bits of precision, reducing linearity, the filter, and reallocating the filter.

Abstract: A method for applying a computation utilizing a processor (112) capable of accessing an on-chip memory (114) and data from an off-chip source (116), the method comprising the iterative steps of retrieving at the on-chip memory (114) successive frames of input data from the off-chip source (116); computing from a current input frame of data (30) available in the on-chip memory current result elements for completing a current output frame of results (33, 34, 35), and pre-computing from the current frame of input data future result elements for contributing to at least one future output frame of results.

Abstract: A method, apparatus and computer program product implement optimized channel routing in an electronic package design. Electronic package physical design data are received. A physical design including a netlist including a plurality of nets is generated. Finite impulse response (FIR) driver coefficients are determined for each net in the netlist from simulation with generation of impulse responses of the netlist.

Abstract: Enhancements to hardware architectures (e.g., a RISC processor or a DSP processor) to accelerate spectral band replication (SBR) processing are described. In some embodiments, instruction extensions configure a reconfigurable processor to accelerat SBR and other audio processing. In addition to the instruction extensions, execution units (e.g., multiplication and accumulation units (MACs)) may operate in parallel to reduce the number of audio processing cycles. Performance may be further enhanced through the use of source and destination units which are configured to work with the execution units and quickly fetch and store source and destination operands.

Abstract: A dynamic weight generator. The inventive generator includes a first memory for storing a PN code; a second memory for storing a plurality of weights, the second memory being coupled to the first memory whereby data output by the first memory is used to address data stored in the second memory; and a correlator for multiplying an input signal by data output by the second memory. In the illustrative embodiment, the weights are finite impulse response filter correlation coefficients. The correlator includes two multipliers. The first of the multipliers is coupled to a source of an in-phase component of the input signal. The second of the multipliers is coupled to a source of a quadrature component of the input signal. The outputs of the multipliers are summed. In the illustrative application, the input signal is a GPS signal. For this application, the inventive teachings are implemented in a signal processing system adapted to receive a GPS signal and provide in-phase and quadrature signals in response thereto.

Abstract: A computer executable method of performing a modal interval operation, and system for performing same is provided. The method includes providing representations of first and second modal interval operands. Each modal interval operand of the operands is delimited by first and second marks of a digital scale, each mark of the marks comprises a bit-pattern. Each bit-pattern of the bit-patterns of the marks of each of the modal interval operands are examined, and conditions of a set of status flags corresponding to each bit-pattern of the bit-patterns of the marks are set. A bit-mask is computed wherein the mask is based upon the set condition of the status flag sets and a presence/absence of an exceptional arithmetic condition, and a presence/absence of an indefinite operand are each represented by a bit of said bits of said bit mask.

Abstract: Methods and apparatus for providing data processing and control for use in a medical communication system are provided.

Abstract: Signal processing apparatus or non-integer divider with a small circuit scale and a fractional N-PLL synthesizer comprising same. An adder 2 and a delay device 4 constitute a 20-bit input accumulator and its input is connected to a signal input terminal 1. Adder 8 and a delay device 10 constitute a 9-bit input accumulator. Into higher 8 bits of its input, higher 8 bits of the output of the accumulator comprising the adder 2 and the delay device 4 are inputted. The output of a 3-input NAND gate 30 is connected to the remaining lowest bit input. An adder 13 and a delay device 15 constitute a 6-bit input accumulator. Higher 6 bits of an output signal of the adder 8 are inputted into this 6-bit input accumulator. An adder 18 and a delay device 20 constitute a 4-bit input accumulator. Higher 4 bits of an output signal of the adder 13 are inputted into this 4-bit input accumulator. Lower 3 bits of output data of the 4-bit delay device 20 are inputted into the 3-input NAND gate 30.

Abstract: Optically coherent, two-port, serially cascaded-form optical delay line circuits can realize arbitrary signal processing functions identical to those of FIR digital filters with complex filter coefficients whilst maintaining a maximum optical transmission characteristic of 100%. The invention provides an iterative process for transitioning in a step-wise manner a filter function of an optical delay line circuit filter from a start filter function to a target filter function. The invention also describes a dynamic gain equalizer incorporating an optical delay line circuit filter.

Abstract: Provided is a complex exponential modulation filter bank which can reduce quantity of arithmetic operation, and can realize low electric power consumption or speeding-up. This complex exponential modulation filter bank has a step of calculating a first intermediate signal from an input signal, a step of calculating a second intermediate signal from the first intermediate signal, a step of calculating a third intermediate signal from the second intermediate signal with fast Fourier transform, and a step of calculating a complex band output signal from the third intermediate signal.

Abstract: To provide a monitoring device which can detect conditions of a sleeping person reliably and which is simple. A monitoring device comprising: multiple independent distance sensors 11 installed facing different positions in a monitored target area 50 to be monitored for measuring a distance to a monitored target 2, a calculating unit 22 for calculating changes over time in the outputs of the distance sensors 11, and a detection processor 23 for detecting changes in shape of the monitored target 2 based on the calculated changes over time in one or multiple distance sensor 11 among the multiple distance sensors 11.

Abstract: The present invention relates to a bank of digital filters that can be cascade connected. It also relates to a reception circuit comprising such a bank of cascaded filters. With the digital filter being sampled at a given sampling frequency Fs, the bank of cascadable digital filters has: at the input, a frequency transposition circuit (31) for the digital signal. A polyphase filter (30) receives as input the frequency-transposed digital signal clocked at the sampling frequency Fs. The polyphase filters has an FFT filter (32) having a number N of points. The output of the filtering device retains a given number of outputs (36) of the FFT filter (32) so that the information bit rate at the output of the device is equal to the information bit rate at the input. The invention is particularly applicable to heterodyne-type radar signal receivers.

Abstract: A computer implemented method filters input data with a kernel filter. A kernel filter is defined, and a set of unique filter coefficients for the kernel filter are determined. A linkage set is constructed for each unique filter coefficient such that the linkage set includes relative links to positions in the kernel filter that have identical filter coefficients, and in which each relative link is an inverse of the position of the unique filter coefficient. Each input data point is processed by multiply values on which the kernel filter is centered by each of the unique filter coefficients, and adding results of the multiplying to the corresponding output data points as referenced by the relative links.

Abstract: Nonlinear filtering and deblocking applications utilizing SIMD (single instruction multiple data) sign and absolute value operations are disclosed. The method of one embodiment includes receiving first data for a first block and second data for a second block. The first data and said second data include a plurality of rows and columns of pixel data. A block boundary between the first block and the second block is characterized. A correction factor for a deblocking algorithm is calculated with a first instruction for a sign operation that multiplies and with a second instruction for an absolute value operation. Data for pixels located along said block boundary between the first and second black are corrected.

Abstract: A signal processing apparatus, comprising: a first filter on an in-phase signal channel; a second filter on a quadrature signal channel; a plurality of filter stages having each of more than one signal paths crossing each other which connects the first filter and the second filter; and at least more than one of the filter stages of more than one of a plurality of the filter stages comprises a switching circuit disconnecting more than one of the signal paths and a correction unit correcting direct current offsets of the first filter and the second filter by using the switching circuit.

Abstract: Adaptively analyzing an observed signal to estimate that part of the signal that best corresponds to a steering vector. Modifying the steering vector by convolution of the steering vector with a vector estimating the effect of multipath on the observed signal.

Abstract: A micro-programmable filter (MFE) engine includes multiple programmable filter elements and a microcode controller. The filter elements can be configured, controlled, and combined in different ways to implement different types of filters. The MFE preferably supports multiple-execution instructions that allow a single instruction to perform multiple moves into accumulators for efficient data movement inside MFE.

Abstract: The arithmetic processing apparatus of the present invention is an arithmetic processing apparatus that can be reconfigured in accordance with a processing mode and has a plurality of arranged unit arithmetic circuits. Each unit arithmetic circuit includes at least one input terminal, at least one output terminal, a first register which holds data, an adder which calculates a sum of two pieces of data, a second register which holds data, a bit shifter which shifts data left or right, a subtractor which calculates a difference between two pieces of data, an absolute value calculating unit which calculates an absolute value of data, and a path setting unit which sets a path according to the processing mode connecting among these circuit elements.

Abstract: A power amplifier pre-distorter is formed by a FIR filter structure which includes an individual look-up table for each filter tap, where each look-up table represents a sample polynomial in a variable representing signal amplitude, and means for selecting, from each filter tap look-up table, a filter coefficient that depends on the amplitude of corresponding complex signal value to be multiplied by the filter tap. A training method for such a pre-distorter sets (S1) the entries of table T0 and T1 to predetermined values. Then it measures and stores (S2) a batch of input signals x and feedback signals y. New estimates of T0 and T1 are determined (S3) using an iteration of a least mean square based iterative procedure. Then it is tested (S4) whether the tables have converged. If the tables have converged, the current estimates are provided as the final tables. Otherwise another iteration (S2-S4) of the least mean square procedure is performed.

Abstract: A sample rate converter suitable for use in an audio DAC includes a first estimating circuit (32A) generating first (TR) and second (STAMPR) signals synchronized to an asynchronous clock (MCLK) and representing the period and edge arrival times, respectively, of a reference clock (REFCLK). A second estimating circuit (32B) operates on the first and second signals to generate third (T1) and fourth (STAMP1) signals representing an input sample rate (32fsin) and arrival times of input data samples, respectively, which are applied to a coefficient and address generator (76) to generate read addresses and coefficients input to a FIFO memory (42) receiving digital input data at the input sample rate and a multiplication/accumulation circuit (78) receiving data from the FIFO memory. The multiplication/accumulation circuit produces an output signal (SRC-out) synchronized to the asynchronous clock at an output sample rate (32fsout).

Abstract: An apparatus for measuring energy usage. The apparatus can include an amplifier having a plurality of gain stages and the amplifier can be for receiving an input signal. The apparatus can also include an analog-to-digital converter that is coupled to the amplifier. Furthermore, the apparatus can include a scaling adjustment module that is coupled to the analog-to-digital converter. Additionally, the apparatus can include a gain control module coupled to the analog-to-digital converter.

Abstract: An eye opening measurement technique, that does not interrupt a receiver's normal operation, is used as a metric for optimizing any selected parameters of the receiver's operation. If eye opening size decreases, as a result of a change to a receiver parameter, the polarity for stepwise changes is reversed such that the next change is in the opposite direction. Other types of search procedures can be used. Eye opening size is the difference between the eye's upper and lower edges. Measurement of eye opening size is accomplished using a data and auxiliary slicer that find each “edge” of an eye opening based upon the slicers' level of agreement. Depending upon the level of agreement, and whether symbols of the upper or lower region of the eye are counted, the threshold of the auxiliary slicer can be adjusted in the direction necessary to converge on the eye edge sought.

Abstract: A Finite Impulse Response (FIR) filter is implemented in software on a general purpose processor in a manner which reduces the number of memory accesses as compared to conventional methods. In particular, an efficient implementation for a general purpose processor having a substantial number of registers includes inner and outer loop code which together make K ? [ ( L 1 + L 2 L 1 ? L 2 ) ? N + L 2 L 1 + 1 ] memory accesses and KN multiply-accumulates, where L1 is the number of output vector elements computed during each pass through the outer loop and where L2 is the number of taps per output vector element computed during each pass through the inner loop. The efficient implementation exploits L1+2L2 general purpose registers.

Abstract: Systems and processes may apply a filter to data in a graph structure using an interface. The filter may be applied upon request from a business application. The interface may determine which portions of the graph structure satisfy the filter criteria. The interface may replace nodes and/or relations that do not satisfy filter criteria with skip nodes or functions. For example, software can be operable to apply a filter to a graph structure that includes nodes and relations between the nodes and evaluating the graph structure according to the filter. The software then replaces a first of the nodes that does not satisfy the filter with a first skip node.

Abstract: A digital filter and method of filtering frequency translate or shift a spectrum of a digital input signal and further filter a translated signal to reduce or attenuate frequency components in the spectrum of the input signal. The digital fitter includes first and second translators and a first filter. The first filter is connected between the first and second translators and is centered approximately at direct current (DC). The digital filter may further include a second filter, a third translator connected to an output of the second filter, a complex local oscillator connected to an input of each translator, and a complex-to-real converter connected to an output of the third translator. The method includes frequency translating the digital input signal and separately frequency translating a first translated signal after the first translated signal is filtered to produce a second translated signal.

Abstract: Wavelet filters computed from a wavelet transform are used for encoding, transmitting, receiving, and decoding spread spectrum signals on multiple parallel frequency channels. The transmitter encodes the data stream via a mapping to a basis set of wavelets which are orthogonal across the time domain. The spread spectrum data is parsed from a serial bit stream to several parallel streams. The number of bits per symbol need not remain constant. Signals are created from each symbol by first up sampling by inserting zeros between successive symbols. These signals are passed through a bank of low-pass and high-pass filters derived from a wavelet packet transform. The resulting signal is transmitted in the base band of the transmission system, or transmitted by modulating the carrier of the transmission system. At the receiver, the steps are reversed to recover the symbols. Symbol decisions are made through any one of a number of methods.

Abstract: A method for long impulse response digital filtering of an input data stream, by use of a digital filtering system. Where the input data stream is divided into zero-input signals and zero-state signals. One of the zero-input signals and a corresponding impulse response of the digital filtering system is converted lo the frequency domain to determine a respective zero-input response of the digital filtering system. One of the zero-state signals is convolved with a corresponding impulse response of the digital filtering system to determine a respective zero-state response of the digital filtering system, wherein at least part of the zero-input signal precedes the zero-stale signal. The zero-state response of the digital filtering system is added to the zero-input response or the digital filtering system to determine the response of the digital filtering system. Apparatus for effecting this method is also disclosed.

Abstract: A system and method for accelerating the performance of finite impulse response (FIR) filtering operations in a processor system. The system and method accelerates FIR filtering operations by using a holding register to provide additional input samples to an instruction beyond those normally accommodated by source registers, and by using a large number of multipliers that can operate in parallel on the input samples in order to generate output sample of a FIR filter, such as a non-decimating FIR filter.

Abstract: A receiver unit includes a prefilter that receives as one of the inputs a channel impulse response (CIR) estimation data set and removes unnecessary data information from the CIR estimation data set and filters input signal so to form a first output data set. An equalizer core receives the first output data set and based on computed CIR length and SNR value of the first output data set so as to determine which portion of the first output data set are assigned to at least one of at least two low complexity equalization modules used for processing.

Abstract: In one aspect a system and method for providing a multi-port memory having a plurality of read ports, each read port including a filter coefficient value representing a dispersion compensation value associated with an optical link. The method includes processing an input optical signal using the filter coefficient values in the multi-port memory to generate an output optical signal for transmission on the optical link.

Abstract: A finite impulse response filter is implemented as a sum of individual component, running-sum filters. The sum of all of the component filters required for a desired filter response is calculated in an accumulator and only the component filters' update terms, which are the difference between a new and an old discarded sample, is calculated for each component filter. A desired impulse response is decomposed into a sum of rectangular impulse responses of equal height, each of which implemented as a running sum requiring a subtraction and an addition. Using circuits running at a multiple of the sampling clock, multiple running sums may be implemented on the same hardware. A whole filter of arbitrary impulse response shapes and lengths may be implemented using memory and two arithmetic units. Two or more such filters may be cascaded to obtain a better approximation of the desired frequency characteristic. The invention saves significant chip resources and manufacturing costs.

Abstract: The present invention provides a method and device for generating a filter coefficient in real time. The method includes: looking up a converted window function value in a converted window function table based on a current coefficient index; generating a current cut-off angular frequency; generating a look-up table address based on the current coefficient index, the filter order and the current cut-off angular frequency and looking up a sine value in a sine table based on the look-up table address; and multiplying the converted window function value by the sine value to obtain the filter coefficient. The device includes a first memory, a second memory, a look-up table address generation module and a first multiplier. The present invention is easily implemented with low hardware resource consumption and high flexibility, and is particularly applicable for the hardware implementation of high-order finite impulse response filters.

Abstract: A signal power coefficient and a noise power coefficient are calculated for each channel, using parameters which have been optimized up to a small error value by an optimizing means, then using the thus-calculated signal power coefficient and noise power coefficient, there are determined a signal power and a noise power for each channel, and the signal power and the noise power thus determined are displayed on one and same display screen channel by channel.

Abstract: There provided is a low-cost, high performance sampling rate conversion calculating apparatus which achieves both a low delay characteristic required for conversational voice data and high quality required for audio data in a concurrent manner. A first digital signal processing section outputs conversational voice data, which requires the low delay characteristic, in accordance with a sampling frequency of an output terminal (111). A second digital signal processing section outputs audio data, which requires the high quality, rather than the low density characteristic, in accordance with the sampling frequency of the output terminal (111). An adder section (107) adds the conversational voice data outputted from the first digital signal processing section and the audio data outputted from the second digital signal processing section and outputs the added data from the output terminal (111).

Abstract: A method for designing Wavelets for communications and radar which combines requirements for Wavelets and finite impulse response FIR filters including no excess bandwidth, linear performance metrics for passband, stopband, quadrature mirror filter QMF properties, intersymbol interference, and adjacent channel interference, polystatic filter design requirements, and non-linear metrics for bandwidth efficient modulation BEM and synthetic aperture radar SAR. Demonstrated linear design methodology finds the best design coordinates to minimize the weighted sum of the contributing least-squares LS error metrics for the respective performance requirements. Design coordinates are mapped into the optimum FIR symbol time response.

Abstract: A new system and method is developed for reducing the crest factor of a signal. The system includes a large signal extraction module for receiving the input signal and the magnitude of the input signal to extract a large signal greater than a predetermined threshold ?; a large signal transformation module for converting the extracted large signal to a monotonically increasing concave function; a large signal filtering module for filtering the large signal transformed by the large signal transformation module to pass a predetermined band of the large signal; a delay means for shifting the phase of the input signal; and a combiner means for combining the signal output from the large signal filtering module with the input signal whose phase has been shifted by the delay means to reduce the crest factor of the input signal.

Abstract: A method and apparatus for reducing the crest factor of a signal uses a plurality of partial correction signals having respective predetermined frequencies. For each of the partial correction signals, the following steps are performed: (a) determining a time position of a maximum absolute amplitude of the signal; (b) calculating an amplitude and a phase depending on said maximum absolute amplitude and said time position for the respective partial correction signal; and (c) subtracting the respective partial correction signal from said signal to obtain a partially corrected signal which is used as the signal in step (a) for the next of the plurality of partial correction signals, and going to step (a) for calculating the next partial correction signal. The last-obtained partially corrected signal is output as the reduced-crest factor signal.

Abstract: A method and apparatus for designing low-order linear-phase IIR filters is disclosed. Given an FIR filter, the method utilizes a new Krylov subspace projection method, called the rational Arnoldi method with adaptive orders, to synthesize an approximated IIR filter with small orders. The method is efficient in terms of computational complexity. The synthesized IIR filter can truly reflect essential dynamical features of the original FIR filter and indeed satisfies the design specifications. In particular, the linear-phase property is stilled remained in the passband.

Abstract: A method of controlling data processing logic which causes a data value to be rotated by a number of bits in order to generate a rotated data value; a number of least significant bits of the rotated data value are masked with other bits of said rotated data value not being masked in order to generate a masked rotated data value; a selected bit of said rotated data value are masked with other bits of said rotated data value not being masked in order to generate a bit preset rotated data value; and said sign-extended bit field extracted data value to be generated by subtracting said masked rotated data value from said bit preset data value or said zero-extended bit field extracted data value to be generated by performing a logical exclusive-OR operation with the masked rotated data value and said bit preset data value.

Abstract: Finite response filters (FIRs) are divided into partial filters that filter a same portion of image data to generate partial filtered results. The partial filtered results may be saved and later retrieved to generate complete filter outputs.

Abstract: A digital filter circuit is capable of processing multi-channel data having different sampling frequencies. RAMs (random access memories) are provided which store data inputted thereto respectively, and the data outputted from the RAMs are alternately processed.

Abstract: A method for inverting telecommunication channel distortion by adaptive wavelet lifting. The distortion signal is analyzed using wavelet lifting and the inverse filter is computed. Coefficients of the inverse filter are used to either compute a transmission pre-filter or to update the transmitted message.

Abstract: A method for processing an image using a bilateral filter. The bilateral filter is reformulated at each pixel location in the image into a sum of the original signal value of a central pixel at said pixel location and a bilateral correction term which is a function of local signal differences between the central pixel and its neighbors. The bilateral correction term is calculated using a computationally efficient approximation.

Abstract: A power spectrum estimator consistent with certain embodiments has a pulse extraction circuit that compares a digital input signal with a delayed version of the digital input signal to produce an output signal containing extracted pulses. An averaging circuit receives the output pulse and produces therefrom an averaged signal representing the averaged value of the output signal. A subtracter subtracts a reference signal from the averaged signal to produce a difference signal. An absolute value circuit converts the difference signal to an error signal by taking the absolute value of the difference signal. This abstract is not to be considered limiting, since other embodiments may deviate from the features described in this abstract.

Abstract: A non-uniform filter bank is created by joining sections of oversampled uniform filter bands that are based on complex exponential modulation (as opposed to cosine modulation). Each filter bank handles a given, non-overlapping frequency band. The bands are not of uniform bandwidth, and the filters of different banks have different bandwidths. The frequency bands of the different filter banks cover the frequency of interest with gaps in the neighborhoods of the filter band edges. A set of transition filters fills those gaps.

Abstract: Briefly, in accordance with one embodiment of the invention, a programmable filter may implement an infinite impulse response filter so that a transceiver in which the filter is utilized may be programmable to operate in one or more modes in accordance with one or more communication standards. The programmable infinite impulse response filter may replace one or more analog filters of the transceiver so that a desired filter response may be programmed by a baseband processor. Delay functions of an infinite impulse response filter may be implemented using feedback and multiplexing.

Abstract: The present invention relates to a data processing apparatus, a method and apparatus for encoding, a method and apparatus for decoding, and a program, that allow a reduction in an algorithm delay. An interpolator 51 produces interpolated PCM data by performing R-times oversampling on original PCM data. A frame encoder 54 fetches a predetermined number of samples of the oversampled data as one frame, encodes the oversampled data on a frame-by-frame basis, and outputs resultant encoded data. A frame decoder 55 decodes the encoded data on a frame-by-frame basis at a rate R times higher than a predetermined normal rate. A decimator 56 decimates data obtained as a result of the decoding such that the number of samples is reduced to 1/R of the number of sampled included in the original data. The present invention is applicable, for example, to an IP telephone system.