Abstract: A programmable logic device can be configured as a finite impulse response (FIR) filter capable of operating in either interpolation mode or decimation mode and of switching between those modes at run time. The FIR filter structure can be mapped onto a specialized processing block of the programmable logic device that includes multipliers and adders for adding the products of the multipliers. The FIR filter structure minimizes the number of multipliers used by reusing various calculations that are repeated as a result of the interpolation or decimation operation, using multiplexers or other run-time-controllable selectors to select which current or stored multiplier outputs to use.

Abstract: The present invention relates to a method of processing a sequence of digital images, intended to detect, in a dynamical manner, a grid comprising blocking artefacts. Said method comprises the steps of, a) detecting (100) a current spatial grid (SG(t)) within a portion of the image constituted by a current field (FLD(t)), b) determining (200) a current reference grid (RG(t)) from a current spatial grid (SG(t)) and a preceding reference grid (RG(t-1)) supplied by a memory MEM (150), the current reference grid (RG(t)) being subsequently stored temporarily in the memory MEM (150), and c) correcting COR (300) blocking artefacts which are present in the current field (FLD(t)) from the preceding reference grid (RG(t-1)) so as to supply a processed field (PPP(t)).

Abstract: A digital signal processing device includes: a memory for coefficient storage including partial memories that dividedly store, for each plurality of bits, a plurality of filter coefficients as divided data; a control unit that outputs, to the memory for coefficient storage, an address signal added with activation/inactivation control information; a CE-signal interrupting unit that transmits the CE signals to the partial memories or interrupts the CE signals based on the activation/inactivation control information; an output selecting unit that is provided in at least a part of the partial memories and selects and outputs, based on the activation/inactivation control information, an output of the partial memory or all-bit zero value; a multiplier that performs multiplication of each of a plurality of input data and each of the filter coefficients including the output of the output selecting unit; and an integration circuit system that integrates multiplication results output from the multiplier.

Abstract: A filtering apparatus for obtaining an output in a case where a discrete-time signal having a length of N (N is an integer) is input to an FIR filter with a filter coefficient having a length of M (M is an integer, N?M?1), including: a division unit for dividing the discrete-time signal; a first zero padding unit for padding zero after the discrete-time signals; a first fast Fourier transform unit for performing FFT on the zero padded data; a second zero padding unit for padding zero after the filter coefficient; a second fast Fourier transform unit for performing FFT on the zero padded data; a multiplication unit for multiplying the frequency domain data by the frequency domain data; an inverse fast Fourier transform unit for performing IFFT on the multiplication results; and an adder unit for adding the discrete-time signals.

Abstract: Methods, circuits, and an apparatus for filtering high-speed serial data is disclosed. In one embodiment, a Programmable Logic Device (PLD) is configured with a filter circuit for filtering serial data at a first clock rate. The filter circuit converts an N number of serial data streams into an N number of M-bit words based on a deserialization factor. The M-bit words are converted to an M number of N-bit data words. The N-Bit data words are filtered at a second clock rate, reformatted, serialized, and outputted as individual serial data streams at the first clock rate. In one embodiment, the N-bit data words are digitally filtered by a Finite Impulse Response (FIR) filter operating at the second clock rate. The data output of the FIR filter is then serialized into an N number of serial data output streams operating at the first clock rate.

Abstract: Noise discrimination in signals from a plurality of sensors is conducted by enhancing the phase difference in the signals such that off-axis pick-up is suppressed while on-axis pick-up is enhanced. Alternatively, attenuation/expansion are applied to the signals in a phase difference dependent manner, consistent with suppression of off-axis pick-up and on-axis enhancement. Nulls between sensitivity lobes are widened, effectively narrowing the sensitivity lobes and improving directionality and noise discrimination.

Abstract: A method for realizing a digital filter in an electronic system. The method includes first determining the specific number of coefficients to be calculated for a design filter and calculating the value of some of the coefficients for the design filter, typically all but one. Next, a reference filter is selected having the same number of coefficients as the design filter and each coefficient of the reference filter is calculated. With the reference filter's coefficients, the method concludes by determining the value of the remaining coefficients of the design filter that were previously not calculated. The determination is based upon an arithmetic comparison to the coefficients of the reference filter. The system and method improve second-order filter response for certain filters implemented with a direct-form topology.

Abstract: Wavelet filters computed from a wavelet transform are used as a means of pulse shaping binary data transmitted and received over multiple parallel channels. At the transmitter the data is parsed from a serial bit stream to several parallel streams. Within each of the parallel bit streams symbols are formed. Signals are created from each symbol by up-sampling by inserting zeros between successive symbols. These signals are passed through a bank of low-pass and high-pass filters derived from a wavelet packet transform. The filters are paired: one high-pass with a low-pass. The ordering is alternated to preserve “natural” frequency ordering. These steps are repeated for this set of signals until only one signal remains. The remaining signal is transmitted in the base band of the transmission system or they are transmitted by modulating the carrier of the transmission system. At the receiver the steps are reversed to recover symbols.

Abstract: Methods and circuits are presented for providing equalization, including decision feedback equalization (DFE), to high data-rate signals. Half-rate delay-chain circuitry produces delayed samples of an input signal using two or more delay-chain circuits operating at a fraction of the input signal data-rate. Two delay-chain circuits operating at one-half the input signal data-rate may be used. More generally, n delay-chain circuits operating at 1/n the input signal data-rate may be used. Multiplexer circuitry combines the outputs of the delay-chain circuits to produce an output signal including samples of the input signal at the input signal data-rate. Duplicate path DFE circuitry includes two paths used to provide DFE equalization while reducing the load of the DFE circuitry on the circuitry that precedes it. A first path produces delayed samples of a DFE signal, while a second path produces the DFE output signal from the delayed samples.

Abstract: Mass flow meter having at least one measurement tube, through which mass flows, as an oscillation body which can be set in mechanical oscillation by means of an excitation unit, the oscillation behavior of which varying as a function of the mass flow can be recorded via at least one oscillation sensor in order to determine the mass flow, wherein in order to eliminate noise signals from the measurement voltage (sen) recorded via the oscillation sensor computational technology means are provided for forming a complex conjugate spectrum (|sa1j|) from the spectrum of the excitation voltage (seD) as well as a vector product between this (|sa1j|) and the measurement voltage (sen) for the purpose of filtering, in order, by further computational technology means for inverse Fourier transformation, to obtain the signal relationship associated with the vector product between the excitation voltage (seD) and the measurement voltage (sen) so that the processed measurement voltage (sa1) resulting therefrom then predominan

Abstract: A digital high-pass filter has an input, an output, and a subtractor stage, having a first input terminal, a second input terminal and an output terminal. The first input terminal of the subtractor stage is connected to the input of the digital high-pass filter and the output terminal is connected to the output of the digital high-pass filter. A recursive circuit branch is connected between the output of the digital high-pass filter and the second input terminal of the subtractor stage. Within the recursive circuit branch are cascaded an accumulation stage, constituted by an integrator circuit, and a divider stage. The cutoff frequency of the digital high-pass filter is variable according to a dividing factor of the divider stage.

Abstract: A repetitive controller scheme with positive feedback and feedforward introduces infinitely many poles on the imaginary axis located at the resonant peaks. The feedforward introduces zeros, which produce notches located in between two consecutive resonant peaks. The latter has the advantage of making the controller more selective, in the sense that; the original overlapping (appearing at the valleys in a simple positive feedback repetitive controller) or interaction between consecutive resonant peaks is removed by the notches. This would allow, in principle, peaks of higher gains and slightly wider bandwidth, avoiding, at the same time, the excitation of harmonics located in between two consecutive peaks. The repetitive controller includes a simple Low Pass Filter (LPF). This modification restricts the bandwidth of the controller and at the same time reinforces stability when the controller is inserted in the closed-loop system.

Abstract: Reflectionless low-pass, high-pass, band-pass, and band-stop filters, as well as a method for designing such filters is disclosed. The filters function by absorbing the stop-band portion of the spectrum rather than reflecting it back to the source, which has significant advantages in many different applications.

Abstract: Passive switched-capacitor (PSC) filters are described herein. In one design, a PSC filter implements a second-order infinite impulse response (IIR) filter with two complex first-order IIR sections. Each complex first-order IIR section includes three sets of capacitors. A first set of capacitors receives a real input signal and an imaginary delayed signal, stores and shares electrical charges, and provides a real filtered signal. A second set of capacitors receives an imaginary input signal and a real delayed signal, stores and shares electrical charges, and provides an imaginary filtered signal. A third set of capacitors receives the real and imaginary filtered signals, stores and shares electrical charges, and provides the real and imaginary delayed signals. In another design, a PSC filter implements a finite impulse response (FIR) section and an IIR section for a complex first-order IIR section. The IIR section includes multiple complex filter sections operating in an interleaved manner.

Abstract: The invention relates to techniques for implementing high-speed precoders, such as Tomlinson-Harashima (TH) precoders. In one aspect of the invention, look-ahead techniques are utilized to pipeline a TH precoder, resulting in a high-speed TH precoder. These techniques may be applied to pipeline various types of TH precoders, such as Finite Impulse Response (FIR) precoders and Infinite Impulse Response (IIR) precoders. In another aspect of the invention, parallel processing multiple non-pipelined TH precoders results in a high-speed parallel TH precoder design. Utilization of high-speed TH precoders may enable network providers to for example, operate 10 Gigabit Ethernet with copper cable rather than fiber optic cable.

Abstract: Aspects provide discrete-time analog, digitally programmable filtering. A filter includes a plurality of transistors coupled as a current mode circuit. Further included is a switch for use in switching the plurality of transistors in and out to tune the current mode circuit, wherein adjustable low bandwidth filtering using small silicon area without passive components is achieved.

Abstract: A digital system has a memory configured to hold operands and a multiply-shift unit coupled to the memory and configured to receive a first operand and a second operand from the memory in parallel, wherein the first operand includes a concatenated encoded shift amount. The multiply-shift unit includes a multiplier configured to receive the first operand after being separated from the concatenated encoded shift amount and to form a quotient from the two operands. A shifter is coupled to receive the quotient and to shift the quotient by an amount indicated by the encoded shift amount and to thereby form a shifted quotient on an output of the multiply-shift unit.

Abstract: A filter apparatus for filtering a time domain input signal to obtain a time domain output signal, which is a representation of the time domain input signal filtered using a filter characteristic having an non-uniform amplitude/frequency characteristic, comprises a complex analysis filter bank for generating a plurality of complex subband signals from the time domain input signals, a plurality of intermediate filters, wherein at least one of the intermediate filters of the plurality of the intermediate filters has a non-uniform amplitude/frequency characteristic, wherein the plurality of intermediate filters have a shorter impulse response compared to an impulse response of a filter having the filter characteristic, and wherein the non-uniform amplitude/frequency characteristics of the plurality of intermediate filters together represent the non-uniform filter characteristic, and a complex synthesis filter bank for synthesizing the output of the intermediate filters to obtain the time domain output signal.

Abstract: Methods and apparatus to perform string matching for network packet inspection are disclosed. In some embodiments there is a set of string matching slice circuits, each slice circuit of the set being configured to perform string matching steps in parallel with other slice circuits. Each slice circuit may include an input window storing some number of bytes of data from an input data steam. The input window of data may be padded if necessary, and then multiplied by a polynomial modulo an irreducible Galois-field polynomial to generate a hash index. A storage location of a memory corresponding to the hash index may be accessed to generate a slice-hit signal of a set of H slice-hit signals. The slice-hit signal may be provided to an AND-OR logic array where the set of H slice-hit signals is logically combined into a match result.

Abstract: Techniques for filtering noisy estimates to reduce estimation errors are described. A sequence of input values (e.g., for an initial channel impulse response estimate (CIRE)) is filtered with an infinite impulse response (IIR) filter having at least one coefficient to obtain a sequence of output values (e.g., for a filtered CIRE). The coefficient(s) are updated based on the sequence of input values with an adaptive filter, a bank of prediction filters, or a normalized variation technique. To update the coefficient(s) with the adaptive filter, a sequence of predicted values is derived based on the sequence of input values. Prediction errors between the sequence of predicted values and the sequence of input values are determined and filtered to obtain filtered prediction errors. The coefficient(s) of the IIR filter are then updated based on the prediction errors and the filtered prediction errors.

Abstract: A method of computing a vector angle by using a CORDIC and an electronic apparatus using the same are disclosed. The electronic apparatus mainly includes a phase error detector, a loop filter, a small-area iteration LUT module and a phase compensation circuit. The phase error can be locked by using the error function in the phase error detector, and even the phase error can be locked to the minimum so that the error oscillates up-and-down about the zero level. The first transfer function in the loop filter can determine the baseband and the converging speed. Moreover, if the shifting technique is used, the operation of the first transfer function is speeded up. By using a phase-locking loop in association with looking up the above-mentioned LUT, the method is able to get fast converging and higher accuracy for the computation.

Abstract: If K=4N, wherein K is a number of subbands and N is a decimation ratio, an analysis filter process unit 21 is used to perform an analysis filter process for every N samples of real-valued input data and output K samples of real-valued data. A GDFT/SSB modulation batch process unit (81) performs a GDFT process and an SSB modulation process on the outputted data by using a real-valued matrix calculation using a (K/2)×K real-valued matrix to output 1 sample×(K/2) channel of real-valued subbands data. Moreover, an SSB demodulation/inverse GDFT batch process unit (82) performs an SSB demodulation process and an inverse GDFT process on 1 sample×(K/2) channel of real-valued subbands data by a real-valued matrix calculation using a K×(K/2) real-valued matrix and outputs K samples of real-valued data. The outputted data is subjected to a synthesis filter process by a synthesis filter process unit (24) to output N samples of real-valued data.

Abstract: A method serves to process output signal of a measuring transducer in a force-measuring device, in particular in a balance, wherein the measuring transducer produces a measuring signal representative of a load acting on the device and the measuring signal is filtered in a variable analog filter and/or, after processing in an analog/digital converter, the measuring signal is filtered in a variable digital filter, in order to remove unwanted signal components that are caused by disturbances affecting the force-measuring device, in particular by changes in the weighing load.

Abstract: The digital delta-sigma modulator includes a signal input for receiving digital samples of N bits, and a digital filter connected to the signal input. The digital filter performs addition/subtraction and integration operations according to a redundant arithmetic coding for delivering digital filtered samples. A quantizer performs a nonexact quantization operation so as to deliver digital output samples of n bits, with n being less than N. The input of the quantizer is connected within the digital filter.

Abstract: In an IIR digital filter, for example, a multi-input multiplier/adder circuit is used as a component in place of a plurality of multipliers and a plurality of adders. With this omission of a plurality of multipliers and a plurality of adders, the circuit size can be reduced. Also, since the multi-input multiplier/adder circuit permits pipelining for increasing the processing speed in feedback processing, filter processing can be performed at high speed.

Abstract: Provided is a filter coefficient calculation method that calculates filter functions, each having (2n+1) rows and (2n+1) columns (n is an integer), the method including calculating a first filter function in accordance with a set value that is externally input, calculating an error between a total sum of values included in the first filter function and an ideal value of the total sum, supplying an odd error included in the error to a first origin coefficient that is located at a center of the first filter function as a first correction value if the error is an odd number, and supplying an even error to one of the first origin coefficient and a coefficient pair that is located symmetrically with respect to a point of the first origin coefficient as a second correction value, the even error being the error except the odd error.

Abstract: A method and apparatus for a receive equalizer of a gigabit transceiver that is reconfigurable to support multiple communication standards. Communication standards having variable common mode and coupling requirements are accommodated through the use of reconfigurable integrated circuits (ICs), such as field programmable gate arrays (FPGAs), that provide a plurality of reconfigurable transceivers that are programmable through configuration, or partial reconfiguration, events. The reconfigurable transceivers apply internally generated common mode voltage signals to the differential input in support of the various communication standards.

Abstract: A signal processing method, receiver and equalizing method are provided. The receiver comprises an estimator estimating a channel coefficient matrix from a received signal, a first calculation unit determining a channel correlation matrix based on the channel coefficient matrix a converter converting the channel correlation matrix into a circulant matrix. A second calculation unit determines equalization filter coefficients by applying a first transform to the real parts of a first subset of the terms in the first column of the circulant matrix and by applying a second transform to the imaginary parts of a second subset of the terms in the first column of the circulant matrix. An equalizer equalizes the received signal by using the determined equalization filter coefficients.

Abstract: A channel equalizer, method and computer program for equalizing a channel. The channel equalizer may include a feed forward filter and a switching unit. The switching unit may receive a signal input to the channel equalizer and an output signal from the feed forward filter, and may supply one of the input signal and output signal as an input to the feed forward filter.

Abstract: A method of data processing. The method comprises applying a filter to an input sample set comprising sample values selected from an input sequence of input sample values, so as to generate a corresponding output sample value having an output sample value position with respect to the input sample set, in which the filter has a maximum output range. The method further comprises deriving a permissible output value range from an input group of two or more input sample values in the input sample set which surround the output sample value position, detecting whether the output of the filter is outside the permissible output value range and, if so, limiting the output of the filter to lie within the permissible output value range.

Abstract: A method and system for the design and implementation of filters is presented in which the filter's transfer function can be provided with a significant insensitivity to the filter's tap coefficient values. A desensitized digital filter includes a first halfband filter and a second filter coupled in cascade between an input of the digital filter and the output of the digital filter. In embodiments, the first filter has the transfer function F(z)=K(1+z?1)(1+z?1) wherein K?0 is a scale factor. The digital filter may also interact with an up-sampler or a down-sampler. A desensitized Hilbert transformer includes an FIR filter having filter-tap coefficients whose absolute values equal the absolute values of the coefficients of an FIR filter F(z) for which the product (1+z?1)F(z) is a halfband filter coupled in cascade with a second filter.

Abstract: A signal processing device includes a converting unit, a filtering unit, a differential computing unit, and a phase difference computing unit. The converting unit samples two alternating signals with a predetermined period and converts the sampled level values into digital alternating signal data. The filtering unit filters the two digital alternating signal data generated by the converting unit so as to abstract digital alternating signal data having a predetermined frequency, and the filtering unit comprises an adaptive digital filter. The differential computing unit computes differentials of the digital alternating signal data generated by the filtering unit. The phase difference computing unit computes phase difference using the two digital alternating signal data generated by the filtering unit, and the two digital alternating signal data generated by the differential computing unit.

Abstract: A flexible engine for implementing digital signal processing (DSP) functions involving repeating various arithmetic/logical operations on a stream of data includes multiple programmable filter elements, at least one of which includes a microcode control program for internal control of the programmable filter element. The engine also includes programmable interconnection logic coupled to the programmable filter elements for selectively combining, scaling, and accumulating output values from the first plurality of programmable filter elements and selectively providing accumulated values as inputs to the first plurality of programmable filter elements. A filter controller coupled to the programmable filter elements and the programmable interconnection logic includes its own microcode control program for external control of the programmable filter elements and the programmable interconnection logic. Multiple engines can be combined to form larger, more powerful engines.

Abstract: A method for preprocessing a signal, wherein an iterative process with at least one iteration is performed to generate an output signal based on an input signal. In each iteration a preceding intermediate output signal and the input signal is received. A process is applied to the preceding intermediate output signal to transform the latter according to a given transfer function so as to generate a transformed preceding intermediate output signal. Then, the input signal is subtracted from the transformed intermediate output signal. Thereby, an intermediate error signal is generated and then added to the intermediate output signal so as to generate a succeeding intermediate output signal which is used as an output signal after the iterative process stopped.

Abstract: A method is disclosed for providing a digital filter system for providing a low pass filter function to a digital input. The method includes the steps of determining a finite impulse response of the input, determining a transfer function of the finite impulse response and providing a polynomial, identifying a plurality of stopband roots of the polymonial that lie in a complex plane, identifying real and complex conjugate pairs for the plurality of stopband roots, and providing coefficients for a complex polynomial that realizes the real and complex conjugate pairs such that a plurality of adjusted stopband roots lie on a unit circle of said complex plane.

Abstract: A method comprising the steps of: providing a known sequence comprising a plurality of data points; and curve-fitting the plurality of data points to calculate coarse frequency offset.

Abstract: A digital all-pass filter has an input port leading to an input sum block and a first feed forward path. Within the first feed forward path is a multiplier. The filter also has an output port coupled to an output sum block that receives a signal from the first feed forward path. A first feedback path is also provided from the output port to the input sum block. The first feedback path includes a multiplier therein. Nested within this structure is a first order all-pass filter having a feed forward path including a forward path delay and forward path that is delayed and a feedback path absent a separate delay element and beginning after the forward path delay element.

Abstract: Recursive digital filter circuitry which avoids persistent unstable conditions therein provides a serial clock signal, a synchronization signal, and a serial data input to corresponding inputs of a 3-wire serial interface circuit to produce a serial clock output signal, a synchronization output signal, and a parallel data output signal which are applied to corresponding inputs of a recursive digital filter. The serial clock signal and the synchronization signal are input to an auto-reset circuit which detects a fault associated with the synchronization signal or the serial clock signal and produces a reset signal in response to detection of the fault for resetting the recursive digital filter.

Abstract: A channel-select decimation filter capable of operating in multiple bandwidth modes includes a first low pass filter stage, a variable gain stage, a subtraction module a second low pass filter stage and a down-sampling module. The first low pass filter stage includes a first programmable delay module for filtering input signals to produce first low pass filtered signals. The variable gain stage applies a programmable gain to the input signals to produce gained input signals. The subtraction module subtracts the first low pass filtered signals from the gain input signals to produce first stage signals. The second low pass filter stage includes a second programmable delay module for filtering the first stage signals to produce channel-selected signals. The first programmable delay module, second programmable delay module and programmable gain are programmed to implement one of the multiple bandwidth modes.

Abstract: A method for data processing includes transforming measurement data acquired in the time domain during an oilfield operation into a second domain to produce transformed data; identifying distortions in the transformed data; removing the distortions from the transformed data; and transforming back from the second domain to the time domain to produce cleaned-up data. The transforming measurement data may use a Fourier transform or a wavelet transform. The method may further include compressing the cleaned-up data or reconstructing signals from the cleaned-up data. A method for data processing includes decomposing measurement data, which are acquired in an oilfield operation, using a low pass filter to produce a first dataset; decomposing the measurement data using a high pass filter to produce a second dataset; removing distortions from the second dataset to yield a corrected second dataset; and reconstructing a corrected dataset from the first dataset and the corrected second dataset.

Abstract: An apparatus comprising an address generation circuit, a lookup table, a multiplexer and an output circuit. The address generation circuit may be configured to generate a series of addresses. The lookup table may be configured to generate one or more coefficients in response to the addresses. The multiplexer circuit may be configured to generate one or more shifted values in response to (i) the coefficients and (ii) the one or more operands. The output circuit may be configured to generate an output signal by combining one or more component values in response to said shifted values. The coefficients are grouped as one over power of 2 components into mutually exclusive groups.

Abstract: Methods and apparatuses in which a first stage of a digital filter receives input data to be filtered, the first stage of a digital filter operating at a first clock; a second stage of the digital filter outputs filtered output data, the second stage of the digital filter operating on a second clock, wherein a ratio of a frequency of the first clock and a frequency of the second clock is a fractional number, and a frequency of the second clock is higher than a frequency of the first clock; the first stage receives an indication of a ratio of the first clock and the second clock; and the first stage receives an indication of a time offset between (1) a clock pulse of the second clock, which occurs between a first clock pulse and a second clock pulse of the first clock, and (2) the first clock pulse of the first clock.

Abstract: A method of prediction is suggested for the characteristics of future values of processes that can be expressed as integrals over future times with different weight functions (kernels), or as anticausal convolution integrals. In particular, all band-limited processes processes are predictable in this sense, as well as high-frequency processes, with zero energy at low frequencies. In addition, process of mixed type can still be predicted using low-pass filter and high-pass filter for this process, to provide separation on low-band and high frequency processes. It is allowed that an outcome of low-pass filter be not a purely band-limited process, but have exponential decay of energy on high frequencies. The algorithm suggested consists of two blocks: separation of a process on band-limited and high-frequency components, and approximation of the transfer function of the anticausal integral that has to be predicted by transfer functions for causal convolution integrals.

Abstract: An nonlinear digital signal processing filter (100, 200, 1100, 1308, 1310, 1312, 1346, 1604) maintains a magnitude ordering for successive windows of signal samples. A set of filter density generator values [f1, f2, f3 . . . fj . . . fndensities] are used according to the ordering in a recursion relation that computes successive values of a set function over the set of filter density generator values. The recursion relation involves an adjustable nonlinearity defining parameter ?. The values are normalized by dividing by a largest of the values, and differences between successive values are taken. An inner product between each window of signal values (used in order according to magnitude) and the adaptive differences is a filtered signal sample.

Abstract: A bit selection circuit that arbitrarily selects, from among (2n) input bits, (2n?1) continuous output bits in the input bit arrangement (where n?3), includes: a first multiplexer selecting {(2n?2)?(20+21+ . . . +2n?3)} continuous bits in the input bit arrangement from among (2n?2) input bits, excluding two first and (2n)th input bits at both ends in the input bit arrangement, in accordance with an input first control signal; and a second multiplexer selecting (2n?1) continuous output bits in the input bit arrangement from among the {(2n?2)?(20+21+ . . . +2n?3)} bits selected by the first multiplexer, the first input bit, and the (2n)th input bit in accordance with an input second control signal.

Abstract: The present invention relates to methods and systems for signal filtering in electronic devices and more particularly, some embodiments related to methods and systems for filtering of radio frequency (RF) signals. In some embodiments, a filter circuit may comprise a down-converter, a filter, coupled to the down-converter and configured to filter the down-converted signal, and an up-converter, coupled to the filter. Various embodiments might also include a combining circuit, coupled to the up-converter and configured to combine the filtered, up-converted signal and the input signal.

Abstract: An instruction-based parallel median filtering processor and method sorts in parallel each combination of pairs of inputs into greater and lesser values; determines from that sorting the minimum, maximum and median filter values of the inputs; processes one of those values and provides the processed value as an input; and applies an instruction for providing one of the values to the processing step, and at least one other instruction for enabling indication of at least one of the maximum, minimum, median filter values.

Abstract: Provided is a discrete signal finite impulse response (FIR) filter and a filter set in which a plurality of FIR filter units are connected in a cascade structure to remove down-sampling by decimation, in order to improve the attenuation characteristics of a FIR filter, such as, for example, a switched capacitor filter. The FIR filter includes a clock generator generating a plurality of clock signals that are different from each other; and N+2 sub blocks each including N sample storage units, each sample storage unit storing a received sample. Each sub block being in a state among a number of possible states including N charging states for storing the received sample, a transfer state for outputting the stored sample and a reset state for operation initialization. The N charging states, the transfer state and the reset state are changed sequentially in response to the clock signals.

Abstract: A signal is filtered by multiplying its Fourier transform by the Fourier transform of a reference sequence to which the filtering is to be matched. The reference sequence (e.g. a Golay sequence pair) is defined as an iterative combination of shorter sequences and its Fourier transform is generated by an iterative process of combining the Fourier transforms of a shorter starting sequence.

Abstract: A receiver architecture for receiving an FSK signal having a predetermined number of modulation levels includes a selectivity filter (206) for selectively passing a wanted channel and rejecting unwanted channels. The selectivity filter has a filter bandwidth of about one-half the bandwidth of a pre-modulation filter in a transmitter sending the FSK signal. A discriminator (208) is coupled to the selectivity filter for demodulating the signal. A symbol recovery processor (210) is coupled to the discriminator for recovering the symbols through a maximum likelihood sequence estimation (MLSE) technique utilizing N states for each symbol time, wherein N equals the predetermined number of modulation levels, and wherein templates used in the MLSE for symbol transitions are optimized with a bandwidth substantially less than the bandwidth of the pre-modulation filter.