Abstract: A NICAM encoder (54) comprises a NICAM processor (82) and a front-end section (80,84) coupled to the NICAM processor. The front-end section is configured for operating with a system clock (68) that is integer divisible such that the system clock can be used by both the NICAM processor (82) and the front-end section (80,84).
Type:
Grant
Filed:
April 29, 2005
Date of Patent:
September 19, 2006
Assignee:
Freescale Semiconductor, Inc.
Inventors:
Luciano Zoso, Allan P. Chin, David P. Lester
Abstract: A computation core includes a computation block, an addressing block and an instruction sequencer, which are coupled to a memory through a memory interface. The computation block includes a register file and dual execution units. The execution units include features for enhanced performance in executing digital signal computations. The computation core is configured for executing digital signal processor instructions and microcontroller instructions, while achieving efficient digital signal processor computation and high code density. A finite impulse response filter algorithm achieves high performance on the dual execution units.
Abstract: An n-bit shift register 102 for shifting input data through successive bit stages and AND gates 103-i (i being 1 to n) corresponding to the bit stages of the shift register 102 are provided. A control circuit 101 feeds out control signals 107-i for on-off controlling the feeding of the outputs of the corresponding bit stages of the shift register 102. Multipliers 104-i multiply the on-off controlled data and predetermined filter coefficient data, and an adder circuit 105 adds together the output of the multipliers to derive an FIR filter output including ramp-up and -down. A ramp-up/-down signal is fed to a shift register in the control circuit 101, and ramp-up data is derived from the output of the adder circuit 105. Thus, the circuit can be readily constructed without scale increase.
Abstract: A device for filtering electrical signals has a number of inputs arranged spatially at a distance from one another and supplying respective pluralities of input signal samples. A number of signal processing channels, each formed by a neuro-fuzzy filter, receive a respective plurality of input signal samples and generate a respective plurality of reconstructed samples. An adder receives the pluralities of reconstructed samples and adds them up, supplying a plurality of filtered signal samples. In this way, noise components are shorted. When activated by an acoustic scenario change recognition unit, a training unit calculates the weights of the neuro-fuzzy filters, optimizing them with respect to the existing noise.
Type:
Grant
Filed:
August 27, 2003
Date of Patent:
August 1, 2006
Assignee:
STMicroelectronics S.r.l.
Inventors:
Rinaldo Poluzzi, Alberto Savi, Giuseppe Martina, Davide Vago
Abstract: An arrangement is provided for using 2's complement arithmetic without the high switching activity of the prior art. In particular, the invention operates to exploit the sign-extension property of a 2's complement number. A reduced representation for 2's complement numbers is provided to avoid sign-extension and the switching of sign-extension bits. The maximum magnitude of a 2's complement number is detected and its reduced representation is dynamically generated to represent the signal. A constant error introduced by the reduced representation is also dynamically compensated.
Abstract: A method and apparatus for generating random number outputs utilized in generating a noise function at a given location in space. The method consists of partitioning selected portions of the random number generation process to achieve outputs in parallel. The relevant parallel outputs are weighted by effect and then summed together to give the amplitude of the noise function at the given location.
Type:
Grant
Filed:
August 8, 2001
Date of Patent:
July 4, 2006
Inventors:
Stephen Clark Purcell, Scott Kimura, Rajeshwaran Selvanesan
Abstract: A complex multiplier is described for filtering a signal in the frequency domain. In one embodiment, additional, independent frequency coefficients are supplied by the complex multiplier so that gain and/or phase of the signal may be independently modified (i.e., gain may be modified without affecting phase and vice-versa).
Abstract: A signal processing device includes a biorthogonal filter bank that processes a finite length signal including a left boundary and a right boundary. The biorthogonal filter bank includes an analysis filter bank. The analysis filter bank includes one or more left boundary filters, one or more right boundary filters, and one or more steady-state analysis filters. Each left boundary filter and each right boundary filter includes a row vector.
Abstract: A graphametric equalizer has graphic and parametric equalization capabilities within a single non-redundant system. A translation function capability converts user selected inputs for center frequency, bandwidth and gain into allpass filter parameters to realize an allpass filter-based equalization filter structure capable of performing graphic and/or parametric equalization on-the-fly. The graphametric equalizer has a softening function capability to time user inputs and increment filter parameters gracefully such that the graphametric equalizer can be recharacterized with new filter parameters on-the-fly without incurring undesirable audible artifacts.
Abstract: A video compression and decompression system has an input to receive an encoded video sequence and an output for a decoded video sequence. A video decoder is coupled to the input and decode the received encoded video sequence. A filter module is coupled to the video decoder and the output and filters the decoded video sequence from the video decoder. The filter module has a variable filter strength that is a function of detected motion activity within the video sequence. The filter module filters coding artifacts, such as mosquito artifacts and blocking artifacts from the decoded video sequence so that the displayed video is more pleasing for a viewer's eyes.
Abstract: A digital group delay compensation system comprising a digital allpass filter that is utilized in an implementation phase; and a system that generates coefficients for the allpass filter used in the implementation phase such that the overall performance of a system is measured and optimized in a calibration phase.
Abstract: A process and method for projection beam lithography which utilizes an estimator, such as a Kalman filter to control electron beam placement. The Kalman filter receives predictive information from a model and measurement information from a projection electron beam lithography tool and compensates for factors which cause beam placement error such as wafer heating and beam drift. The process and method may also utilize an adaptive Kalman filter to control electron beam placement. The adaptive Kalman filter receives predictive information from a number of models and measurement information from a projection electron beam lithography tool and compensates for factors which cause beam placement error such as heating and beam drift. The Kalman filter may be implemented such that real-time process control may be achieved.
Abstract: A method and a device are described for filtering a variable. A first filtering arrangement is used for forming an output variable as a function of an input variable, the first filtering arrangement having at least a delaying effect. The input variable of the first filtering arrangement is corrected using a correcting variable which is obtained by starting from the input variable of the first filtering arrangement and by filtering, using a second filtering arrangement.
Abstract: A method, apparatus, and computer program product for combining a subband decomposition and a linear signal processing filter (LSPF). Operations performed include merging the LSPF, via superposition, with each synthesis filter of the first level of the subband decomposition into a set of composite filters; generating an equivalent structure for the low-pass composite filter and its adjacent upsampler to allow combining the equivalent structure with the synthesis filter on the next level of the subband decomposition; repeatedly operating the merging on the next level of the subband decomposition; creating an equivalent structure for the intermediate structure generated by the merging step and its adjacent upsampler in order to allow for combination of the equivalent structure with the at least one synthesis filter on the next level; repeating the operations for each remaining level to generate a composite subband synthesis linear operator, which operates directly on data of the subband decomposition.
Abstract: The present invention relates to a filter bank approach to adaptive filtering method using independent component analysis. More particularly, the invention relates to a method of improving the performance of adaptive filtering method by applying independent component analysis that is capable of reflecting the secondary or even higher order statistical characteristics to adaptive filtering algorithm using the filter bank approach. In order to implement the conventional adaptive filter algorithm using independent component analysis to the real world problem, a large number of filter training coefficients are required and also a large amount of calculation is required when a training is undertaken. This results in a very slow learning speed and the deterioration in the quality of result signals.
Type:
Grant
Filed:
January 31, 2003
Date of Patent:
May 9, 2006
Assignees:
Korea Advanced Institute of Science and Technology, Extell Technology Corporation
Abstract: An equalizer and an equalization method capable of suppressing distortion specific to radio unit and reducing both the oversampling number and the amount of calculations without causing characteristic deterioration.
Abstract: Efficient reconstruction of a discrete signal in a range from subband coefficients of multirate analysis filtering translates the range into required input coefficient ranges and minimizes computation and memory access.
Abstract: A method is provided of slewing a bandwidth characteristic of a digital filter within a range between a first bandwidth characteristic and a second bandwidth characteristic. The digital filter includes a plurality of cascaded filter sections, each filter section being comprised of a second order filter having coefficients a1, a2, b0, b1, and b2. An index value is determined for identifying a desired bandwidth characteristic within the range. Values are interpolated for the coefficient values for the a1 and a2 coefficients of a respective filter section in response to the index value. Coefficient values are derived for the b0, b1, and b2 coefficients in response to the coefficient values for the a1 and a2 coefficients such that the b0, b1, and b2 coefficient values provide a matched gain for the respective filter section. The coefficient values are loaded into the respective filter section.
Type:
Grant
Filed:
April 15, 2002
Date of Patent:
April 25, 2006
Inventors:
Sunil Shukla, Mark W. Corless, J. William Whikehart
Abstract: The invention provides for improved signal to noise ratios in evaluation techniques. This is done by acquiring a signal, processing it to obtain a complex form thereof, obtaining a filtering factor from the complex form and processing the acquired signal with the filtering factor. The signal may be areturned ultrasonic, radar or sonar signal which may be reflected from a suitably sharp pulse. In particular, the invention may he used to evaluate articles to detect defects therein. In a preferred form, the complex form is filtered with a number of complex filters and the phases of the complex filtered signals determined. These phases are then used to provide the filtering factor.
Abstract: Disclosed is a digital sampling rate converter for compensating for a drop of an in-band signal, the digital sampling rate converter including a CIC (Cascaded Integrator-Comb) decimator for performing a decimation operation at a first decimation ratio based on an overall decimation ratio, for an input signal; a sub-decimator for performing a decimation operation at a second decimation ratio for a signal output from the CIC decimator; and a compensation unit for performing at least two multiplication operations and two addition operations with respect to a signal output from the sub-decimator using a lowest operation clock frequency in an assigned band.
Abstract: A method and apparatus for estimating a state parameter in a nonlinear discrete time system are provided. The method for estimating a state parameter has the steps of (a) predicting a state parameter at a current time using an estimated state parameter at a previous time and a system dynamics; and (b) estimating an optimal state parameter at the current time from the state parameter predicted in the step (a) and a system output parameter measured at the current time, using a geometric data fusion method. Since the method and apparatus for estimating a state parameter have an excellent estimation performance particularly when nonlinearity is great or the error in an estimated initial value is big, the method and apparatus solve many problems, which cannot be solved by the conventional extended Kalman filter, and more improve the performance of estimating a state parameter, by analyzing the system characteristic and then appropriately utilizing constraints such as the operation range of the state parameter.
Abstract: The FIR filter separately receives input data consisting of transmitting information and composed of bit strings, and additional data which is added in order to transmit the input data. The input data is operated with the additional data. A difference between the additional data corresponding to previous data (for instance, most recent data) among the input data and the additional data corresponding present data is obtained, and the difference and the previous data are operated. Then, the operation results are added and the resultant is outputted as a filter response. The input data and the additional data are separately received to be operated so that the circuit scale of the filter is reduced. Therefore, a chip of the semiconductor integrated circuit can be downsized and thereby cost reduction in the communication system can be realized.
Abstract: A method and system for performing joint equalization and decoding of Complementary Code Key (CCK) encoded symbols. The system comprises: a decision feedback equalizer (DFE) structure for simulating an inverse communications channel response and providing an output comprising an estimation of the received symbols, the DFE structure including a forward equalizer path and a feedback equalizer path including a feedback filter; and, a CCK decoder embedded in the feedback path and operating in conjunction with a feedback filter therein for decoding the chips based on intermediate DFE outputs including those chips corresponding to past decoded CCK symbols. Decisions on a symbol chip at a particular time are not made until an entire CCK codeword that the chip belongs to is decoded, thereby reducing errors propagated when decoding the symbols. Advantageously, the trellis decoding method is implemented as a computationally efficient 64-state trellis.
Abstract: A wireless communication device processes N Radio Frequency (RF) bursts contained within N slots of a digital communications time divided frame, wherein N is a positive integer greater than one. The wireless communication device includes an RF front end, a baseband processor, and an equalizer module. The RF from end is operable to receive the plurality of received RF bursts and to convert the RF bursts to corresponding baseband signals. The baseband processor operably couples to the RF front end, is operable to receive the baseband signals, is operable to pre-equalization process the baseband signals to produce processed baseband signals, and is operable to post-equalization process soft decisions. The equalizer module operably couples to the baseband processor and is operable to equalize the processed baseband signals to produce the soft decisions. These RF bursts may be contained in adjacent slots or, in non-adjacent slots, or in a combination of adjacent slots and non-adjacent slots.
Type:
Grant
Filed:
December 9, 2003
Date of Patent:
April 11, 2006
Assignee:
Broadcom Corporation
Inventors:
Baoguo Yang, Li Fung Chang, Zhijun Gong
Abstract: A system and method for improving the performance of digital filters. The data bandwidth and spectral control are improved by adaptively selecting ramp-up and ramp-down symbols based on the actual filtered data. Thus, the energy in the truncated tail of the filter is minimized for a given filter design. The invention is of particular utility in systems that filters intermittent data streams, thus requiring the filter to energize and deenergize repeatedly.
Abstract: A method, apparatus, and a computer program product for generating a set of jointly optimized linear signal processing filters and subband filters for processing digital data on a computer system are presented. In general, the invention performs the operations of determining a design scheme for at least one linear signal processing filter; determining a design scheme for at least one subband filter; and relating the design schemes for the at least one linear signal processing filter and the at least one subband filter in order to determine a relationship therebetween. The relationship provides criteria for optimization (e.g. maximizing data compression while minimizing processing requirements). Next, the design schemes are jointly adjusted using the relationship to optimize the criteria for optimization and generates an optimized linear signal processing filter/subband filter set to provide improved data processing performance.
Abstract: A receiver for improving the performance of conventional Discrete Multitone Modulation (DMT) based Asymmetric Digital Subscriber Line (ADSL) modems, in the presence of noise and/or interference. A demodulator having an FFT followed by a single-tap-per-bin frequency-domain equalizer is augmented by an additional data-path utilizing windowing or pulse shaping. Windowing is done independently for each symbol over the orthogonality interval and efficiently in the time domain or frequency domain. A decision feedback equalizer at the output of the windowed data-path cancels inter-bin-interference created by windowing.
Abstract: A method and system for equalizing a signal transmitted via a channel of a communications system stores an input signal received via the channel in a main buffer. A training signal portion of the received input signal is stored in a circular buffer as a circulating training signal. A mean square error of the training signal is minimized while estimating the transmitted signal, until the mean square error is less than a predetermine threshold. In this case, the input signal received via the channel is equalized directly to make decisions on symbols of the signal transmitted via the channel. During an initial stage of training, the mean square error is determined directly from the training signal, during subsequent stages of training the circulating training signal is used.
Type:
Grant
Filed:
February 14, 2002
Date of Patent:
March 21, 2006
Assignee:
Mitsubishi Electric Research Laboratories, Inc.
Inventors:
Jyhchau Horng, Jinyun Zhang, Philip Orlik
Abstract: The present invention provides a speech feature extraction system suitable for use in a speech recognition system or other voice processing system that extracts features related to the frequency and amplitude characteristics of an input speech signal using a plurality of complex band pass filters and processing the outputs of adjacent band pass filters. The band pass filters can be arranged according to linear, logarithmic or mel-scales, or a combination thereof.
Abstract: A method for reducing computational time for calculating a noise-filtered average approximation of a throttle position in an automotive environment. During controller initialization, an initial average value for N samples is established by conventional averaging. The sum obtained is retained for future use as a previously-retained sum. When an updated average value is required, the oldest sample value and the last output calculation are both subtracted from the previously-retained sum, and the newest sample value is added twice to the previously-retained sum, as well as being stored in sequence in the buffer. The new sum is then divided by the number of sample values to obtain a new noise filtered average approximation of throttle position, which again is retained for use in the next update. The new output value obtained by the throttle position sensor is weighed more heavily to decrease the deviation from the average approximation of throttle position.
Abstract: The ratio of useful-signal power to the power of interference signals at an antenna (ANT) having plural sensors, and at least one sensor is obtained by filtering the antenna output signal with a filter having a transfer function (W(t), W(t, f)) equal to the ratio of two linear functions of the power ({circumflex over (p)}y(t), {circumflex over (p)}y(t, f)) at the output of the antenna to the power {circumflex over (p)}x(t), {circumflex over (p)}x(t, f)) at the input of the antenna (ANT).
Abstract: An image is picked up through sampling in a predetermined sampling pattern to acquire an image signal representing the image. Sampling information, which concerns the predetermined sampling pattern, is appended to the image signal, which has been acquired. The sampling information is information for discriminating checkered sampling and square sampling from each other. Different sharpness enhancement processing is performed on the image signal and in accordance with the sampling information to obtain a processed image signal. The different sharpness enhancement processing may be a processing in accordance with frequency characteristics of the image signal, which has been acquired, due to the sampling pattern.
Abstract: An area-efficient realization of a coefficient block includes hardware sharing techniques and optimizations applied to this block. The block is connected to coefficient lines coming from a delay block to be connected to perform a filtering operation or a mathematical computing operation with optimization in hardware and provides a zero latency output. The coefficient block also enables an area minimal realization of digital filters based on the coefficient block, when operated in serial bit fashion. The optimization techniques and structure are good for bit-serial digital filters typically a finite impulse response (FIR) filter, including finite impulse response filter (IIR) and for other filters and applications based on combinational logic that includes delay elements, multipliers, and serial adders and/or subtractors.
Type:
Grant
Filed:
October 13, 1998
Date of Patent:
February 28, 2006
Assignee:
STMicroelectronics Asia Pacific (Pte) Ltd.
Abstract: Systems and methods are disclosed herein to provide low pass filters. For example, in accordance with an embodiment of the present invention, a synchronous low pass filter is disclosed. The filter may be employed, for example, to suppress signal transients in power supply monitoring applications.
Abstract: A non-uniform filter bank is created by joining sections of oversampled uniform filter bands that are based on complex exponential modulation (as opposed to cosine modulation). Each filter bank handles a given, non-overlapping frequency band. The bands are not of uniform bandwidth, and the filters of different banks have different bandwidths. The frequency bands of the different filter banks cover the frequency of interest with gaps in the neighborhoods of the filter band edges. A set of transition filters fills those gaps.
Abstract: A discretization processing method for transforming a transfer function in continuous time systems to a transfer function in discrete time systems is disclosed. To obtain the new transfer function, angular frequency ?a of the original transfer function in continuous time systems is transformed to angular frequency ?c using the bilinear z-transform of the inverse characteristic. In the discretion processing result, the equivalent characteristics of the original transfer function in continuous time systems can be obtained by performing the bilinear z-transform against the new transfer function in continuous time systems having been obtained by the angular frequency transformation of inverse characteristic.
Abstract: The present invention discloses a method for finding an optimized filter parameters design to meet input specifications and hardware constraints in accordance with a typical single channel digital IF programmable downconverter. Said typical single channel digital IF programmable downconverter comprises four stages, including a high speed down-sampling stage, a spectral shaping stage, a rate matching stage and an oversampling stage. According to input specifications, said method firstly determines a number of Halfband interpolation filters used in said oversampling stage, secondly obtains optimized parameters for a CIC decimation filter and a Halfband decimation filter in said high speed down-sampling stage, using as many Halfband decimation filters as possible. Then determine if it is necessary to use re-sampling FIR filter for rate matching.
Abstract: A method for deriving a polynomial for generating filter coefficients to be used in a digital filter in an electronic unit having a digital signal processor. The digital filter has a plurality of reconfigurable filter sections to achieve a desired bandwidth characteristic between a first characteristic with a first cutoff frequency and a second characteristic with a second cutoff frequency. A first set of filter coefficients is determined for providing the first characteristic. A second set of filter coefficients is determined for providing the second characteristic. A third set of filter coefficients is determined for providing a third characteristic having a third cutoff frequency between the first and second cutoff frequencies.
Type:
Grant
Filed:
April 15, 2002
Date of Patent:
January 17, 2006
Assignee:
Visteon Global Technologies, Inc.
Inventors:
Mark W. Corless, Sunil Shukla, J. William Whikehart
Abstract: A variable-gain digital filter includes a selector and multiplier arranged inside the digital filter for regulating gain whereby the number of bits of filter input is X, the number of flip-flops inside the filter is X×n bits, and a (Y×n bit) reduction in the number of flip-flops is enabled. The gain regulation circuit incorporated within the digital filter enables a reduction in circuit scale.
Abstract: A circuit generally comprising a first circuit and a second circuit. The first circuit may be configured to (i) detect a state of an input signal and (ii) present a plurality of intermediate signals each representative of the state of the input signal during a plurality of clock cycles. The second circuit may be configured to present a filtered signal in response to a selected number of the intermediate signals having a predetermined state.
Type:
Grant
Filed:
August 28, 2001
Date of Patent:
January 3, 2006
Assignee:
LSI Logic Corporation
Inventors:
Christopher D. Paulson, Steven A. Schauer
Abstract: Methods and systems for determining characteristics of a Finite Impulse Response system that can include applying a number of identical sets of probe signals to the system and averaging the observed outputs. A discrete Fourier transform (DFT) of the averaged outputs can be obtained and the DFT components can be multiplied by corresponding transformed companion components related to the probe components. The system characteristics can be selected based on computing the inverse DFT of the resulting product components. The probe components can be taken from a circulant matrix of size S×S, or from an inverse DFT of a set of transform components consisting of arbitrary, non-zero, real numbers for first and last components of a partial set and arbitrary, non-zero, complex numbers for other components of the partial set to which the non-zero, complex number components of the partial set are added in reverse order and in complex conjugate.
Abstract: A delay addressed data path register file is designed for use in a programmable processor making up a cell in a multi-processor or array signal processing system. The delay addressable register file is particularly useful in, inter alia, adaptive filters where the filter update latency is variable, interpolation filters where the interpolation factor needs to be programmable, and decimation filters where the decimation factor needs to be programmable. The programmability is achieved in an efficient manner, reducing the number of cycles required to perform this task. A single parameter, the “delay limit” value, is programmed at start-up, setting up an internal delay-line within the register file of the processor. Thus, any of the delayed registers can be addressed by specifying the delay index during run-time. The delay line advances one location, modulo “delay-limit”, when the processing loop starts a new iteration.
Abstract: A device for processing digital data. A module (M2, M3) produces on a data vector of the frequency domain Z(k), wherein K varies from 0 to N?1, a convolution with a function U, convolution which corresponds to a cancellation in the time domain of the samples of the inverse transform of Z(k). The function U is in the form: U(k)=sin c(k?k0/2.e)?j?(?(k?k0/2.P(k)), wherein K0 is a constant integer and P(k) a weighting window symmetrical about k0.
Type:
Grant
Filed:
August 5, 1999
Date of Patent:
November 22, 2005
Assignee:
France Telecom
Inventors:
André Gilloire, Wolfgang Tager, Valérie Turbin
Abstract: A method for finding optimal filter coefficients for a filter given an input data sequence and an objective function is disclosed. The method includes selecting a wavelet basis having k parameters and minimizes the k parameters according to the predetermined objective function. The wavelet basis is reparameterized into k/2 rotation parameters and factorized into a product of rotation and delay matrices. The k/2 rotation parameters are provided for the rotation matrices and a data transform matrix is computed based on the product of the rotation and delay matrices. The input data sequence is converted into transformed data by applying the data transform matrix to the input data. The Jacobian of the data transform matrix and the input data sequence is determined and multiplied by the gradient vector with respect to the transformed data of the objective function.
Abstract: A method for channel equalization of received data includes steps of: receiving the received data in a received data packet; calculating filter setting coefficients for an input filter and calculating equalizer setting coefficients for an equalizer; setting the input filter using the filter setting coefficients and setting the equalizer using the equalizer setting coefficients; equalizing the received data using the input filter and using the equalizer; determining channel parameters for the transmission channel from the received data Xk; storing the channel parameters in a data field; and performing the step of calculating the filter setting coefficients for the input filter and calculating the equalizer setting coefficients for the equalizer by performing a GIVENS rotation of the data field.
Abstract: The invention offers a method of calculating digital filters enabling to multiplex various different filters with the aid of a programmable co-processor circuit comprising a calculation element and memory registers. The invention comprises making an anticipated calculation of part of the result of the current filter before the last data included in the calculation of this result has arrived. For this purpose, successive products between predetermined filter coefficients and the corresponding input data which have already been used for the calculation of the preceding results are accumulated in an iterative fashion in an intermediate result in order to anticipate the calculation of the current result. The calculation of the last intermediate result for each final result is triggered each time a new input data is received, so that each filter result is immediately available once the last input data involved in this result has been received.
Abstract: An oversampled filter bank structure that can be implemented using popular and efficient fast filter banks to allow subband processing of an input signal with substantially reduced aliasing between subbands. Even subbands (SB0, SB2, SB4, . . . ) of an input signal (x(n)) are frequency-shifted (212, 1012, 1012?, 1012?) prior to analysis filtering (214, 214?, 214?) at a 2× oversampled filter bank, subband processing (240, 240?, 240?), and synthesis filtering (216, 216?, 216?). A subsequent frequency-shift (218, 218?) returns the even subbands to their original band positions. The odd subbands (SB1, SB3, SB5, . . . ) are delayed (252) to compensate for the processing time of the frequency shifting. Separate analysis (214, 214?) and synthesis (216, 216?) filter banks may be provided for the even and odd subbands, or common complex analysis (284) and synthesis (286) filter banks may be used. In another embodiment, the subbands are processed in four subband paths (Paths 0, 1, 2, 3), and 4× oversampling is used.
Abstract: For the offset compensation of a digital signal, particularly of a communication signal transmitted in a cordless digital communication system, a recursive digital filter is used. The recursive digital filter has at least one filter coefficient that is varied in a time-dependent manner. The recursive digitial filter has a first multiplying device multiplying symbols of the digital input signal by a first time-variable filter coefficient to obtain a digital output signal having symbols.
Abstract: A method for initializing an equalizer in an Orthogonal Frequency Division Multiplexing (“OFDM”) receiver includes generating a desired equalizer tap setting based on an adaptive algorithm. An initial setting for the adaptive algorithm corresponds to an approximate inverse of a channel estimate, and the desired tap setting corresponds to an ideal inverse of the channel estimate. In an alternative embodiment, a method includes generating a channel estimate, generating an equalizer tap setting based on a complex conjugate of the estimate and a quantized magnitude squared of the estimate, and repeatedly generating subsequent tap settings until an error falls within limits.
Type:
Grant
Filed:
September 18, 2001
Date of Patent:
September 13, 2005
Assignee:
Thomson Licensing S.A.
Inventors:
Maxim B. Belotserkovsky, Louis Robert Litwin, Jr.
Abstract: Implementations of a progressive two-dimensional pyramid filter bank are disclosed including a method of adding a first and a last input signal sample to a sum of input samples of a next lower-tap filter of a current filter to produce a sum of input signal samples for the current filter; and adding the sum of input signal samples for the current filter to an output signal sample of the next lower-tap filter of the current filter to produce an output signal sample for the current filter. In one implementation the first and second adding is performed by different adders. In another implementation the first and second adding is applied by column and by row.