Abstract: There is provided a transfer apparatus having a bridge that transfers a transaction between a first and a second bus, and a data transfer unit that performs a data transfer by DMA between the first and second bus. The transfer apparatus controls a transfer sequence of transaction transfers by the bridge and data transfers by the data transfer unit, in which transaction transfers by the bridge are based on bus sequencing rules and data transfers by the data transfer unit are based on a data transfer activation condition.

Abstract: A discussion of improving integrated device deterministic response to test vectors. For example, limiting the transmission delay for an integrated device's response within known bounds by synchronizing an initialization training sequence to a reset deassertion. Specifically, the proposal facilitates response determinism from the DUT by synchronizing training sequences and subsequently synchronizing flit transmission to reset assertion as sampled by reference clock.

Abstract: The present invention discloses a power management apparatus and method for devices comprising an interface module that includes receivers for receiving input signals from a device, an auto power management unit coupled with receivers for determining a state of the input signals, and outputting a power management signal based on the determined state of the input signal. Further provided is an electronic unit coupled with the auto power management unit for driving driver units, with the power management signal toggling ON/OFF a status of the electronic unit based on the determined state of the input signal to thereby reduce power utilization.

Abstract: A method for synchronizing a transmission of information over a bus, and a device having synchronization capabilities.

Abstract: An exclusion controller which allows an information processing unit to acquire a contended resource to the exclusion of the other information processing units includes a plurality of non-prioritized information processing units mutually exclusively acquiring a non-prioritized exclusion right, which indicates a candidate for acquiring the contended resource, by a first process. The exclusion controller further includes a prioritized information processing unit acquiring the contended resource by a second process, which requires a shorter processing time than the first process, to the exclusion of the non-prioritized information processing unit having acquired the non-prioritized exclusion right.

Abstract: A digital bit-level repeater for joining two wired-AND buses such as the I2C bus is described. A protocol detector is used for tracking clock and data signals to determine the direction of the transfer. A state machine reads and regenerates the clock lines of both buses and provides the clock-stretching protocol feature on both buses. The repeater is designed to pass data bits from one bus to the other transparently when possible, and to latch and hold each data bit until the receiving bus can be clocked when clock-stretching occurs or when the bus is turned around.

Abstract: An apparatus comprising a remote storage array, a primary storage array and a network. The remote storage array may be configured to (i) define a queue size based on a performance capability of the remote storage array, (ii) generate a multiplier based on resources being used by the remote storage array, and (iii) adjust the queue size by the multiplier. The primary storage array may be configured to execute input/output (IO) requests between the remote storage array and the primary storage array based on the adjusted queue size. The network may be configured to connect the remote storage array to the primary storage array.

Abstract: In a data communication system for communicating data between a plurality of data communicating entities, data is transmitted simultaneously from at least a first data communicating entity and a second data communicating entity onto a serial data ring. A first portion of the serial data ring is cross coupled to a second portion of the serial data ring so that data from the first data communicating entity avoids conflict with data from the second data communicating entity, thereby emulating a forward and reverse transmission on a single unidirectional serial ring.

Abstract: A multi-input/output serial peripheral interface of an integrated circuit includes many pins coupled to the integrated circuit. The integrated circuit receives an instruction under a control of selectively using only a first pin or a combination of the first pin, a second pin, a third pin, and a fourth pin of the multi-input/output serial peripheral interface. The integrated circuit receives an address using the first pin, the second pin, the third pin, and the fourth pin of the multi-input/output serial peripheral interface. The integrated circuit sends a read out data using the first pin, the second pin, the third pin, and the fourth pin of the multi-input/output serial peripheral interface.

Abstract: Certain exemplary embodiments can comprise a system, which can comprise a module communicatively coupled to a programmable logic controller (PLC). The module can comprise a transmission circuit and/or a receiving circuit. The module can be adapted to communicate with the PLC via 8B/10B encoded frames. A frame of the 8B/10B encoded frames can comprise a plurality of ordered fields.

Abstract: A plurality of modes is provided for communicating between a host system and a peripheral storage system controller. A first communication mode may be selected from the plurality of communication modes based on a bit length required to communicate a physical address. During runtime, a switch from the first communication mode to a second communication mode may be performed in order to improve the efficiency of processing address requests at the storage system controller.

Abstract: An electronic flash memory external storage method and device for data processing system, includes firmware which directly controls the access of electronic storage media and implements standard interface functions, adopts particular reading and writing formats of the external storage media, receives power via USB, externally stores date by flash memory and access control circuit 2 with the cooperation of the firmware, driver and operating system, and has write-protection so that the data can be safely transferred. The method according to present invention is highly efficient and all parts involved are assembled as a monolithic piece so that it has large-capacity with small size and high speed. The device operates in statistic state and is driven by software. It is plug-and-play and adapted to data processing system.

Abstract: An image forming apparatus includes a controller having an integrated circuit for image processing. The controller is connected to an engine via a peripheral component interconnect (PCI). The engine includes a plotter and a scanner. The controller includes a central processing unit (CPU) to which a chip-set is connected via an accelerated graphics port (AGP). The controller also includes an application specific integrated circuit (ASIC) that controls whether to output scanner image data, which is data acquired by the scanner, to the PCI as plotter data for the plotter, or to output the scanner image data to the AGP, or to output image data input through the AGP to the PCI as plotter data for the plotter. The ASIC includes a combiner that combines a plurality of image data.

Abstract: A wireless communication system and a channel changing method thereof are provided. The wireless communication system which includes a plurality of channels, uses one of the plurality of channels as a specific channel, and uses another channel of the plurality of channels as a communication channel, includes: a base terminal for obtaining the one of the plurality of channels as an alternative channel, generating a channel change command including information on the alternative channel, and transmitting the command on a specific channel, when there is a data error received on the communication channel; and a wireless input device for resetting the alternative channel as a new communication channel and performing wireless communication on the communication channel which was reset, after obtaining the information on the alternative channel by receiving the channel change command from the specific channel.

Abstract: A system chip includes a plurality of processing elements for performing primary computations of a plurality of tasks, a plurality of non-processing elements for controlling flow of data associated with the tasks among the processing elements, and a main controller including a scheduler, a resource allocation module, and a power management module. The scheduler assigns the tasks on the processing and non-processing elements with reference to time parameters of the processing and non-processing elements. The resource allocation module controls operations of the processing and non-processing elements with reference to task assignments determined by the scheduler. The power management module performs dynamic voltage management upon the processing and non-processing elements according to the scheduled tasks.

Abstract: A computer program product and distributed data processing system that allows a single physical I/O adapter, such as a PCI, PCI-X, or PCI-E adapter, to validate that a direct memory access address referenced by an incoming I/O transaction that was initiated through a memory mapped I/O operation are associated with a virtual adapter or virtual resource that is referenced by the incoming memory mapped I/O operation is provided. Specifically, the present invention is directed to a mechanism for sharing conventional PCI (Peripheral Component Interconnect) I/O adapters, PCI-X I/O Adapters, PCI-Express I/O Adapters, and, in general, any I/O adapter that uses a memory mapped I/O interface for communications. A single physical I/O adapter validates that one or more direct memory access addresses referenced by an incoming I/O transaction initiated through a memory mapped I/O operation are associated with a virtual adapter or virtual resource that is referenced by the incoming memory mapped I/O operation.

Abstract: The invention relates to a method for detecting a charger on a serial data bus in a first device (8). The method comprises connecting (100) said first device to a second device via a serial data bus interface, measuring (104) logic voltage levels of first (D+) and second (D?) data lines of said serial data bus, and determining whether a battery (14) of said first device (8) may be charged from a power supply line (VBUS) of said serial data bus based on said measured logic voltage levels.

Abstract: An airbag deployment system including at least one module housing, at least one deployable airbag associated with each housing, an inflator associated with each housing for inflating the airbag(s) to deploy into the passenger compartment, an airbag inflation determination unit for determining that deployment of the airbag(s) is/are desired, and respective electronic control units arranged within or proximate each housing and coupled to a respective inflator and the airbag inflation determination unit for initiating the inflator to inflate the airbag(s) in the respective housing upon receiving a signal from the airbag inflation determination unit. The control units include a power supply for enabling initiation of the inflator.

Abstract: A method for improving the speed and efficiency of transmitting data between two components in which the transmitted data is sent, at least partly, through a serial bus is shown. According to the method, the fields in the data frames being transmitted between the components are of a fixed length regardless of the amount of data that the receiving device can receive at one time. The data bits of the fixed-length frame correspond to the signals accepted as input by the receiving component.

Abstract: A system and method for the provision for the auto detection and data exchange within different data transmission environments, such as those involving serial devices, Bluetooth-based devices, ZigBee-based devices, WiFi-based devices and/or WiMax-based devices is provided for in the present invention.

Abstract: A method and system are provided for coupling a DRAM and a memory controller during driver training to reduce mismatches by controlling impedances within the system environment. The memory device, which is typically the device initializing a bit level voltage on a data net, is adjusted through altering what appears to be the reference voltage value to the memory device. A current driven to the memory device is varied in small increments while impedance training is rerun until a desired value is achieved to set the 0 level voltage on the data net.

Abstract: A memory device is connected through an interface to a memory controller. The controller's reference voltage is set based on a driver's impendence of the memory device during driver training. The voltage is applied to a reference resistor pair at the controller and changed until the voltage level switches. The voltage is then set at the reference resistor pair of the controller.

Abstract: A memory module and a related memory system are disclosed. The memory module comprises a semiconductor memory having a data output buffer, a data input buffer, a command/address input buffer and a first termination resistor unit connected to a data bus. The memory module further comprises a second termination resistor unit connected to an internal command/address bus. First and second termination resistor units are preferably of different resistive value and/or type.

Abstract: A method and system are provided for coupling a DRAM and a memory controller during driver training to reduce mismatches by controlling impedances within the system environment. A memory device initializes a bit level voltage on a data net. A driver impedance in a driving element in the controller is modified to yield improvements in timing margins.

Abstract: A computerized system configured to provide a data cell graph for a distributed data set comprised of different data formats. The system comprises a plurality of data repositories, each data repository configured to retain a portion of the distributed data set translated into a uniform semantic language and a plurality of processing cells, each processing cell configured to translate a portion of the distributed data set into the uniform semantic language, wherein the processing cells are further configured to perform at least one of applying rules to classify data against semantic knowledge models and/or adding inferred facts to and/or transforming the structure of the data found in the translated data in the data repository. The processing cells are configured in a computerized data cell graph so as to progressively create a unified semantic knowledge model for the distributed data set.

Abstract: A memory device and memory controller are coupled during driver training to reduce mismatches. The impedances of the system are controlled through a termination at the memory device to yield improvements in timing margins. The coupling of the components on a shared electrical bus through adjustment of the termination values during training removes known offset issues.

Abstract: A circuit for an integrated interface of a PDA and a wireless communication system is suitable for integrating the PDA and the wireless communication system. The circuit includes a first serial port has two terminals, in which one of the two terminals is electrically connected to the PDA, and another one of the two terminals is electrically connected to the wireless communication system. The first serial port is used to bi-directionally transmit a control signal between the PDA and the wireless communication system. A second serial port has two terminals, in which one of the two terminals is electrically connected to the PDA, and another one of the two terminals is electrically connected to the wireless communication system. The second serial port is used to bi-directionally transmit data between the PDA and the wireless communication system.

Abstract: A modular computer system (for example a blade server system) includes a plurality of information processing modules (e.g., server blades). Each information processing module can include a processor operable to provide information processing functions and a service controller operable to provide both management and console functions. A service processor can be connectable via a respective management connection to the service controller of each information processing module. Each management connection between the service processor and a service controller can be operable to carry both management signals and console signals. Management signals to be sent between the service processor and the service controller can be interlaced with console signals via the management connection in one or more management packets bounded by terminal escape sequences.

Abstract: A packetized cascade memory system including a plurality of memory assemblies, a memory bus including multiple segments, a bus repeater module and a segment level sparing module. The bus repeater module is in communication with two or more of the memory assemblies via the memory bus. The segment level sparing module provides segment level sparing for the communication bus upon segment failure.

Abstract: Disclosed are methods and systems, among which is a system that includes a pattern-recognition processor, a central processing unit (CPU) coupled to the pattern-recognition processor via a pattern-recognition bus, and memory coupled to the CPU via a memory bus. In some embodiments, the pattern-recognition bus and the memory bus form about the same number of connections to the pattern-recognition processor and the memory, respectively.

Abstract: A switching device and methods thereof are disclosed. One of the methods includes an arbitration process for communicating a data payload between interface modules. A first intra-chassis packet is sent by a source interface module to the target interface module. The first intra-chassis packet represents a request for permission to transmit a data payload to the target interface. A second intra-chassis packet is received at the source interface module from the target interface module indicating whether the request has been approved. If the request is approved, the source interface module sends a third intra-chassis packet comprising at least a portion of the data payload to the target interface module.

Abstract: A double data rate interface in which the set-up interval is extended for a data path in which data is delayed relative to the other data path. Data is latched into a register comprised of mid cycle type latches, such as for example L2* latches. For example, if the delayed half of the data is not available until the second half of the double data rate cycle, the second half of the data is allowed to have a set-up interval around the mid cycle point while the on-chip timing logic launches the least delayed half of the data on the clock edge after it is set up, without waiting for the expiration of the set up interval of the delayed data.

Abstract: A backup site and a client are coupled to a network and the backup site obtains backup data for the client using a portable storage device by providing a direct coupling between the portable storage device and the backup site. The portable storage device contains full backup data for the client. The direct coupling is separate from the network. Full backup data is uploaded from the portable storage device to the backup site via the direct coupling. At least one incremental backup, based on the prior full backup, is performed to transfer data from the client to the backup site through the network. The network may be the Internet. The direct coupling may be USB, Firewire, or eSATA. Only a subset of data corresponding to a backup dataset may be provided on the portable storage device. Data on the portable storage device may be encrypted.

Abstract: An apparatus and method are provided that include providing a transaction data structure, and monitoring the transaction data structure for a predetermined amount of time. A link between a bus device and a host controller may be provided into a low power state in response to the monitored transaction data structure.

Abstract: Provided are a method, system, and program for managing path groups to an Input/Output (I/O) device. Indication is made of a connection path on which a processing system initially communicated an establish request to establish a connection with an I/O device, wherein attention that the processing system may own a lock for the I/O device is transmitted down the indicated connection path. A request is received from the processing system to add a path to a path group with respect to the I/O device, wherein the added path is capable of comprising the connection path the processing system used to establish the connection with the I/O device. The received path is added to the path group.

Abstract: Exemplary embodiments are directed to broadcasting data on a USB system. The system includes a USB host and multiple broadcast-capable USB devices. Each USB device includes at least a default control endpoint for receiving control information and an isochronous sink endpoint for receiving a broadcast stream. The USB host programs a shared device address to an address register of each USB device such that all broadcast-capable USB devices programmed to that shared device address will accept the broadcast stream. One of the USB devices at the shared device address is set as a primary broadcast slave that will respond to non-isochronous transfers to the shared device address. All other USB devices with the shared device address are set to secondary slaves that ignore non-isochronous transfers to the shared device address.

Abstract: According to one aspect of the invention, when an algorithm bay is connected to a signal processing apparatus according to a first connection mode, a selector of the algorithm bay selects and sets a first function provided by a first function provider as the signal processing function of the signal processing apparatus. When the algorithm bay is connected to the signal processing apparatus according to a second connection mode, the selector of the algorithm bay selects and sets a second function provided by a second function provider as the signal processing function of the signal processing apparatus. According to another aspect of the invention, a first information provider of an algorithm bay supplies a signal indicating first information to be used in the signal processing of a signal processor of a signal processing apparatus to the signal processor via a wired interface of the algorithm bay, wired connection, and a wired interface of the signal processing apparatus.

Abstract: A dual or triple access interface (e.g., hardware and software implementation) allows a CPU and at least one DMA peripheral, e.g., Universal Serial Bus (USB) DMA engine, to transfer data in and/or out of a common single port SRAM by negotiating access requests between the CPU and the DMA peripheral, and then subsequently forms memory cycles to the single port SRAM to satisfy both the CPU's and DMA peripheral's memory access throughput requirements. This allows the CPU and the at least one DMA peripheral to access a shared single port SRAM by time multiplexing granted accesses between, for example, two or three simultaneous memory access requests, thus eliminating the need for a dual port memory.

Abstract: A data transfer control device includes a PATA I/F connected to a PATA bus, an SATA I/F connected to an SATA bus, and a sequence controller that controls a transfer sequence. The PATA I/F includes a task file register (TFR). The sequence controller suspends transmission of a register FIS corresponding to an ATA packet command issued by a host to a device, and performs a dummy setting that causes the host to issue an ATAPI packet command using the TFR. The sequence controller transmits the register FIS corresponding to the ATA packet command to the device after the host has issued the ATAPI packet command.

Abstract: The invention relates to a control and/or data-transmission system comprising a number of I/O modules connected in series one adjacent to the other and a control and/or data-transmission module, as well as a control and/or data-transmission module for controlling I/O modules for such a control and data-transmission system. The invention proposes a control and data-transmission system that comprises a number of I/O modules connected in series one adjacent to each other, wherein each I/O module comprises at least one I/O signal channel and also at least one first signal terminal for connecting the I/O signal channel to a data bus and at least one second signal terminal for connecting a bus subscriber to the I/O signal channel, and wherein the system comprises a control and/or data-transmission module that comprises control electronics for the selective control of the number of I/O modules and that forms a detachable unit.

Abstract: An electronic device includes routing logic operatively coupled to a communication port that is externally accessible so that there is no need to disassemble the electronic device to gain access. The port may be a USB port and provides access to an internal bus. The routing logic is also operatively coupled to a memory subsystem such that it may route data from an external device, connected at the port, to the memory subsystem to modify or replace a boot code, including a BIOS code. A memory interface device includes an interface module, a memory interface module for communicating with a memory subsystem including a boot PROM, and a routing logic coupled to the interface module and the memory interface module. The routing logic routes data from the external device to the boot PROM, so that a boot code, including a BIOS, may be modified or replaced.

Abstract: Methods and apparatuses for improving detection of a Serial Advanced Technology Attachment (“SATA”) target device by a storage initiator over a link. The storage initiator receives a Frame Information Structure (“FIS”) and determines whether the FIS is valid. In direct response to a determination that the FIS is invalid, the storage initiator immediately resets the link to the SATA target device.

Abstract: Application protocol data units are conveyed in a universal serial bus so that a portable electronic object such as a smart card can be recognized by a terminal, such as a micro-computer, as being a peripheral. The header and the data field, when such a data field exists, of each command are encapsulated in data fields of data packets of respective downlink transactions. The data field, when such a data field exists, and the trailer of each response are encapsulated in the data packet data field of at least one uplink transaction. By means of this bus link, the data rate between the terminal and the electronic object is higher, and a plurality of portable electronic objects can be connected to the terminal.

Abstract: A modular computer system (20) including a universal connectivity station (UCS) (22) interconnected to a plurality of remote modules (30, 32, 34, 36, 38, 42) via a plurality of respective high speed serial links (26, 40) such as based on proprietary Split-Bridge™ technology. The plurality modules, including a processor module (42) which may include core parts including a CPU, memory, AGP Graphics, and system bus interface may be remotely located from each of the other modules, including the UCS (22). The present invention achieves technical advantages wherein each module of the modular computer system (20) appear to each device to be interconnected to the other on a parallel bus since the high speed serial links appear transparent. Preferably, although not necessary, each of the modules including the UCS 22 are based on the PCI bus architecture, or the PCMCIA bus architecture, although other bus architectures are well suited to be incorporated using the present invention.

Abstract: A method and apparatus includes a real time event engine that monitors event signals. A real time event detector within the real time event engine detects when the real time event occurs. Thereupon, real time event commands within a real time event command buffer are fetched and consumed by the command processor in response to the occurrence of the real time event. The real time event detector contains a plurality of control registers, which contain an event selector register, a real time command buffer point register, and a real time command buffer length register. A driver may program the registers, whereupon a singe real time event detector may be used in conjunction with a plurality of real time event command buffers.

Abstract: A method of optimizing communication over a high-speed serial bus by minimizing the delay between packets transmitted over the bus is disclosed. The method comprises: calculating the round trip delay between PHYs connected on the bus by pinging; a bus manager sending a configuration packet to all PHYs connected on the bus, the configuration packet containing a minimum gap_count parameter value; and all PHYs connected on the bus sending packets over the bus using the minimum gap_count parameter value as a delay between packets.

Abstract: A system and method of controlling power consumption are provided. The example method may be directed to controlling power consumption in a system including first and second interface blocks, and may include transitioning a first interface block to a power saving mode in response to a status of a first transmission channel, the first transmission channel configured to forward information from the first interface block to a second interface block and transitioning a second interface block to the power saving mode in response to a status of a second transmission channel, the second transmission channel configured to forward information from the second interface block to the first interface block.

Abstract: A control apparatus for controlling at least one peripheral device includes a non-volatile storage element and a controller. The non-volatile storage element is used for storing at least one control information set. The controller is externally coupled to the non-volatile storage element and includes a read-only storage element which stores a segment of program code. The controller loads the segment of program code to execute the segment of program code for reading at least one portion of the control information set from the non-volatile storage element to control the operation of the peripheral device.

Abstract: A data processing apparatus transmits and receives moving image data to and from an external device through a transmission path. A first pipe used for transferring the moving image data and a second pipe used for transferring timing information relating to the processing timing of the moving image data are provided on the transmission path. The moving image data is being transferred to the external device through the first pipe in parallel with the timing information relating to the moving image data being transferred through to the external device through the second pipe.

Abstract: A communication monitoring apparatus (100) monitors a network (130) to which a plurality of devices are connected with an IEEE1394 serial bus. An obtaining unit (111) obtains information that concerns a communication control parameter that is determined or managed by another device on the network. A determining unit (112) determines whether the information that concerns a communication control parameter is compatible with the network (130) based on the information that concerns a communication control parameter that is obtained by the obtaining unit (111). A reporting unit (113) reports a result of determination by the determining unit (111).