Abstract: A position sensing system controls selection of channels in a KVM switch having a plurality of channels. The system has a sensor interface for receiving a sensor reading indicating a current position of a position movable component. Each position of the movable component is associated with one of the plurality of channels. The position sensing system also includes a position component for selecting channels of the KVM switch according to the sensor reading. The position component comprises a position definition component and a translation component. The definition component identifies one of the channels corresponding to the sensor reading based on one of a position definition. Each position definition provides sensor readings corresponding to the positions associated with one of the channels. The translation component generates a signal for selecting the determined channel at the KVM switch. This signal is provided to the KVM switch to switch the KVM channel.

Abstract: A plurality of processing cores, are central storage unit having at least memory connected in a daisy chain manner, forming a daisy chain ring layout on an integrated chip. At least one of the plurality of processing cores places trace data on the daisy chain connection for transmitting the trace data to the central storage unit, and the central storage unit detects the trace data and stores the trace data in the memory co-located in with the central storage unit.

Abstract: In one embodiment, the present invention includes a method for receiving a non-coherent atomic request from a device coupled to an agent via a non-coherent link, accessing a mapping table of the agent to convert the non-coherent atomic request into a coherent atomic request, and transmitting the coherent atomic request via a coherent link to a second agent coupled to the agent to cause the second agent to be a completer of the non-coherent atomic request. Other embodiments are described and claimed.

Abstract: The present disclosure relates to a portable storage device that can communicate with different types of host devices. In some embodiments, the portable storage device receives digital media content via a multi-mode device port and exports a derivative of the digital media content (for example, a media stream) via the same multi-mode device port. In some embodiments, the device port has at least one selectively active pin which is active when receiving digital media content and is dormant when exporting a derivative of the digital media content. Alternatively or additionally, the device port includes at least one selectively active pin which is dormant when receiving digital media content and is active when exporting a derivative of the digital media content. In some embodiments, the portable storage device selects a device mode and/or communications protocol in accordance with at least one detected feature of a complementary port and/or a host.

Abstract: A serial peripheral interface of an integrated circuit including multiple pins is provided. The pins are coupled to the integrated circuit. The integrated circuit receives an instruction through only one of the plurality of pins. The integrated circuit receives an address through the plurality of pins. The integrated circuit sends a read out data through the plurality of pins.

Abstract: There is provided a system for comprising a plurality of blocks, each block comprising any hardware element and a plurality of segments for providing interconnection of the plurality of blocks. A segment comprises a connector between multiple blocks and other segments and segments are connected via the ports of blocks or other segments. Communications between blocks is packet based, each packet including at least a destination block. The packet includes at least one of data, packet/message identification and padding. Blocks have an associated address. A block has one or more input ports and one or more output ports. Segments include means for routing packets to destinations. Each block and segment includes properties. Properties include one or more of clocks, bandwidth, bit widths, and latencies. The plurality of segments for multiple packets to be active on different segments. A single segment includes a plurality of ports for multiple packets to be active on different ports of the segment.

Abstract: System and method for operating a motor using a single general purpose input/output (GPIO) pin of a controller. In one embodiment, a control circuit may include a first terminal coupled to a GPIO pin of a controller. The first terminal can be configured to receive, and output, at least one or more signals. The control circuit may include a plurality of elements coupled to the first terminal, and motor driver circuit output terminal, such that the control circuit may be configured to output one more control signals to the motor driver circuit output terminal for control the motor driver circuit. Motor driver control signals may be based, at least in part, on one or more signals received from the first terminal.

Abstract: A system for recovery of data access of a locked secure storage device can comprise a keystore module and an authorization module. The keystore module may be configured to allow access to a master file system comprising a user encryption key for data stored within the locked secure storage device based on a master code. The authorization module may be configured to receive the administrator code, authenticate the administrator code, decode the master code, and reset a lockout parameter of the locked secure storage device.

Abstract: A semiconductor memory module includes a memory module board having at least one semiconductor memory device, an advanced memory buffer (AMB) for receiving the data and the command/address signal from a host and providing the data and the command/address signal to the at least one semiconductor memory device, and a second termination resistor unit located on the memory module board and electrically connected to the AMB. The at least one semiconductor memory device includes a data input buffer for receiving data via a first input terminal and receiving a first reference voltage via a second input terminal, a command/address input buffer for receiving a command/address signal via a first input terminal and receiving a second reference voltage via a second input terminal, and a first termination resistor unit connected to the first input terminal of the data input buffer.

Abstract: A memory bus with a first bus segment coupled to a memory controller that includes control logic and a first memory device, a second bus segment coupled to a second memory device, and a switch between the first bus segment and the second bus segment. The control logic outputs control information to the switch to selectively decouple the first bus segment and the second bus segment to effect a change in the length of the memory bus to enable data transfer with respect to the first memory device at a first data rate. Additionally, the control logic may output control information to the switch to selectively couple the first bus segment and the second bus segment to increase the length of the memory bus to enable data transfer with respect to the second memory device at a second data rate that is slower than the first data rate.

Abstract: A mobile device includes an air chip card for wireless connectivity to the internet or another mobile device, the air chip card being removably connected to the mobile device. A plurality of calling numbers are associated with the mobile device where an active call can be switched from one number to another. Means captures images for engaging in a video chat. A chat window displays the video chat. An optical port ports information to and from the mobile device where the optical port further enables scanning of objects. Means displays a flash in message. Means attaches a webpage to the mobile device for changing functions of the mobile device. Means solar charges the mobile device.

Abstract: In a printing system or method, two printing units apply printing ink onto a recording material, each printing unit having multiple apparatuses with a respective microprocessor controller. The microprocessor controllers are connected with one another via a respective data bus segment and each data bus segment has multiple data lines. The two data bus segments of the two printing units are connected with a bus switch. The bus switch has a data switch to connect a respective one of the lines of the one data bus segment with the corresponding line of the other data bus segment, a respective terminating resistor being provided for each data bus segment. The terminating resistors are connected with a respective terminating switch coupled with the data switches such that either all terminating switches are open and all data switches are closed, or all terminating switches are closed and all data switches are open.

Abstract: Quality-of-Servitrce (QoS) is an important system-level requirement in the design and implementation of on-chip networks. QoS requirements can be implemented in an on-chip-interconnect by providing for at least two signals indicating priority at a transaction-level interface where one signal transfers information in-band with the transaction and the other signal transfers information out-of-band with the transaction. The signals can be processed by the on-chip-interconnect to deliver the required QoS. In addition, the disclosed embodiments can be extended to a Network-on-Chip (NoC).

Abstract: An anti-virus system for enforcing a virus monitoring and scanning process, the anti-virus and firewall system comprises a master CPU card, a plurality of slave CPU cards and a programmable logic. The master CPU card is used for controlling the virus monitoring and scanning process and dividing the virus monitoring and scanning process into a plurality of sub-processes. The plurality of slave CPU cards are controlled by the master CPU card in a software level and a hardware level, each of the plurality of slave CPU cards receives and processes one of the plurality of sub-processes then sends back to the master CPU card. The programmable logic controlled by the master CPU card for monitoring and controlling said plurality of slave CPU cards at a hardware level.

Abstract: Provided is a method of streaming transfer of data between a plurality of devices of a computer system. The method includes providing data to be sent from a source device to a target device and includes receiving, at the source device, one or more transfer credits from the target device. A transfer credit may be indicative of an amount of data that the target device is authorizing to be sent to the target device. The method also includes determining whether or not an accumulated transfer credit value satisfies a threshold value. If the accumulated transfer credit value satisfies the threshold value, the source device sends data to the target device and modifies the accumulated transfer credit value based on a quantity of data sent. If the accumulated transfer credit value does not satisfy the threshold value the source device does not send data to the target device.

Abstract: A data communications system is disclosed having at least one Legacy cloud coupled to at least one Beta cloud. The system further having at least one BOSS node and at least one border node. A method for ensuring compatibility is disclosed comprising determining when the BOSS node is idle, determining whether the last packet transmitted by any border node was an Alpha format packet if the BOSS node is idle, and unlocking the Legacy cloud if the last packet transmitted by the border node was not an Alpha format packet.

Abstract: As part of the protocol for Common Public Radio Interface/Open Base Station Architecture Initiative (CPRI/OBSAI) systems, multiple data rates are supported, which are each supported by one or more reference clock frequencies. Traditionally, timing circuits presently used for the physical layer (PHY) paths to determine the data rates for the serial data have been plagued with numerous problems. Here, however, a circuit that performs an automatic rate sense (ARS) of high speed serial signals in a low speed digital domain is provided, which is also relatively easy to implement and robust.

Abstract: A computing module includes an interface to asynchronously, serially exchange parallel system bus data with one or more other modules of a computer system that includes the computing module. The computing module can asynchronously, serially transfer first parallel bus data to another module of the computer system, and can asynchronously, serially receive second parallel bus data from another module of the computer system.

Abstract: Dynamic bus-based virtual channel multiplexing may be accomplished by establishing one or more virtual channels with a multiplexing device function driver and a multifunction device coupled to a bus, determining one or more functions to be activated on the device, and for each activated function, launching a second-tier function driver to handle operation of the activated function. The second-tier function driver has a function driver type. Establishment of the one or more virtual channels is accomplished using a multiplexing protocol and multiplexing device function driver with the multifunction device via a bus driver coupled to the bus.

Abstract: The invention provides a method and apparatus for providing a synchronized multichannel universal serial bus, the method in one aspect comprising supplementing the signal channels in the USB specification to provide synchronization information from an external source, and in another aspect comprising observing USB traffic and locking a local clock signal of a USB device to a periodic signal contained in USB data traffic, wherein the locking is in respect of phase and/or frequency.

Abstract: The present disclosure relates to an example of a method for a first router to adaptively determine status within a network. The network may include the first router, a second router and a third router. The method for the first router may comprise determining status information regarding the second router located in the network, and transmitting the status information to the third router located in the network. The second router and the third router may be indirectly coupled to one another.

Abstract: A motherboard includes a central processing unit (CPU) with a reset signal output pin, a buffer circuit, and at least one memory device. The buffer circuit includes an input terminal connected to the reset signal output pin of the CPU and at least one output terminal. The input terminal and the at least one output terminal have the same voltage level. The at least one memory device has a reset signal receiving terminal connected to the at least one output terminal of the buffer circuit.

Abstract: Various embodiments are described herein for a mobile communication device that utilizes a smart battery. The mobile device includes a main processor for controlling the operation of the mobile communication device. The smart battery is coupled to the main processor and provides supply power. The smart battery includes a battery processor for controlling the operation of the smart battery and communicating with the main processor, and a battery module having one or more batteries for providing the supply power. A battery interface is provided for coupling between the main processor and the battery processor for providing communication therebetween. The battery interface comprises a data communication line and protection circuitry for protecting the main processor from electrostatic discharge. A communication protocol is also provided for communication between the main processor and the battery processor.

Abstract: An apparatus for detecting bus connection is provided for determining whether an electrical connector of a peripheral device is connected to an electrical connection port. In the apparatus, a detection capacitor is electrically coupled to a detection pin in the electrical connection port, and a controller is provided to transmit a detection signal to the detection pin. According to the signal fed back by the detection capacitor, the occurrences of the charge and discharge phenomena in the detection capacitor are determined, and then the controller is able to determine whether the detection pin of the electrical connector is electrically coupled to the electrical connector, so as to initiate a system event. The detection pin is not electrically charged when the detection pin is not electrically coupled to the electrical connector, so as to prevent the detection pin from being electrolyzed in the water or in a humid circumstance.

Abstract: A data processing apparatus may include a data conversion unit that arranges the input data in each transfer data in the conversion unit using one transfer data as one transfer unit and a predetermined number of transfer units as one conversion unit when converting a plurality of input data input sequentially into transfer data having a bit number identical to a predetermined bit number of a data bus and sequentially transferring the converted transfer data. The data conversion unit may include a data generation unit and a first data arrangement changing unit. The first data arrangement changing unit may include a bit change number calculating unit, a bit change number analysis unit, a first data sorting unit, and a data coupling unit.

Abstract: The computer system of the present invention has a plurality of SAS target devices, an SAS initiator device, and a service delivery subsystem that is connected to each SAS target device by means of a physical link that is physical wiring and connected to the SAS initiator device by means of a wide link constituted by a plurality of physical links. The SAS initiator device controls how many physical links in the wide link are allocated to a particular SAS target device, whereby access from the SAS initiator device to the SAS target device is made via a physical link that is allocated to the SAS target device and is not made via a physical link that is not allocated to the SAS target device.

Abstract: A method and system for converting the output of a communications port (e.g., a serial port or a USB port) into video signals representing the output of a terminal using a KVM switch. Upon receiving characters from the communications port, the system interprets the characters as terminal emulation commands and internally generates a representation of what a resulting terminal screen would look like. From that internal (digital) representation, the system produces analog outputs representing the terminal screen. The analog outputs are output on the monitor attached to the KVM switch.

Abstract: A method for decrypting a serial transmission signal includes the following steps. First, the serial transmission signal including a serial data signal and a serial clock signal is received. Then, m bits are sequentially read from the serial data signal according to the serial clock signal. Next, values corresponding to the m bits are generated. Thereafter, each value is added to a content value of a register by an addition operation to obtain an addition result, and then the addition result replaces the content value and is stored in the register.

Abstract: A data processing apparatus and method for measuring a value of a predetermined property of transactions are provided. The data processing apparatus has initiator circuitry for initiating transactions, recipient circuitry for handling each transaction initiator by the initiator circuitry, and a communication path interconnecting the initiator circuitry and the recipient circuitry via which the transactions are propagated between the initiator circuitry and the recipient circuitry. Measurement circuitry is coupled to the communication path for measuring a value of a predetermined property of the transactions, such as the latency of those transactions. The measurement circuitry has active transaction count circuitry for maintaining an indication of the number of transactions in progress, and accumulator circuitry for maintaining an accumulator value which is increased dependent on the number of transactions in progress.

Abstract: A method of implementing data transmission is provided, which comprises: A) comparing bit by bit data to be transmitted currently with previous transmitted data, and counting to obtain total number of different bits; and B) when it is determined that the total number of different bits is more than a half of number of bits of the data to be transmitted currently, inverting the data to be transmitted currently and then converting the inverted data into a differential signal for transmission. A device of implementing data transmission is also provided. The method and device provided by embodiments of the present invention can minimize electromagnetic interference during data transmission.

Abstract: Described embodiments provide a memory system including a plurality of addressable memory arrays. Data in the arrays is accessed by receiving a logical address of data in the addressable memory array and computing a hash value based on at least a part of the logical address. One of the addressable memory arrays is selected based on the hash value. Data in the selected addressable memory array is accessed using a physical address based on at least part of the logical address not used to compute the hash value. The hash value is generated by a hash function to provide essentially random selection of each of the addressable memory arrays.

Abstract: An information processing system includes a host device transmitting an order according to a USB standard and an information processing terminal responding to the order. The information processing terminal includes a storing unit, a first operation unit, a receiver, an operation-mode switch, a first processor, and a first outputting unit. The host device includes a second operation unit, a transmitter, a second processor, and a second outputting unit.

Abstract: Methods, apparatus, and computer program products are described for resetting a HyperTransport link in a blade server, including reassigning, by a blade management module, a gate signal from enabling a transceiver to signaling a HyperTransport link reset; sending, by the blade management module to a reset sync module on an out-of-band bus, the gate signal; and in response to the gate signal, sending, by the reset sync module to the blade processor, HyperTransport reset signals. The HyperTransport link includes a bidirectional, serial/parallel, high-bandwidth, low-latency, point to point data communications link. The blade server includes the blade processor, the reset sync module, and the baseboard management controller. The blade server is installed in the blade center. The blade center includes the blade management module. The blade management module is coupled to the baseboard management controller by the blade communication bus.

Abstract: An IC card and a terminal mounted with an IC card are disclosed.

Abstract: A printer utility 06 determines, upon receiving an instruction to display the remaining amount of ink, whether the interface with the selected printer is busy. If not busy, a status is obtained using that interface, and the remaining amount of ink, which is a part of the status, is displayed. If busy, a nearest previous status of the printer is read if stored in a printer status storage unit 05, and the remaining amount of ink is displayed. If not stored, a nearest previous status of the printer is read if stored in a printer status storage unit 07, and the remaining amount of ink is displayed.

Abstract: A computer device comprises an output monitor configured to determine an output configuration setting for the computer device and automatically actuate an output setting indicator corresponding to the output configuration setting.

Abstract: A telecommunications system and constituent two-wire interface module. The two-wire interface module includes a first two-wire interface component configured to receive a first two-wire interface communication following a first two-wire interface protocol, and a second two-wire interface component configured to generate a second two-wire interface communication following a second two-wire interface protocol. The first and second two-wire interface communications each include a header portion and a payload portion. The second two-wire interface component is further configured to use one or more of the data fields from the payload portion of the first two-wire interface communication in the header portion of the second two-wire interface communication.

Abstract: Provided are a data processor, and a control system, in which an interrupt controller and an event link controller are adopted. The event link controller responds to a generated event signal to output a start control signal for controlling start of an operation of a circuit module. The circuit module is able to generate an event signal. The event link controller generates the start control signal according to the correspondences between event signals and start control signals which are defined by event control information. The links between the event signals and start control signals can be prescribed by the event control information. Therefore, operations of circuit modules prescribed by such links can be controlled sequentially. The control neither involves save and return processes by CPU as in the interrupt processing, nor needs priority level control as executed on competing interrupt requests.

Abstract: An arrangement for transferring message based communications between separate disjunctive components. The arrangement includes at least two components. At least a first component is arranged to provide services to at least one second component and/or to an operator of the loosely coupled system. At least one message bus is arranged to perform real-time transfers of communications from/to the at least one first component to/from the at least one second component. The at least one message bus is connected to or integrated in an internal communication backbone arranged with a communication member for establishing outgoing communication links. A predetermined message based interface is arranged relative to each of the components and the at least one message bus such that all communications between the at least one first component and the at least one second component are defined in the same single standardized message language.

Abstract: An apparatus, system and method for providing health-care equipment in a plurality of customizable configurations. A configuration includes a selection and arrangement of health-care equipment modules that each provide specialized support for the provision of health care, including the measurement of physiological parameters. Various types of configurations include those adapted to be mounted upon a desk top or a wall surface, or adapted for wheel mounting or hand-carriable mobile configurations.

Abstract: A method for saving power in transmission of data across buses. By knowing the power characteristics of a bus and characteristics of data to be transmitted across the bus, the data can be encoded in such a fashion as to conserve system power over transmitting the same data in an unencoded format across the bus. The encoding method may be selected before transmission of the data across the bus, and may change depending on the data to be transmitted across the bus.

Abstract: A method and apparatus for avoiding live-lock during transaction execution is herein described. Counting logic is utilized to track successfully committed transactions for each processing element. When a data conflict is detected between transactions on multiple processing elements, priority is provided to the processing element with the lower counting logic value. Furthermore, if the values are the same, then the processing element with the lower identification value is given priority, i.e. allowed to continue while the other transaction is aborted. To avoid live-lock between processing elements that both have predetermined counting logic values, such as maximum counting values, when one processing element reaches the predetermined counting value all counters are reset. In addition, a failure at maximum value (FMV) counter may be provided to count a number of aborts of a transaction when counting logic is at a maximum value.

Abstract: The invention relates to a control and/or data-transmission system comprising a number of I/O modules connected in series one adjacent to the other and a control and/or data-transmission module, as well as a control and/or data-transmission module for controlling I/O modules for such a control and data-transmission system. The invention proposes a control and data-transmission system that comprises a number of I/O modules connected in series one adjacent to each other, wherein each I/O module comprises at least one I/O signal channel and also at least one first signal terminal for connecting the I/O signal channel to a data bus and at least one second signal terminal for connecting a bus subscriber to the I/O signal channel, and wherein the system comprises a control and/or data-transmission module that comprises control electronics for the selective control of the number of I/O modules and that forms a detachable unit.

Abstract: The invention relates to a microprocessor having a plurality of components which are selected from registers (14,16), arithmetic logic units (30,32), memory (36,38), input/output circuits and other similar components where the plurality of components are interconnected in a manner which allows connection between some of the components to be varied under program control.

Abstract: A flash-card reader improves transmission efficiency by using bulk streaming of multiple pipes. A bulk data-out pipe carries host write data to the card reader and can operate in parallel with a bulk data-in pipe that carries host read data that was read from a flash card attached to the card reader. Status packets do not block data packets since the he status packets are buffered through a separate status pipe, and commands are buffered through a command pipe. Flash data from multiple flash cards are interleaved as separate endpoints that share the bulk data-in pipe. A data in/out streaming state machine controls streaming bulk data through the bulk data-in and data-out pipes, while a status streaming state machine controls streaming status packets through the status pipe. Transaction overhead is reduced using bulk streaming where packets for several commands are combined into the same bulk streams.

Abstract: Transfer of data blocks between a host and a multi-media card (“MMC”) are performed in a pre-defined mode. In pre-defined mode, the host sets a pre-determined number of blocks, a “multiblock,” to be transferred. Use of pre-defined mode results in faster transfers than those performed using an open-ended mode incorporating a stop command. Furthermore, corruption errors resulting from delays in providing the stop command which may occur in an open-ended mode are avoided. Pre-defined multiblock transfers are supported by existing operating systems through trapping open-ended mode transfers in the MMC stack, leaving existing device drivers unaffected.

Abstract: A bus system includes a plurality of stubs; a plurality of connectors, each of which is serially coupled between a corresponding one of the stubs and a corresponding one of memory modules; a plurality of first serial loads, each of which is serially coupled to a corresponding one of the connectors; and a plurality of second serial loads, each of which is serially coupled to characteristic impedance of a transmission line of a corresponding one of the stubs, wherein the first and the second serial loads are determined to be impedance matched at each transmission line terminal of the stubs.

Abstract: Providing access to a backup application is disclosed. A request to access a service associated with a backup application is received via a mobile telecommunication network from a client running on the mobile telecommunication device. The backup application is communicated with on behalf of the client running on the mobile telecommunication device to provide access to the service associated with a backup application.

Abstract: A processor may include several processor cores, each including a respective higher-level cache; a lower-level cache including several tag units each including several controllers, where each controller corresponds to a respective cache bank configured to store data, and where the controllers are concurrently operable to access their respective cache banks; and an interconnect network configured to convey data between the cores and the lower-level cache. The controllers may share access to an interconnect egress port coupled to the interconnect network, and may generate multiple concurrent requests to convey data via the shared port, where each of the requests is destined for a corresponding core, and where a datapath width of the port is less than a combined width of the multiple requests. The given tag unit may arbitrate among the controllers for access to the shared port, such that the requests are transmitted to corresponding cores serially rather than concurrently.

Abstract: A general bus system is provided which combines a number of internal lines and leads them as a bundle to the terminals. The bus system control is predefined and does not require any influence by the programmer. Any number of memories, peripherals or other units can be connected to the bus system (for cascading).