Abstract: A method includes generating a data packet at a source device for transmission via an Institute of Electrical and Electronics Engineers 802.11 wireless network. The data packet includes multiple data symbols that are duplicated in the data packet. At least a portion of a preamble of the data packet is not duplicated in the data packet. The portion of the preamble indicates that the packet is a low rate mode packet. The method also includes transmitting the data packet from the source device to a destination device via the wireless network.

Abstract: A distributed work processing system for processing computational tasks IS scalable and fault-tolerant without requiring centralized control. Worker processes running on worker hosts and worker coordinators running on worker coordinator hosts interact with a task store that holds a collection of tasks to be performed by a logical group of worker processes, a lock database used for locking the logical group for coordination by one worker coordinator process at a time, a membership store that contains mappings of worker processes to logical groups, and an assignment store indicating which tasks are assigned to which workers. The worker coordinator process has a scanner process to deal with unassigned tasks and deduplicating duplicate assignments. If a worker coordinator does not see enough worker processes, it can instantiate more. If a worker process does not see a worker coordinator, it can instantiate one.

Abstract: In one embodiment, the present invention includes a method for handling a request received in an agent designed in accordance with a peripheral component interconnect (PCI) specification using PCI Express™ semantics. More specifically, responsive to determining that the agent does not support the request, an unsupported request detection register of the agent can be updated, and a response sent from the agent to indicate that the agent does not support the request. Other embodiments are described and claimed.

Abstract: Three-dimensional (3-D) processor devices are provided, which are constructed by connecting processors in a stacked configuration. For instance, a processor system includes a first processor chip comprising a first processor and a second processor chip comprising a second processor. The first and second processor chips are connected in a stacked configuration with the first and second processors connected through vertical connections between the first and second processor chips. The processor system further includes a mode control circuit to selectively operate the processor system in one of a plurality of operating modes. For example, in a one mode of operation, the first and second processors are configured to implement a run-ahead function, wherein the first processor operates a primary thread of execution and the second processor operates a run-ahead thread of execution.

Abstract: A method and apparatus for providing caching service in network infrastructure. In an embodiment, there is provided a method for providing caching service in network infrastructure, comprising: in response to at least one application node accessing data in a storage node, caching a copy of the data in a cache server; in response to the at least one application node accessing the data in the storage node, obtaining an identifier indicating whether the data in the storage node is valid or not; and in response to the identifier indicating the data in the storage node is valid, returning the copy; wherein the at least one application node and the storage node are connected via the network infrastructure, and the cache server is coupled to a switch in the network infrastructure. In another embodiment of the present invention, there is provided an apparatus for providing caching service in network infrastructure.

Abstract: Embodiments of the present invention disclose a PCI express device, and a link energy management method and device. The method includes: obtaining, by a first device, adjustment information for performing adjustment processing on a current rate and/or bit width of a PCI express link; stopping, by the first device, data sending, and clearing a master enable bit of a configuration space command register of a second device at an opposite end of the link, so that the second device stops data sending after current data sending is finished; performing, by the first device, adjustment processing on the rate and/or bit width of the link according to the adjustment information; resuming, by the first device, the data sending, and resetting the master enable bit, so that the first device and the second device send and receive data again at a rate and/or bit width that is obtained after the adjustment processing.

Abstract: A network device connected via a bus with a plurality of network devices includes: an authentication unit that executes authentication based upon message authentication information included in data transmitted, via the bus, by one of the plurality of network devices acting as a sender device; and a processing unit that invalidates the data upon determining that unauthorized data have been transmitted by the sender device impersonating another network device among the plurality of network devices if the authentication fails.

Abstract: Executing multiple concurrent transactions on the single database schema using a single concurrent transaction database infrastructure, wherein the single database schema is a single concurrent transactional relational database.

Abstract: A platform that facilitates software application development, maintenance, and support includes a storage component that receives structured and unstructured data pertaining to at least one application subject to development, maintenance, or support and causes the structured and unstructured data to be stored in a distributed fashion over a plurality of accessible data repositories. The storage component causes the structured and unstructured data to be stored in the data repositories such that the structured and unstructured data is accessible through utilization of a common access format. An executor component executes an analytical process over the structured and unstructured data and generates a first dataset, wherein the storage component causes the first dataset to be stored in at least one of the plurality of accessible data repositories in a format that is accessible by front end analysis applications.

Abstract: Techniques are disclosed relating to integrated circuits that implement a virtual memory. In one embodiment, an integrated circuit is disclosed that includes a translation lookaside buffer configured to store non-prefetched translations and a translation table configured to store prefetched translations. In such an embodiment, the translation lookaside buffer and the translation table share table walk circuitry. In some embodiments, the table walk circuitry is configured to store a translation in the translation table in response to a prefetch request and without updating the translation lookaside buffer. In some embodiments, the translation lookaside buffer, the translation table, and table walk circuitry are included within a memory management unit configured to service memory requests received from a plurality of client circuits via a plurality of direct memory access (DMA) channels.

Abstract: In a lighting device (101), a primary control unit (103) is arranged to select, on the basis of an obtained lighting device control command, a broadcast communication mode or an addressing communication mode of a control unit interface (113), and to communicate at least one light generation control command to at least one light unit interface (117) of at least one respective light unit (107) of a group of light units (107) of the lighting device (101) via a control unit interface (113) of the primary control unit (103) using the selected communication mode.

Abstract: A method for operating a decimal-floating point (DFP) processor. The method includes identifying a first op-code requiring read access to a first plurality of DFP operands in a vector register of the DFP processor; granting read access from a first port of the vector register to a first execution unit of the DFP processor selected to execute the first op-code; initializing a read pointer of the first port; reading out, from the first port and based on the read pointer, a first DFP operand of the plurality of DFP operands in response to a read request from the first execution unit; and adjusting the read pointer of the first port in response to reading out the first DFP operand.

Abstract: An air-conditioning apparatus includes a refrigerant circuit having a plurality of expansion devices that controls a flow rate of the refrigerant flowing in each of a plurality of heat exchangers related to heat medium; a heat medium circuit having the heat exchangers related to heat medium and a use side heat exchanger that exchanges heat between the heat medium and air; heat medium flow switching devices disposed on an inflow side and an outflow side of the use side heat exchanger to mix or diverge the heat medium pertaining to the heat exchangers related to heat medium; and a controller that controls at least the heat medium flow switching device on the inflow side or the outflow side that controls the amount of heat exchange in each of the heat exchangers related to heat medium during cooling only operation mode or heating only operation mode.

Abstract: An information processing system includes a first information processing apparatus and a second information processing apparatus that are interconnected via a network. The first information processing apparatus includes an input unit configured to input a group of programs, a first install unit configured to install a first program of the input group of programs onto the first information processing apparatus, and a transmission unit configured to transmit a second program of the input group of programs to the second information processing apparatus. The second information processing apparatus includes a second install unit configured to install the second program transmitted from the transmission unit onto the second information processing apparatus.

Abstract: A method and apparatus to operate a watchdog timer having a first time out period in a processing system. The watchdog timer receives an indication of a change in a mode of operation in the processing system. In response to the change in the mode of operation of the processing system, the watchdog timer changes the time out period to a second time out period corresponding to the new mode of operation.

Abstract: A voice or video call is to be established between a caller and a callee based on a call flow that involves a call establishment request and a corresponding call acceptance response. A first call establishment request is sent to a called terminal (of the callee) that is unready to accept the call upon receiving this first call establishment request. Once the called terminal is ready to accept the call, instead of the call acceptance response, a reverse call establishment request for the call is received back from the called terminal. The reverse call establishment request is automatically accepted on behalf of the caller on condition that the reverse call establishment request was received back from the called terminal within a certain time limit. If so, the call is accepted by sending an instance of the call acceptance response to called terminal.

Abstract: A storage device is detected as being decoupled from an apparatus. At least one partition of the storage device is part of a storage volume that includes an array of separate storage devices in an initial configuration prior to being decoupled. In response to the storage device being recoupled to the apparatus, a universally unique identifier (UUID) of the storage device is detected. In response to determining the UUID of the storage device was previously associated with the storage volume, the storage volume is reconfigured/restored to include the at least one partition of the storage device in the initial configuration.

Abstract: A system and method suited for improved overall data transmission having a hardware-based transceiver configured for transmitting upstream data with suppressed data packets. In TCP sessions between devices, a server seeks an “acknowledgement” that the downstream data transmission has been received by a client. Some data packets sent upstream may contain only TCP acknowledgement data and therefore may be combined with other purely TCP acknowledgement data packets in order to reduce the impact of the TCP acknowledgement packets on the overall upstream data throughput. In addition, this results in increased TCP performance in the downstream transmission direction as well because the algorithm enables replacing earlier arriving ACK packets with later arriving ACK packets which allows the device to send all TCP ACK information known to the suppressor at the earliest possible time.

Abstract: Systems and methods for maintaining an order of read and write transactions for each source through a bridge in a bus fabric. The bridge provides a connection from a first bus to a second bus within the bus fabric. The first bus has a single path for read and write transactions and the second bus has separate paths for read and write transactions. The bridge maintains a pair of counters for each source in a SoC to track the numbers of outstanding read and write transactions. The bridge prevents a read transaction from being forwarded to the second bus if the corresponding write counter is non-zero, and the bridge prevents a write transaction from being forwarded to the second bus if the corresponding read counter is non-zero.

Abstract: A bidirectional bus system that includes a bus master having a first transmitter coupled to a bidirectional bus. The first transmitter transmits a signal in a first voltage range onto the bus. The bus master has a first receiver coupled to the bus. A bus slave having a second transmitter coupled to the bus is included. The second transmitter transmits a signal in a second voltage range onto the bus, where the bus slave having a second receiver is coupled to the bus. The first receiver is configured to interpret the signal in the first voltage range to indicate an idle state while the second receiver interprets the signal in the first voltage range as indicating data. The second receiver interprets the signal in the second voltage range as indicative of an idle state while the first receiver interprets the signal in the second voltage range as indicating data.

Abstract: Aspects of the subject disclosure relate to a storage device including a flash memory, a controller coupled to the flash memory, wherein the controller is configured to store data to the flash memory and a power arbiter unit coupled to the controller and to the flash memory via a plurality of flash channels, wherein the power arbiter unit is configured to receive a plurality of power requests via one or more of the plurality of flash channels and process the plurality of power requests based on a respective priority identifier associated with each of the plurality of power requests. Additionally, a computer-implemented method and power arbiter unit (PAB) are provided.

Abstract: Each time a currently scheduled virtual machine (VM) accesses a hardware resource over a bus for the hardware resource via the currently scheduled VM running on a processor, a hardware component adjusts a bandwidth counter associated with usage of the bus for the hardware resource, without involvement of the currently scheduled VM or a hypervisor managing the currently scheduled VM. Responsive to the bandwidth counter reaching a threshold value, the hardware component issues an interrupt for handling by the hypervisor to maintain bandwidth quality-of-service (QoS) of bus bandwidth related to the hardware resource. Upon expiration of a regular time interval prior to the bandwidth counter reaching the threshold value, the hardware component resets the bandwidth counter to a predetermined value associated with the currently scheduled VM, without involvement of the currently scheduled VM or the hypervisor; the hardware component does not issue an interrupt. The hardware resource can be memory.

Abstract: Each time a currently scheduled virtual machine (VM) accesses a hardware resource over a bus for the hardware resource via the currently scheduled VM running on a processor, a hardware component adjusts a bandwidth counter associated with usage of the bus for the hardware resource, without involvement of the currently scheduled VM or a hypervisor managing the currently scheduled VM. Responsive to the bandwidth counter reaching a threshold value, the hardware component issues an interrupt for handling by the hypervisor to maintain bandwidth quality-of-service (QoS) of bus bandwidth related to the hardware resource. Upon expiration of a regular time interval prior to the bandwidth counter reaching the threshold value, the hardware component resets the bandwidth counter to a predetermined value associated with the currently scheduled VM, without involvement of the currently scheduled VM or the hypervisor; the hardware component does not issue an interrupt. The hardware resource can be memory.

Abstract: Disclosed herein are systems, methods, and non-transitory computer-readable storage media for calculating and reporting the cost-savings associated with communicating content on a single stream of data from a content server versus communicating that same content to clients where each client has an individual data stream connection, and the comparison of those costs over various data paths. These costs can be the actual bandwidth, the data throughput, or monetary in nature. They can also include other factors beyond communication rates, such as setup, maintenance, and switching costs.

Abstract: Processor-based system hybrid ring bus interconnects, and related devices, systems, and methods are disclosed. In one embodiment, a processor-based system hybrid ring bus interconnect is provided. The processor-based system hybrid ring bus interconnect includes multiple ring buses, each having a bus width and configured to receive bus transaction messages from a requester device(s). The processor-based system hybrid ring bus interconnect also includes an inter-ring router(s) coupled to the ring buses. The inter-ring router(s) is configured to dynamically direct bus transaction messages among the ring buses based on bandwidth requirements of the requester device(s). Thus, less power is consumed than by a crossbar interconnect due to simpler switching configurations. Further, the inter-ring router(s) allows for provision of multiple ring buses that can be dynamically activated and deactivated based on bandwidth requirements.

Abstract: Various embodiments of the present disclosure provide techniques for monitoring one or more transactions output from a configurable logic system (CLS) to a hard logic system. The CLS and the hard logic system are communicatively coupled by a bridge. The hard logic system receives an exception indicating that a malformed interconnect response has been output by the CLS, clears all pending CLS transactions, isolating the CLS, and executes a run-time recovery process. The run-time recovery process may include reading an interconnect register to obtain an offending address, within the CLS, associated with the malformed interconnect response, and logging the offending address into a system log.

Abstract: A method and apparatus for scheduling reservations of resources in a packet-switched communication network including end-nodes and core network switches are described including a time information to each request, issued by an end-node and forwarded by at least one core network switch, and requesting a resource reservation for receiving a stream defined by specifications at a time which is represented by the time information, the reservation scheduling being handled at a data link layer of an Open Systems Interconnection (OSI) model and storing the time information, included into each forwarded end-node request in correspondence with associated stream specifications, into at least one related database managed by a core network switch participating in the request forwarding.

Abstract: Systems and techniques are disclosed that include in one aspect a computer implemented method storing a received stream of data elements in a buffer, applying a boundary condition to the data elements stored in the buffer after receiving each individual data element of the stream of data elements, and producing one or more data elements from the buffer based on the boundary condition as an output stream of data elements sorted according to a predetermined order.

Abstract: The invention relates to a method for wire bound, high precision, temporal synchronization of measured value acquisition in a measurement system designed as a space coordinate measurement apparatus having a plurality of measurement sub-units with signaling of a time for triggering the measured value acquisition by means of a trigger signal and with the respective acquisition and intermediate storage of a measured value in the measurement sub-unit at the time determined by the trigger signal. Each acquisition of the measured value is carried out in the measurement sub-units in a time quantified manner with a local timing signal of the measurement sub-unit.

Abstract: Disclosed is a computer system (100) comprising a processor unit (110) adapted to run a virtual machine in a first operating mode; a cache (120) accessible to the processor unit, said cache including a cache controller (122); and a memory (140) accessible to the cache controller for storing an image of said virtual machine; wherein the processor unit is adapted to create a log (200) in the memory prior to running the virtual machine in said first operating mode; the cache controller is adapted to transfer a modified cache line from the cache to the memory; and write only the memory address of the transferred modified cache line in the log; and the processor unit is further adapted to update a further image of the virtual machine in a different memory location, e.g. on another computer system, by retrieving the memory addresses stored in the log, retrieve the modified cache lines from the memory addresses and update the further image with said modifications.

Abstract: Described are techniques for configuring storage access control. A set of inputs including a first identifier of an initiator port and a device set devices in a data storage system is received. Responsive to receiving the set of inputs, an allowable path set is automatically defined for the initiator in accordance with an initiator-level of granularity. Each device in the device set is accessible by the initiator over each path in the allowable path set. The allowable path set includes paths between the initiator port and each target port of the data storage system. A set of target ports is either specified using a wildcard indicator denoting all target ports of the data storage system, or the set of target ports is otherwise determined implicitly as all target ports of the data storage system.

Abstract: Disclosed is a computer system (100) comprising a processor unit (110) adapted to run a virtual machine in a first operating mode; a cache (120) accessible to the processor unit, said cache including a cache controller (122); and a memory (140) accessible to the cache controller for storing an image of said virtual machine; wherein the processor unit is adapted to create a log (200) in the memory prior to running the virtual machine in said first operating mode; the cache controller is adapted to transfer a modified cache line from the cache to the memory; and write only the memory address of the transferred modified cache line in the log; and the processor unit is further adapted to update a further image of the virtual machine in a different memory location, e.g. on another computer system, by retrieving the memory addresses stored in the log, retrieve the modified cache lines from the memory addresses and update the further image with said modifications.

Abstract: A method and apparatus to interface a semiconductor storage device and a host in order to provide performance throttling of the semiconductor storage device. In the method, the semiconductor storage can receive a setting request command from the host. The semiconductor storage device sets a performance throttling parameter to a particular value in response to the setting request command. The semiconductor storage device can send to the host a setting response signal indicating completion of the setting of the performance throttling parameter.

Abstract: An arbiter configured to selectively grant access to a shared bus to a plurality of requestors. The arbiter includes a plurality of request shapers each configured to receive a request signal corresponding to a request, from a respective one of the plurality of requestors, to access the shared bus, a base priority signal indicating a base priority level of the respective one of the plurality of requestors, and a delta period signal indicating a counter value threshold. The counter value threshold corresponds to a threshold amount of time, and the counter value threshold is different for each of the plurality of requestors. Each of the plurality of request shapes is configured to separately output the request signal and a priority signal indicating a priority level of the request based on the base priority level, the counter value threshold, and a counter value.

Abstract: Responsive to selecting a particular queue from among at least two queues to place an incoming event into within a particular entry from among multiple entries ordered upon arrival of the particular queue each comprising a separate collision vector, a memory address for the incoming event is compared with each queued memory address for each queued event in the other entries in the at least one other queue. Responsive to the memory address for the incoming event matching at least one particular queued memory address for at least one particular queued event in the at least one other queue, at least one particular bit is set in a particular collision vector for the particular entry in at least one bit position from among the bits corresponding with at least one row entry position of the at least one particular queued memory address within the other entries.

Abstract: Disclosed herein is a controller architecture that pairs a controller with a NVM (non-volatile memory) storage system over a high-level, high speed interface such as PCIe. In one embodiment, the NVM storage system includes a bridge that communicates with the controller via the high-level interface, and controls the NVM via an interface (e.g., ONFI). The controller is provided a rich set of physical level of controls over individual elements of the NVM. In one embodiment, the controller is implemented in a higher powered processor that supports advanced functions such as mapping, garbage collection, wear leveling, etc. In one embodiment, the bridge is implemented in a lower powered processor and performs basic signal processing, channel management, basic error correction functions, etc. This labor division provides the controller physical control of the NVM over a fast, high-level interface, resulting in the controller managing the NVM at both the page and block level.

Abstract: A system-on-chip bus system and an operating method of the same are provided. The bus system includes a master device, a slave device and an interconnector coupled between the master device and the slave device. The interconnector includes a synchronization/compaction block to control traffic provided from a master device to a slave device. When a write request traffic and a corresponding write data traffic are all provided from the master device, the synchronization/compaction block may transfer the two traffics to the slave device.

Abstract: Systems and methods for adaptive bitrate streaming in which playback devices select streams based upon stream delay and channel rate in accordance with embodiments of the invention are disclosed. One embodiment is configured to select a first video stream from a set of alternative streams, where at least a plurality of the alternative streams are encoded to have an upper bound seek delay that is equal to or less than the upper bound seek delay of streams in the set of alternative streams that are encoded at a higher maximum bitrate, request chunks of the first video stream and store the requested chunks in the buffer, playback the buffered chunks, measure the channel data rate, and select a second video stream from the set of alternative streams, where the second video stream has a maximum bitrate that is less than the measured channel data rate.

Abstract: A multi-chip package includes first and second semiconductor chips each configured to perform first and second operations having different current consumptions. The first and second semiconductor chips perform the first operation in response to an enable control signal transmitted from one of the first and second semiconductor chips to the other and transmitted from the other back to the one.

Abstract: A method for setting addresses of slave devices in a communication network is provided. In the communication network, a master device identifies address-collided slave devices and requests the address-collided slave devices to return their unique identification data. The master device sets addresses of the address-collided slave devices so that each of the slave devices in the communication network has a different address from one another.

Abstract: An apparatus for operating a data bus system of a motor vehicle having data bus segments, at least one of the data bus segments is designed to switch from an active state to a rest state and vice versa. In a first step, a communication requirement is detected of a first control device of a first data bus segment in the rest state. If a communication requirement of the first control device is detected, the first data bus segment is brought from the rest state into the active state. If a communication requirement of the first control device with a second control device outside of the first data bus segment is detected, all other data bus segments of the data bus system outside of the first data bus segment that are in the rest state are additionally activated across the board.

Abstract: A system is disclosed that may compensate for bus timing that may vary over operating conditions of a bus. The system may include a communication bus, a first functional unit configured to transmit data via the communication bus, and a second functional unit configured to receive data via the bus. The first functional unit may transmit a first value via the communication bus to the second functional unit. The first functional unit may be further configured to assert a data valid signal responsive to a determination that a first time period has elapsed since the transmission of the first data value. The second functional unit may be configured to receive the first data value and sample the first data value dependent upon the data valid signal.

Abstract: A device can include a processor configured to write a first data structure to a memory, the first data structure comprising a list of at least one data channel; and a scheduler circuit comprising logic circuits responsive to the processor, the scheduler circuit configured to transfer data packets to the at least one data channel via a packet based serial data communication interface and according to the first data structure.

Abstract: A network node comprising at least one network interface the network node arranged to form network links to other network nodes through the or each network interface, each network link being to a neighboring one of the other network nodes, the network node arranged to determine whether data transmitted over the links to the relevant neighboring network nodes is successfully received. Should the network node make a first determination that data sent over a given network link to a neighboring node has not been successfully received, the network node temporarily disables the entry for that network link in a memory for a period of time, such that the network node does not send data to the neighboring node over the given network link during the period of time, but then subsequently re-enables the entry after the period of time has elapsed.

Abstract: A method, of configuring contacts of a receptacle based on determined conditions is disclosed. The method may include receiving, via contacts of a receptacle, a plug communicatively coupled to a peripheral device. The method may also include receiving, via a control channel communicatively coupled to one or more of the contacts, a signal related to conditions of the peripheral device including a first bus type and a second bus type of the peripheral device. The method may also include determining, via a controller communicatively coupled to the control channel, the conditions of the peripheral device. The method may also include configuring the contacts based on the determined conditions, wherein configuring the contacts comprises routing a first set of contacts corresponding to the first bus type to a first interface and routing a second set of contacts corresponding to the second bus type to a second interface.

Abstract: The present invention discloses an arbitration mechanism for controlling access of a plurality of nodes external to a shared resource, to which accesses by the number of nodes must be restricted, is applicable to any shared source in a computer or computer-controlled system. The present design delivers the following advantageous features. It provides localized arbitration to obtain resource access and localized self-management of resource mastery; eliminates resource seizure locally; it allows equal access to the share resource, encapsulate all four above features with the same circuit/protocol.

Abstract: A computer program product includes a tangible storage storing instructions for performing a method. The method includes: receiving a request at a channel subsystem in a host computer system to provide a channel path description for a channel path, the channel subsystem including a channel configured to be coupled to a control unit via the channel path, the channel configured to control information transfer over the channel path; and outputting a channel path description block from the channel subsystem to the operating system in response to the request, the channel path description block including channel path identification and description information, the channel path description block specifying whether the channel path supports a Fiber Channel protocol for commanding an I/O operation, the channel path description block specifying whether the channel path supports an extension to the Fiber Channel protocol based on the channel path supporting the Fiber Channel protocol.

Abstract: A microcontroller has a housing with external pins and an integrated debugging interface using only a single signal pin. In a method for operating a microcontroller as described above, the method includes the step of debugging or programming the microcontroller using only a single signal pin of the external pins.

Abstract: A protecting circuit for a basic input output system (BIOS) chip of a computer includes a platform controller hub (PCH), an inverting circuit connected to the PCH, a BIOS socket to connect the BIOS chip, and a controlling circuit connected between the inverting circuit and the BIOS socket. The PCH outputs a first signal or a second signal, and a third signal. The inverting circuit outputs an inverted signal with a level contrary to the first or second signal. The controlling circuit receives the first or second signal and the inverted signal, to output a processing signal to the BIOS socket, thereby controlling write-protection states of the BIOS chip.

Abstract: In one embodiment, the present invention includes a method for receiving requests from requestors in an arbiter, detecting that none of the requestors have a qualified request for at least one cycle of an arbitration round, and preventing a grant count reload of grant counters associated with the when at least one of the requestors has available grants for the arbitration round. Other embodiments are described and claimed.