Abstract: An island-based network flow processor (IB-NFP) integrated circuit includes rectangular islands disposed in rows. In one example, the configurable mesh data bus is configurable to form a command/push/pull data bus over which multiple transactions can occur simultaneously on different parts of the integrated circuit. The rectangular islands of one row are oriented in staggered relation with respect to the rectangular islands of the next row. The left and right edges of islands in a row align with left and right edges of islands two rows down in the row structure. The data bus involves multiple meshes. In each mesh, the island has a centrally located crossbar switch and six radiating half links, and half links down to functional circuitry of the island. The staggered orientation of the islands, and the structure of the half links, allows half links of adjacent islands to align with one another.

Abstract: Systems and methods for real-time control of a bus operating point in a portable computing device (“PCD”) are presented. An indication of an event occurring in a bus interface is used as an indicator of a mismatch between a resource request and a data throughput level that can be supported by the bus. A suitable mechanism for identifying the mismatch provides a cost effective and non-invasive solution that is generally applicable for all usage situations.

Abstract: Various embodiments of a method [800] of distributing configuration information within a predefined set of conjoined blades of a blade partition are described. In one embodiment, a configuration rule at a database for a predefined set of conjoined blades of a blade partition is accessed, wherein conjoined blades within the blade partition are coupled with management processors [805]. A portion of the configuration rule is compared with a hardware configuration of the blade partition [810]. The portion of the configuration information is an identification of the conjoined blades [810]. When the portion of the configuration rule correlates with the hardware configuration, the configuration rule is provided to the management processors of the blade partition [815].

Abstract: A multiprocessing system executes a plurality of processes concurrently. A process execution circuit (10) issues requests to access a shared resource (16) from the processes. A shared access circuit (14) sequences conflicting ones of the requests. A simulating access circuit (12) generates signals to stall at least one of the processes at simulated stall time points selected as a predetermined function of requests from only the at least one of the processes and/or the timing of the requests from only the at least one of the processes, irrespective of whether said stalling is made necessary by sequencing of conflicting ones of the requests. Thus, part from predetermined maximum response times, predetermined average timing can be guaranteed, independent of the combination of processes that is executed.

Abstract: Partitioning of a variable length scatter gather list including a processor for performing a method that includes requesting data from an I/O device comprising an I/O buffer. The requesting includes initiating a subchannel. The method further includes determining whether the subchannel supports data divisions by requesting SSQD data from the I/O device and inspecting at least one bit in the SSQD data. A determination is made whether the requested data includes a metadata block in response to determining that the subchannel support data divisions. Also, the subchannel is notified that the requested data includes the metadata block in response to determining that the requested data includes the metadata block. A location of storage is identified in an SBAL in response to notifying the subchannel.

Abstract: Embodiments of the invention provide a memory device that may be accessed by a plurality of controllers or processor cores via respective ports of the memory device. Each controller may be coupled to a respective port of the memory device via a data bus. Each port of the memory device may be associated a predefined section of memory, thereby giving each controller access to a distinct section of memory without interference from other controllers. A common command/address bus may couple the plurality of controllers to the memory device. Each controller may assert an active signal on a memory access control bus to gain access to the command/address bus to initiate a memory access.

Abstract: A multimode communication integrated circuit comprising baseband processing circuitry with a shared radio interface. Various aspects of the present invention may comprise a processor module adapted to perform various processing (e.g., baseband processing) in support of multimode communications. A first radio module may be communicatively coupled to the processor module through a common communication interface. A second radio module may also be communicatively coupled to the processor module through the common communication interface. The common communication interface may, for example, be adapted to communicate information over a communication bus that is shared between the processor module and a plurality of radio modules (e.g., the first and second radio modules).

Abstract: A microcontroller for a control unit, in particular for a vehicle control unit, includes a central processing unit (CPU), at least one interface-unspecific input module, at least one interface-unspecific output module, at least one routing unit and at least one arithmetic unit for processing interface-specific information. The microcontroller is configurable in such a way that the at least one interface-unspecific input module, the at least one interface-unspecific output module, the at least one routing unit and the at least one arithmetic unit for processing interface-specific information fulfill functions corresponding to one of multiple serial interfaces, in particular of SPI, UART, LIN, CAN, PSI5, FlexRay, SENT, IC2, MSC or Ethernet. In addition, the input module stores an entire input message frame of the input data and makes this available to the arithmetic unit or the central processing unit (CPU).

Abstract: Provided are a computer program product, system, and method for selecting Direct Memory Access (DMA) engines in an adaptor for processing Input/Output requests received at the adaptor. A determination is made of an assignment of a plurality of processors to the DMA engines, wherein each processor is assigned to use one of the DMA engines. I/O request related work for a received I/O request directed to the storage is processed by determining the DMA engine assigned to the processor processing the I/O request related work and accessing the determined DMA engine to perform the I/O related work.

Abstract: A data transmitting system, comprising: a processor; a first transmitting interface; a first transmitting apparatus; a second transmitting interface; a second transmitting apparatus and a signal transmitting line. The processor enters a power down mode when the first transmitting apparatus does not output data. The first transmitting generates a data transmitting indication signal when the processor is operated in the power down mode and the first transmitting apparatus has data to be output. The second transmitting apparatus generates a recovery signal according to the data transmitting indication signal, and transmits the recovery signal to the processor via the second transmitting interface. Thereby the processor goes back to a normal mode to control the first transmitting apparatus to output data.

Abstract: A method of communication between a master circuit and two slave circuits over a serial bus wherein: the two slave circuits simultaneously transmit their associated identifiers; the two slave circuits simultaneously transmit the inverse of these identifiers; and each slave circuit exploits the combinations present on the bus to determine an order of communication between the two circuits.

Abstract: A method is described for assigning payload data from a bus data packet to different sensor transmission devices, a bus control device being connected to a data bus of a vehicle designed for the simultaneous transmission of bus data packets (100) between multiple sensor transmission devices and the bus control device. The bus data packets include at least one signaling field and a payload data field having at least two payload data blocks. The method includes a step of reading in a bus data packet and a step of determining an assignment rule based on an action list. The action list includes multiple combinations in each case of one of multiple possible operating states for each sensor transmission device which uses the data bus.

Abstract: In a real-time application, one or more computational tasks execute according to a time schedule and use input data from input devices and/or output data from output devices. One or more of the input devices or output devices may be unscheduled devices that attempt to access the peripheral bus at unscheduled times. Such unscheduled bus access can cause the time schedule to become comprised. Various methods for arbitrating access to the bus to better integrate the bus access with the time schedule followed by the application are described.

Abstract: A method for coupling a first sensor to at least one second sensor is provided, the method including a step of transmitting a first signal from the first sensor to the at least one second sensor. Furthermore, the method includes a step of providing a second signal by way of the second sensor. The second signal is provided in response to the first signal, the second signal representing a measured value of the second sensor. Furthermore, the method includes a step of outputting a third signal for a control unit by way of the first sensor. The outputting of the third signal is carried out in response to the second signal, the third signal representing at least one measured value of the first sensor.

Abstract: A guaranteed rate port scheduler (GRPS) is used for serving multiple destination ports simultaneously without under-runs, even if the total bandwidth of the ports is more than the bandwidth capability of the device. Certain network protocols, such as Ethernet, do not allow “gaps” (called under-runs) to occur between bits of a packet on the wire. If a network device is transmitting packets to several such ports at the same time and the combined bandwidth of these ports is more than the device can source, under-runs begin to occur within the transmitted packets. The disclosed GRPS solves this problem by: (a) the GRPS serves only as many destination ports at a given time as can be “handled”, and (b) the GRPS fairly selects new destination ports to serve after every end-of-frame data packet transmission by effectively “de-rating” the statistical bandwidth of each destination port in proportion to the diminished capacity of the device.

Abstract: A computer program product includes a tangible storage storing instructions for performing a method. The method includes receiving a request at a channel subsystem in a host computer system from an operating system in the host computer system to provide a channel path description for a channel path, the channel subsystem configured to direct information flow between memory and the control unit via the channel path; and outputting from the channel subsystem to the operating system, a channel path description block including the channel path description for the channel path in response to the request. The channel path description block includes: a descriptor field (DESC) indicating that the channel path supports a Fiber Channel protocol for commanding an I/O operation; and an extension support indicator field (F) specifying whether the channel path supports an extension to the Fiber Channel protocol.

Abstract: Methods and structure for preemptively terminating Serial Attached Small Computer System Interface connections are provided. One exemplary embodiment includes an expander comprising multiple physical links, switching circuitry able to establish connections between end devices coupled with the expander through the physical links, and a connection manager. The connection manager is able to process an Open Address Frame from an end device, and to determine that the Open Address Frame requests a connection through a physical link that is already servicing an established connection. The connection manager is further able to determine that the Open Address Frame requests a higher priority connection than the established connection, and to direct one of the end devices utilizing the established connection to terminate the established connection based on the higher priority.

Abstract: A relational model may be used to encode primitives for each of a plurality of threads in a multi-core processor. The primitives may include tasks and parameters, such as buffers. The relationships may be linked to particular tasks. The tasks with the coding, which indicates the relationships, may then be used upon user selection to display a visualization of the functional relationships between tasks.

Abstract: Systems and methods for providing instant-on functionality on an embedded controller are disclosed. A method of providing instant-on functionality on a controller comprises an initial state, an intermediate state and a final state. The initial state comprises installing a first responder code, enabling the first responder code and enabling a timer interrupt service routine. The intermediate state comprises registering the first responder code as a timer interrupt service routine. The timer interrupt service routine initiates periodic processing. The final state comprises registering a steady-state interrupt service routine.

Abstract: A method to interact with a local USB device is disclosed. Messages are transmitted to a remote host controller driver from a host controller associated with the local USB device. Messages are received from the remote host controller driver for the host controller. In some embodiments, a transfer descriptor prototype is received from the remote host controller driver. A completed transfer descriptor is received from the remote host controller driver. The completed transfer descriptor and the transfer descriptor prototype are transformed into a modified transfer descriptor in part by using a collection of rules. The modified transfer descriptor is submitted to the local host controller without intervention from the remote host controller driver.

Abstract: A system and method for conveying data include the capability to determine whether a transaction request credit has been received at a computer module, the transaction request credit indicating that at least a portion of a transaction request message may be sent. The system and method also include the capability to determine, of a transaction request message is to be sent, whether at least a portion of the transaction request message may be sent and to send the at least a portion of the transaction request message if it may be sent.

Abstract: A memory management system and method include and use a cache buffer (such as a table look-aside buffer, TLB), a memory mapping table, a scratchpad cache, and a memory controller. The cache buffer is configured to store a plurality of data structures. The memory mapping table is configured to store a plurality of addresses of the data structures. The scratchpad cache is configured to store the base address of the data structures. The memory controller is configured to control reading and writing in the cache buffer and the scratchpad cache. The components are operable together under control of the memory controller to facilitate effective searching of the data structures in the memory management system.

Abstract: Systems and methods for configuring contacts of a first connector includes detecting mating of a second connector with the first connector and in response to the detection, sending a command over one of the contacts and waiting for a response to the command. If a valid response to the command is received, the system determines the orientation of the second connector. The response also includes configuration information for contacts in the second connector. The system then configures some of the other contacts of the first connector based on the determined orientation and configuration information of the contacts of the second connector.

Abstract: Circuits, methods, and apparatus that reduce the power consumed by transactions initiated by a number of USB host controllers. Peripheral devices on a number of USB networks are accessed in a coordinated manner in order to reduce power dissipated by a CPU and other circuits when reading data needed by the host controllers. The resulting memory reads are temporally clustered. This allows the CPU to process a greater number of requests each time it leaves a low-power state. As a result, the CPU may possibly remain in a sleep state for a longer period of time, thus saving power. This is accomplished at the host controller level by synchronizing the time frames used by each host controller in a system. The synchronizing signal may be one or more bits of a frame count provided by one host controller to a number of other frame controllers.

Abstract: A method for expanding input/output in an embedded system is described in which no additional strobes or enable lines are necessary from the host controller. By controlling the transitions of the signal levels in a specific way when controlling two existing data or select lines, an expansion input and/or output device can generate a strobe and/or enable signal internally. This internal strobe and/or enable signal is then used to store output data or enable input data. The host controller typically utilizes software or firmware to control the data transitions, but no additional wires are needed, and no changes are needed to existing peripheral devices. Thus, an existing system can be expanded when there are no additional control lines available and no unused states in existing signals.

Abstract: In accordance with an embodiment, a receiver includes a first state machine configured to be coupled to a bus. The first state machine is configured to determine that a first output signal is a first symbol if a first received bus signal transitions from a first bus state to a second bus state and stays in the second bus state for less than a first predetermined period of time, and the first output signal is a second symbol if the first received bus signal transitions from the first bus state to the second bus state and stays in the second bus state for at least the first predetermined period of time.

Abstract: An example disclosed is directed to a switch. The switch includes a communication interface and a discovery module. The discovery module is to receive a registration request for bulk discovery from an initiator device via the communication interface. The discovery module is further to receive a change indication specifying that a change has occurred in a fabric associated with the switch, and update a data model based on the received change indication to generate an updated data model. The discovery module then filters the updated data model to generate a filtered data model, and sends the filtered data model to the initiator device via the communication interface.

Abstract: An integrated circuit includes a bus; a processing unit configured to execute a user program; and a debugging circuit connected to the bus, the debugging circuit transferring a command in a command register to the processing unit via the bus in response to a command transfer request from the processing unit, wherein, when the processing unit halts the execution of the user program and makes a request for the command transfer request to the debugging circuit, the debugging circuit makes a response for freeing the use right of the bus from the processing unit in a period between the command transfer request and the command transfer operation.

Abstract: A memory bus connected module with context switching capability is described. The module can include a memory bus connection compatible with a memory bus socket, a plurality of offload processors attached to the module and connected to a memory bus, with each offload processor having a cache with an associated cache state, a context memory attached to the module and connected to the offload processors, and a scheduling circuit configured to direct a transfer of a cache state between at least one of the offload processors and the context memory.

Abstract: A processor arrangement is provided. The processor arrangement includes: a first processor; a plurality of second processors, each second processor including a bit-mask generator configured to generate a processor-specific bit-mask sequence; wherein the first processor includes a bit-mask generator configured to generate the processor-specific bit-mask sequences of the second processors; wherein the first processor is configured to bit-mask a data bit sequence to be transmitted to one second processor of the plurality of second processors using a processor-specific bit-mask sequence specific to the one second processor, to thereby generate a processor-specific bit-masked data sequence to be transmitted to the one second processor.

Abstract: A circuit comprising: a device determiner configured to, in a first mode of operation, receive a device selection signal via at least one of: at least one control line and at least one signal line; and a device router configured to, in a second mode of operation, route signals between the at least one of: at least one control line and at least one signal line and at least one device dependent on the device selection signal.

Abstract: A transaction processing method is disclosed to solve the issue of multiple producers (software and hardware) and one or more consumers operating in a peer or hierarchical system. The transaction processing method is a deterministic method operable in a system having any number of producers. The producers themselves may be any combination of hardware and software and may be part of peer or hierarchical systems.

Abstract: A method comprises selecting a starting point on a map of equalization coefficients and measuring an eye height of a signal transmitted using the set of equalization coefficients associated with the starting point and an eye height associated with each adjacent point on the map relative to the starting point. The eye height associated with an adjacent point is based on a signal transmitted using the set of equalization coefficients associated with the adjacent point. The method also comprises walking on the map in a first direction from the starting point to the adjacent point associated with the greatest eye height, wherein the eye height associated with the adjacent point is greater than or equal to the eye height associated with the starting point.

Abstract: A management engine may be used to trap configuration cycles during the boot process and thereafter in response to operating system enumeration. As a result, a virtual bus device can be created. The bus device may be used to provision software to the platform even when the operating system is corrupted or non-functional.

Abstract: A method, a system, an apparatus, and a computer program product for allocating resources of one or more shared devices to one or more partitions of a virtualization environment within a data processing system. At least one user defined resource assignment is received for one or more devices associated with the data processing system. One or more registers, associated with the one or more partitions are dynamically set to execute the at least one resource assignment, whereby the at least one resource assignment enables a user defined quantitative measure (number and/or percentage) of devices to operate when the one or more transactions are executed via the partition. The system enables the one or more devices to execute one or more transactions at a bandwidth/capacity that is less than or equal to the user defined resource assignment and minimizes performance interference among partitions.

Abstract: A method of performing collective communication in a collective communication system includes processing nodes, including: determining whether a command message, regarding one function among a broadcast function, a scatter function, and a gather function, is generated by a processor; determining a transmission order between the processing nodes by giving transmission priorities to processing nodes that do not communicate, based on a status of each of the processing nodes if it is determined that the command message regarding the one function among the broadcast function, the scatter function, and the gather function, is generated by the processor; and performing communication with respect to the command message based on the determined transmission order.

Abstract: An example embodiment includes an abstraction device including a mapping platform, a vehicle transceiver, and a mobile device transceiver. The mapping platform is configured to convert input data messages formatted in a vehicle-specific format to output data messages formatted in a standard mobile device format. The mapping platform is further configured to convert input data messages formatted in the standard mobile device format to output data messages in the vehicle-specific format. The input data messages may have any of multiple data message types, which are communicated from multiple mobile device subsystems, and multiple vehicle subsystems. The vehicle transceiver is configured to transmit the output data messages formatted in the vehicle-specific format to a vehicle via a controller area network (CAN) bus of the vehicle. The mobile device transceiver is configured to transmit the output data messages formatted in the standard mobile device format to a mobile device.

Abstract: An apparatus including a first circuit and a second circuit connected in parallel to the bidirectional communication path, and one of the first and second circuits being an active circuit monitoring a value of the data signal on the bidirectional communication path while the other of the first and second circuits being a passive circuit that is not monitoring the value of the data signal. The active circuit initially starts in a low gain state, but on detection of a transition by transition detection circuitry, it enters a high gain state where the switch circuitry disconnects the transition detection circuitry from the bidirectional communication path, and the drive circuitry is activated in order to drive the data signal on the bidirectional communication path to the opposite value. Once the data signal has been driven to the opposite value, the active circuit and the passive circuits switch states.

Abstract: A host controller is suitable for transferring data in transactions, each transaction being described by a transfer descriptor, and the transactions include split transactions. The transfer descriptor for a split transaction includes a bit which may be set to indicate whether the split transaction is a start split or a complete split transaction, and, once a transaction comprising split transactions has been started by a first split transaction, subsequent split transactions are generated automatically until the transaction is complete.

Abstract: Disclosed herein is a controller architecture that pairs a controller with a NVM (non-volatile memory) storage system over a high-level, high speed interface such as PCIe. In one embodiment, the NVM storage system includes a bridge that communicates with the controller via the high-level interface, and controls the NVM via an interface (e.g., ONFI). The controller is provided a rich set of physical level of controls over individual elements of the NVM. In one embodiment, the controller is implemented in a higher powered processor that supports advanced functions such as mapping, garbage collection, wear leveling, etc. In one embodiment, the bridge is implemented in a lower powered processor and performs basic signal processing, channel management, basic error correction functions, etc. This labor division provides the controller physical control of the NVM over a fast, high-level interface, resulting in the controller managing the NVM at both the page and block level.

Abstract: A communication device includes a transmission circuit that transmits a transmission signal under a certain transmission condition, a reception circuit that receives a reception result of the transmission signal under a certain reception condition and the certain reception condition, and an adjustment circuit that transmits information used to adjust the reception condition based on the reception result and the reception condition from the transmission circuit.

Abstract: To improve processing performance of an information processing device as a whole by controlling priority in units of processes. There are provided a bus for data transfer and a plurality of function modules each having a processing function performing processing in units of processes and capable of issuing a data transfer request for the bus. Further, there is provided a process identification information holding unit capable of holding process identification information set for each of the processes in association with the function module performing processing of the process. Furthermore, there is provided a bus arbiter determining a priority order of processing for each piece of the corresponding process identification information for each data transfer request from the function module and arbitrating contention of data transfer requests for the bus according to the priority order. Processing performance is improved by performing priority order control in units of processes.

Abstract: Methods and apparatus relating to fast deskew when exiting a low-power partial-width high speed link state are described. In one embodiment, an exit flit on active lanes and/or a wake signal/sequence on idle lanes may be transmitted at a first point in time to cause one or more idle lanes of a link to enter an active state. At a second point in time (following or otherwise subsequent to the first point in time), training sequences are transmitted over the one or more idle lanes of the link. And, the one or more idle lanes are deskewed in response to the training sequences and prior to a third point in time (following or otherwise subsequent to the second point in time). Other embodiments are also disclosed and claimed.

Abstract: Methods and apparatus for termination of signal lines coupled to a number of memory devices are disclosed. One such method includes adjusting an input impedance of one or more terminals of an interface of a memory device in response to the memory device receiving a particular address. One such apparatus includes memory devices configured to selectively adjust an input impedance seen by one or more of the signal lines in response to receiving a particular address.

Abstract: Disclosed embodiments may include a circuit having a plurality of data terminals, no more than two pairs of differential data strobe terminals associated with the plurality of data terminals, and digital logic circuitry. The digital logic circuitry may be coupled to the data terminals and configured to use the no more than two pairs of differential data strobe terminals concurrently with the plurality of data terminals to transfer data. Other embodiments may be disclosed.

Abstract: It may be difficult to give bus right to a bus master that cannot output a bus request signal when a bus arbitration apparatus is ready to grant bus permission precisely in a ratio of a preset number of times of the bus acquisition. The bus arbitration apparatus operates to wait until bus request signals of bus masters that have not performed transfers of the preset number of times of the bus acquisition are output while a bus slave operates.

Abstract: A system and method can support message pre-processing in a distributed data grid. The system can associate a message bus with a service thread on a cluster member in the distributed data grid. Furthermore, the system can receive one or more incoming messages at the message bus using an input/output (I/O) thread, and pre-process said one or more incoming messages on the I/O thread before each said incoming message is delivered to a service thread in the distributed data grid. Additionally, the system can take advantage of a pool of input/output (I/O) threads to deserialize inbound messages before they are delivered to the addressed service, and can relieve the bottleneck that is caused by performing all message deserialization in a single threaded fashion before the message type can be identified and offloaded to the thread-pool within the distributed data grid.

Abstract: An L2 cache, method and computer program product for transferring an inbound bus operation to a processor side handling machine. The method includes a bus operation handling machine accepting the inbound bus operation received over a system interconnect, the bus operation handling machine identifying a demand operation of the processor side handling machine that will complete the bus operation, the bus operation handling machine sending the identified demand operation to the processor side handling machine, and the processor side handling machine performing the identified demand operation.

Abstract: Methods and structure are provided for representing ports of a Serial Attached SCSI (SAS) expander circuit within routing memory. The SAS expander includes a plurality of PHYs and a routing memory. The routing memory includes entries that each indicate a set of PHYs available for initiating a connection with a SAS address, and also includes an entry that represents a SAS port with a start tag indicating a first PHY of the port and a length tag indicating a number of PHYs in the port. The SAS expander also includes a Content Addressable Memory (CAM) including entries that each associate a SAS address with an entry in the routing memory. Further, the SAS expander includes a controller that receives a request for a SAS address, uses the CAM to determine a corresponding routing memory entry for the requested SAS address, and selects the port indicated by the corresponding routing memory entry.

Abstract: A system-on-chip bus system and an operating method of the same are provided. The bus system includes a master device, a slave device and an interconnector coupled between the master device and the slave device. The interconnector includes a synchronization/compaction block to control traffic provided from a master device to a slave device. When a write request traffic and a corresponding write data traffic are all provided from the master device, the synchronization/compaction block may transfer the two traffics to the salve device.