Abstract: A circuit arrangement for a data processing system is configured to process data in a plurality of modules. The circuit arrangement is configured such that each module is provided with at least one clock pulse, a time base and a base of at least one additional physical variable. The circuit arrangement also comprises a central routing unit to which the plurality of modules are coupled and via which the plurality of modules can periodically exchange data amongst themselves, based on the time base and/or the base of other physical variables. Each module is configured independently and parallel to other modules of the plurality of modules in order to process data. The circuit arrangement is employed in a corresponding method.

Abstract: Memory access alignment in a double data rate (‘DDR’) system, including: executing, by a memory controller, one or more write operations to a predetermined address of a DDR memory module, including sending to the DDR memory module a predetermined amount of data of a predetermined pattern along with a data strobe signal; executing, by the memory controller, a plurality of read operations from the predetermined address of the DDR memory module, including capturing data transmitted from the DDR memory module; and determining, by the memory controller, a read adjust value and a write adjust value in dependence upon the data captured in response to the read operations.

Abstract: A card can be communicationally coupled to a storage device. The card can then cause the storage device to perform stand-alone tasks without a computing device. The card can invoke instructions already present in the firmware of the storage device or the card can first copy instructions to the firmware and then invoke them. The card can cause the storage device to perform actions, such as a secure erase, and the storage device can remain inaccessible until such actions are performed, even if power is interrupted. The card can also receive information from the storage devices and then use that information with a new storage device to, for example, enable the new storage device to take the place of, and reconstruct the data of, the old storage device in a storage array directly from other storage devices in the array and without burdening a computing device or array controller.

Abstract: In the processor device connected to the endoscope, the imaging signal transmitted in serial from an imaging chip of the endoscope is converted by an S/P converter to parallel data, and is then decoded by an 8B10B decoder. When data corruption occurs due to noise or the like during transmission of the imaging signal and normal pixel data cannot be obtained due to decode error at an 8B10B decoder, that pixel data is interpolated with pixel data of a peripheral part in an inner memory of an image processing circuit.

Abstract: The present invention relates to a digital broadcasting receiver for a magic remote control and a method of controlling the receiver. The digital broadcasting receiver for the magic remote control according to an embodiment of the present invention may include: a receiving unit receiving a control signal, wherein the control signal includes a first signal representing that a button of the magic remote control is pressed, a second signal representing the drag state of the magic remote control while the button of the magic remote control is pressed, and a third signal representing that the button of the magic remote control is released; a display unit; a processor; and a platform.

Abstract: A protocol for optimizing the use of coded transmissions such as over wireless links. In this technique, interframes are split into segments selected to be an optimum size according to transmission characteristics of the radio channel. The inverse process is applied at the receiver. Using this scheme, segments containing erroneous data may be resent.

Abstract: In one embodiment, a storage system comprises: a first type interface being operable to communicate with a server using a remote memory access; a second type interface being operable to communicate with the server using a block I/O (Input/Output) access; a memory; and a controller being operable to manage (1) a first portion of storage areas of the memory to allocate for storing data, which is to be stored in a physical address space managed by an operating system on the server and which is sent from the server via the first type interface, and (2) a second portion of the storage areas of the memory to allocate for caching data, which is sent from the server to a logical volume of the storage system via the second type interface and which is to be stored in a storage device of the storage system corresponding to the logical volume.

Abstract: In a method of processing display data, a host device (e.g. a PC) determines display data to send to a remote device and compresses it, and determines processing resources required at the remote device to decompress the compressed display data. The host sends the compressed display data and control information regarding the required processing resources data to the remote device, and the remote device adjusts its processing resources based on the control information, saving energy. The required processing resources can be the number of processing units, clock speed, or operating voltage required by the remote device. The host may determine the required resources for each display frame. The remote device may send details of its processing capabilities to the host.

Abstract: Some media applications use media that contains multiple types of media components in it and media sources with access to this media must send each type of media component to one or more media rendering destination devices. Furthermore there may be multiple destinations that can receive a particular type of media component and the media must be received at each destination without losses. This invention describes a two tier packet buffer structure at the media source with primary and virtual packet buffers that ensures minimal memory use at the media source and minimal network use. Furthermore the use of a sliding window with each virtual packet buffer associated with each destination, independently keeps control and track of destination state, ensuring the correct receipt of media data at each destination.

Abstract: In some embodiments, a switch fabric system includes multiple access switches configured to be operatively coupled to a switch fabric. The multiple access switches include multiple ports each to be operatively coupled to a peripheral processing device. A first set of ports from the multiple ports and a second set of ports from the multiple ports are managed by a first network control entity when the switch fabric system is in a first configuration. The first set of ports is managed by the first network control entity and the second set of ports is managed by a second network control entity when the switch fabric system is in a second configuration. The second network control entity is automatically initiated when the system is changed from the first configuration to the second configuration.

Abstract: An electronic device includes a set of programming terminals for receiving corresponding programming signals, and assignment circuitry for assigning an address to the electronic device according to the programming signals. The assignment circuitry includes circuitry for providing a set of comparison signals, with at least part of the comparison signals that is variable during a non-zero comparison interval, and comparison circuitry for determining the address according to a comparison between the programming signals and the comparison signals during the comparison interval.

Abstract: Dynamically sharing information among a plurality of adapters in a multipath input/output (MPIO) system, selecting one of the adapters to receive an input/output request based on the shared information, and sending the input/output request to that adapter.

Abstract: In a method for enabling transmission of larger data quantities relatively rapidly in a data network, the sent data frames have a logical structure according to CAN Specification ISO 11898-1, the bit length in time within a data frame being able to assume at least two different values; for a first specifiable range within the data frame, the bit length in time being greater than, or equal to a specified minimum value of approximately one microsecond and in at least one second specifiable range within the data frame the bit length in time compared to the first range is at least halved, preferably less than halved; the change of the bit length in time being implemented by using at least two different scaling factors for setting the bus time unit relative to a shortest time unit or the oscillator clock pulse during running operation.

Abstract: Methods, systems and computer readable storage medium embodiments for communicating over a data bus include, determining a number of changes in bit value in respective bit positions between a previous bit string and a current bit string, transmitting either the current bit string in an inverted form over the data bus if the determined number of changes in bit value exceeds a threshold or the current bit string in non-inverted form if the determined number of changes in bit value does not exceed a threshold, and transmitting an additional at least one bit along with the current bit string having a logic value that indicates whether the current bit string is in an inverted form or non-inverted form. Methods, systems, and computer readable storage medium embodiments for receiving bit strings over a bus are also disclosed.

Abstract: A message is simultaneously broadcast to multiple systems on a 1-wire bus. A first addressed communication session is established between a microprocessor and a first 1-wire I/O expander via a 1-wire bus, where the first 1-wire I/O expander is electrically coupled to a first system. The first 1-wire I/O expander is placed into “fast access mode”, and then removed from the 1-wire bus by opening a switch to the 1-wire bus. A second addressed communication session is established between the microprocessor and a second 1-wire I/O expander before the switch recloses, where the second 1-wire I/O expander is electrically coupled to a second system. The second 1-wire I/O expander is then placed into “fast access mode”. In response to the timer expiring and the switch reclosing, an unaddressed message is broadcast from the microprocessor to the first and second systems via the first and second 1-wire I/O expanders.

Abstract: Systems, devices, memory controllers, and methods for controlling memory are described. One such method includes activating a memory unit of a memory device; after activating the memory unit, providing a command to the memory device; and returning the memory unit to a previous state if the command does not indicate a target memory volume, wherein the memory unit remains active if the command indicates a target memory volume associated with the memory unit.

Abstract: An electronic assembly has a plurality of functional units each including a board element populated with electronic modules. The board elements are connected to one another in terms of signaling via a contact board. An assembly having a high degree of communication flexibility in conjunction with favorable production costs can be provided if it contains a communication unit connected to the contact board directly by data lines. The communication unit is populated with electronic components in such a way that it serves as a communication interface for modules of the board elements.

Abstract: A data communications system is disclosed having at least one Legacy cloud coupled to at least one Beta cloud. The system further having at least one BOSS node and at least one border node. A method for ensuring compatibility is disclosed comprising determining when the BOSS node is idle, determining whether the last packet transmitted by any border node was an Alpha format packet if the BOSS node is idle, and unlocking the Legacy cloud if the last packet transmitted by the border node was not an Alpha format packet.

Abstract: An optoelectronic device includes a packaged part and a core component. The core component includes a chip subcarrier and an optoelectronic chip. The device also includes a connecting plate that forms a coplanar waveguide transmission line together with the ground through a high-frequency transmission line and an isolation dielectric. The coplanar waveguide transmission line and a low-frequency line are connected to the packaged part and the core component and are configured to transmit a high-frequency signal and a low-frequency signal between the packaged part and the core component.

Abstract: A reconfigurable high speed memory chip module includes a type of memory cell array group, a first transmission bus, and a logic unit. The type memory cell array group includes multiple memory cell array integrated circuits (ICs). The first transmission bus coupled to the type memory cell array group has a first programmable transmitting or receiving data rate, a first programmable transmitting or receiving signal swing, a first programmable bus width, and a combination thereof. The logic unit is coupled to the first transmission bus for accessing the type memory cell array group through the first transmission bus.

Abstract: Novel method and system for distributed database ray-tracing is presented, based on modular mapping of scene-data among processors. Its inherent properties include matching between geographical proximity in the scene with communication proximity between processors.

Abstract: A programmable logic controller (PLC) system, and more particularly, a data processing apparatus and method in the PLC system are provided. In the data processing method in a programmable logic controller (PLC) system, first dummy code data is output to an area having a chip selection signal for valid data output. The valid data is output after the first dummy code data is output. And second dummy code data is output when the valid data output is completed.

Abstract: Systems and methods of operating a serial interconnect interface provide for generating a pulse in response to a state change in a data signal of the serial interface interconnect, and transmitting the pulse from a physical layer of the serial interconnect interface to a link layer of the serial interconnect interface. The duration of the pulse can be selected based on whether the state change corresponds to an end of packet (EOP) condition. In addition, the data signal may include a non return to zero invert (NRZI) encoded signal, wherein the pulse is part of a digital NRZI signal.

Abstract: An apparatus includes a semiconductor device that includes a multi-ported three-dimensional (3D) memory. The multi-ported 3D memory includes multiple memory cells arranged in multiple physical levels above a substrate. The multi-ported 3D memory includes circuitry associated with operation of the multiple memory cells.

Abstract: A printing system including a printer for storing a setup program for installing a printer driver and an information processing apparatus, wherein the information processing apparatus starts up the setup program acquired from the printer, when the printer driver is installed, identifies an attribute of an OS running on the information processing apparatus, creates a port having a port name according to a predetermined format according to the identified attribute of the OS, and installs the printer driver.

Abstract: A power supply, and a method of controlling the power supply, in which more or less power capacity of the power supply is activated depending on the state of a digital data signal on a data bus. The power supply has a control circuit which detects the number of “zero” bits present on the data bus, and responsively activates one or more of a plurality of power supply circuits such as charge pump circuits. The outputs of the charge pump circuits are mutually connected to a driver adapted to program memory cells of a flash memory circuit. A charge pump apparatus and a memory integrated circuit are also described.

Abstract: A high speed memory chip module includes a type of memory cell array group and a logic unit. The type memory cell array group includes multiple memory cell array integrated circuits (ICs), and each of the memory cell array ICs has a data bus and at least one memory cell array, and corresponds to first metal-oxide-semiconductor field-effect transistor (MOSFET) gate length corresponding to a first MOSFET process. The logic unit accesses the type of memory cell array group through a first transmission bus, where bus width of the first transmission bus is wider than bus width of the data bus of each of the memory cell array ICs. Corresponding to a second MOSFET process, the logic unit has a second MOSFET gate length which is shorter than the first MOSFET gate length.

Abstract: A test system may include test stations for testing a device under test. The test stations may each include test equipment that may be connected to a device under test using a test cable. The test cable may include a status indicator to indicate when tests have been passed or have failed. A first connector at one end of the test cable may be coupled to the test equipment. A second connector at an opposing end of the test cable may be coupled to the device under test. Communications through the first connector may use a first communications protocol. Communications through a first set of contacts in the second connector may use the first communications protocol. Communications through a second set of contacts in the second connector may use a second communications protocol.

Abstract: Technologies and implementations for improving life of a solid state storage device are generally disclosed.

Abstract: A system and apparatus are described for providing greater flexibility and performance in a mixed-signal array through improved and highly configurable routing, control elements and signal processing capabilities.

Abstract: One or more switches in an occupancy sensor are enabled. When a switch is enabled, a reduction timer measuring a reduction time delay is initiated when an occupancy condition is detected by an occupancy sensor. In addition, one or more outputs controlled by the reduction timer are activated so that a signal is sent to a control system to notify the control systems of the occupancy condition. When the reduction time delay expires, the outputs of the occupancy sensor that are controlled by the reduction timer are deactivated, and so the outputs cease sending the signal to the control system. As a result, the control systems initiate their own internal time delays sooner.

Abstract: An apparatus includes a semiconductor device that includes a three-dimensional (3D) memory. The 3D memory includes multiple memory cells arranged in multiple physical levels above a substrate. The 3D memory includes circuitry associated with operation of the multiple memory cells and includes a serializer/deserializer interface.

Abstract: A motor driving device includes a communication path selection unit, to which operation command information for controlling driving of a motor is input in a serial data format or a parallel data format via a common input path, a communication unit which includes a serial interface unit for the serial data format and a parallel interface unit for the parallel data format, and outputs a control signal based on the operation command information input via the communication path selection unit, and a driving control unit which controls driving of the motor based on the control signal. The communication path selection unit selects between outputs path to the serial interface unit and the parallel interface unit, which corresponds to the data format of the input operation command information, and outputs the input operation command information to the serial interface unit or the parallel interface unit through the selected output path.

Abstract: A DMA controller allocates space at a buffer to different DMA engines based on the length of time data segments have been stored at a buffer. This allocation ensures that DMA engines associated with a destination that is experiencing higher congestion will be assigned less buffer space than a destination that is experiencing lower congestion. Further, the DMA controller is able to adapt to changing congestion conditions at the transfer destinations.

Abstract: A method of providing a gift registry service over a distributed network of computers. The method includes the steps of running a gift registrar application on at least one gift registry site, running a gift registration agent application on at least one goods or services provider (SP) site, a gift registrant accessing the at least one SP site and making a gift selection from the site, the gift registration agent application sending the gift selection to the gift registrar application, gift registrar application storing the gift selection as an update to a wish list in a wish list data memory structure accessible to the at least one gift registry site, and a gift purchaser accessing the stored wish list from a site on the distributed network remote from any gift registry site.

Abstract: A host apparatus, into which a card having a nonvolatile semiconductor memory is inserted, issues a check command to the card. The check command instructs to send information on whether the card supports a termination process in which the card shifts into a state ready for a stop of power supply from the host apparatus.

Abstract: A signal transmission method for a USB interface and an apparatus thereof are provided. The method includes: receiving a first USB signal sent from a sending terminal, processing the first USB signal into a USB-like signal, and transmitting the USB-like signal via a networking cable; receiving the USB-like signal, processing the USB-like signal into a second USB signal, and sending the second USB signal to a receiving terminal. According to the embodiments of the present invention, the first USB signal is processed into a USB-like signal which is similar to the USB signal, the USB-like signal is transmitted via a networking cable, and the USB-like signal is processed into a second USB signal. The transmission process does not require converting the USB signal into a networking-cable signal which is to be transmitted via a networking cable, thereby avoiding conversion between protocols, and simplifying the entire transmission process.

Abstract: In one embodiment, a semiconductor integrated code (SIC) may be provided in a binary format by a processor manufacturer. This SIC may include platform independent code of the processor manufacturer. Such code may include embedded processor logic to initialize the processor and at least one link that couples the processor to a memory, and embedded memory logic to initialize the memory. Other embodiments are described and claimed.

Abstract: A storage array, a storage system, and a data access method. A data access method of a storage device includes: transferring data input from a user interface chip to a non-volatile storage device through a peripheral component interconnect express (PCIE) link, where the user interface chip and the non-volatile storage device are connected to the PCIE link, and the non-volatile storage device includes a memory and a non-volatile storage medium; writing the data to the memory of the non-volatile storage device; and writing the data written in the memory of the non-volatile storage device to the non-volatile storage medium. The technical solutions provided by the embodiments of the present disclosure are advantageous for reducing occupation of PCIE links due to data access and improving system performance.

Abstract: A communication system includes a first interface module which can be coupled to a first logic unit and a second interface module which can be coupled to a second logic unit. The first and second interface modules are interconnected by a virtual channel over a routing network. The first interface module is configured to receive messages from the first interface module and to send the received messages over the virtual channel to the second interface module. The second interface module is configured to transmit the received messages to the second logic unit. The second interface module is further configured to receive a processing complete signal from the second logic unit when the received messages have been processed in the second logic unit and is further configured to send an acknowledgement signal to the first interface module after reception of the processing complete signal. Further a communication method is provided.

Abstract: A non-volatile memory device uses division addressing scheme and N address input terminals. A address decoder of the non-volatile memory device simultaneously activates a row select signal and a column select signal by synchronizing a first N-bit address signal and a second N-bit address signal sequentially input after the first N-bit address signal.

Abstract: According to one embodiment, a data transfer control device complying with a communication protocol which executes an update of information from an attachment device in a predetermined area of a system memory, the device includes a receiving part receiving the information from the attachment device, a transferring part transferring the information in the predetermined area, the information from the transferring part overwritten in the predetermined area sequentially, and a determining part inhibiting a transfer of the information in the transferring part to omit the update of the information in the predetermined area.

Abstract: Methods, systems, apparatuses, and computer-readable media for controlling components connected to and/or otherwise associated with a data bus are presented. According to one or more aspects of the disclosure, a plurality of processing devices having data bus management capability and at least one data bus associated with the plurality of processing devices may be identified. Subsequently, an inter-processor communication (IPC) layer for communication between the plurality of processing devices and the at least one data bus may be established over a messaging layer utilized by the at least one data bus. At least one component associated with the at least one data bus may then be controlled via the IPC layer using at least one of the plurality of processing devices.

Abstract: Snooping in SAS expander networks is disclosed. Ports in a SAS expander may include snoop circuitry and a snoop tap which allows snoop data to be diverted for snooping prior to any significant transformation of the traffic by the regular port logic. Furthermore, the snoop circuitry can receive OOB signaling and convert it to K characters for transmission through the SAS network and subsequent analysis by a protocol analyzer. The ports and cascades in the expander network can be configured to create snoop paths to enable snoop data to be passed through the network to locations where a protocol analyzer can be easily attached. With SAS snoop ports, there is no disruption to the system. Because only a copy of the data is routed to the analyzer, there is no change to the original signal path and latency is identical with or without the analyzer.

Abstract: A method for encapsulating functions for application programming interface in a cloud environment is disclosed. The method includes the steps of: A. providing an API supported by a driver; B inheriting the API as a new class if the API is usable for a service device in a computing node environment; C. augmenting extending function(s) for the service device to the driver; and D. repackaging the driver to conform to the inherited API.

Abstract: A package structure includes a networking unit including a plurality of switches/routers and a plurality of network interface units coupled to the plurality of switches/routers, and an interposer including a plurality of metal connections. The interposer is substantially free from functional elements built therein. A functional element is outside of, and bonded onto, the interposer, wherein the functional element is electrically coupled to the networking unit through the plurality of metal connections.

Abstract: Apparatuses and methods for driving input data signals onto signal lines as output data signals are disclosed. An example apparatus includes a detection circuit, a driver adjust circuit, and a data driver. The detection circuit is configured to detect a characteristic(s) of a group of input data signals to be driven onto adjacent signal lines. A characteristic could be, for example, a particular combination of logic levels and/or transitions for the group of input data signals. The driver adjust circuit is configured to provide a driver adjustment signal based at least in part on a detection signal, that is provided by the detection circuit. A data driver is configured to drive a respective one of the group of input data signals as a respective one of the output data signals, wherein the data driver is adjusted based at least in part on the driver adjustment signal.

Abstract: A switch includes network ports and a network processor with a fabric interface that provides SerDes (Serializer/Deserializer) channels. The network processor divides each packet received over the network ports into cells and distributes the cells across the SerDes channels. Fabric ports of the switch communicate with the fabric interface to transmit cells to and receive cells from the fabric interface. The switch is selectively configurable as a standalone switch by connecting each fabric port of the switch to another of the fabric ports of the switch, as a member of a switch stack by connecting each fabric port of the switch to a different other switch through one fabric port of that other switch, or as a member of a distributed fabric system by connecting each fabric port of the switch to a different scaled-out fabric coupler (SFC) chassis by an SFC fabric port of that SFC chassis.

Abstract: A method for offloading Fiber Channel transmit data in an I/O operation. The transmit data includes Fiber Channel sequences, each Fiber Channel sequence includes multiple frames. The method includes generating a single transmit sequence request descriptor for transmitting all of the plurality of frames; creating an Ethernet header, a FCoE encapsulation header, and a Fiber Channel header for each frame in response to information in the transmit sequence request descriptor; creating start of frame and end of frame delimiters; inserting data into each frame; computing Fiber Channel CRC and Ethernet FCS for each frame; and transmitting the plurality of frames over a network. In each of the plurality of frames, the Ethernet header precedes the FCoE encapsulation header, which precedes the Fiber Channel header, which precedes the data. The data is followed by the Fiber Channel CRC, which is followed by the Ethernet FCS.

Abstract: This invention relates to a method of associating or re-associating devices in a control network including control zones to respective zone controllers (ZCs) controlling the control zones. In a first step, an associating or re-associating timer (ZC_REASSC_TIMER) window is initialized at the (ZCs) defining the time during which said associating or re-associating of the devices takes place. In a second step, during the (ZC_REASSC_TIMER) window zone specific information (ZN_SPEC) message sage is transmitted, the (ZN_SPEC) message including information about the devices expected to be in the zones controlled by the (ZCs). In a third step, it is compared whether the zone specific information contained in the (ZN_SPEC) received by the devices includes device specific information that match with local device specific information associated to the devices.