Abstract: Methods and systems for analyzing bus traffic in a target device, such as a system on-a-chip (SOC) comprises capturing a processor event and generating an interrupt based on a threshold associated with the processor event. Based on at least the interrupt, a instruction pointer associated with the processor event that generated the interrupt is identified. An instruction analyzer identifies a memory address of the instruction associated with the processor event that generated the interrupt. At least the processor event and a associated instruction information are collected by a sample collector and transferred to a host for performance profiling.

Abstract: A flexible-width peripheral register mapping is disclosed for accessing peripheral registers on a peripheral bus.

Abstract: A dual host system and method with back to back non-transparent bridges and a proxy packet generating mechanism. The proxy packet generating mechanism enables the hosts to send interrupt generating packets to each other.

Abstract: Non-address data is received for transmission on a non-transitory communication medium communicably coupling a plurality of devices, wherein the communication medium includes an address component and a data transport component separate from the address component. At least a portion of the non-address data is inserted into a portion of an address command. An indicator is set in the address command to notify a receiver that the information received in the address command over the address component is not associated with a memory address. The address command containing the non-address data is then sent over the address component of the communication medium.

Abstract: A bus protocol compatible device includes an encoder having an input for receiving a local clock signal, and an output, a multiplexer having a first input for receiving a reference clock signal, a second input coupled to said output of said encoder, a control input for receiving a select signal, and an output, and a driver having an input coupled to said output of said multiplexer, and an output for coupling to a bus protocol link.

Abstract: A storage appliance system is disclosed which may include at least one application server for locally executing an application, and one or more storage servers in communication with the application server for I/O transmission therebetween. Also disclosed are an application server, a method, and a computer program product.

Abstract: A computer system arrangement for minimizing communication and integration complexity between a plurality of software applications having each an individual data model defining an individual set of application parameters, includes a bus arrangement having connections to each one of said plurality of applications, the bus being arranged to interpret between each application and to orchestrate incoming and outgoing requests from each application, the bus arrangement including, a generic information model defining a set of generic parameters in relation to the application parameters of each application, an adaptor together with said generic information model, in connection with an incoming request, arranged to map parameters of that individual data model to said generic parameters, a device arranged to transfer the mapped generic information model together with the request to a process execution engine, which includes a device arranged to handle the request to identify a corresponding adaptor to which the reques

Abstract: Novel method and system for distributed database ray-tracing is presented, based on modular mapping of scene-data among processors. Its inherent properties include matching between geographical proximity in the scene with communication proximity between processors.

Abstract: Systems and methods that implement communication of error information on a bus, including a bus having a small number of pins are disclosed. In one embodiment, an apparatus includes an interface circuit configured to couple to a bus and one or more sideband signals. The sideband signals may be used to communicate error information such as parity information for a bus that does not otherwise have this capability. In some embodiments, parity information may be driven on the bus during a portion of a bus transaction corresponding to unused address bits.

Abstract: Embodiments of the present invention disclose a peripheral component interconnect express interface control unit. The unit includes a P2P module, configured to receive a first TLP from a RC or an EP and forward the first TLP to a reliable TLP transmission RTT module for processing; the reliable TLP transmission module, configured to determine, according to the received first TLP, sending links connected to active and standby PCIE switching units, and send the first TLP to the active and standby PCIE switching units through the sending links at the same time, so that a destination PCIE interface controller of the first TLP selectively receives the first TLP forwarded by the active and standby PCIE switching units and sends the first TLP to a destination EP or a destination RC, thereby implementing reliable transmission of a TLP in a case of a PCIE switching dual-plane networking connection.

Abstract: In some implementations, a riser card can be configured to connect to multiple PCIe connectors on a motherboard of a computing device. The riser card can be configured to route signals from an accessory installed in the riser to the CPU of the computing device through multiple PCIe connectors. The riser card can be configured to connect to a PCIe connector on the motherboard using cabling.

Abstract: A system for parameterizing field devices of an automation or control system includes a higher-ranking unit, which is connected via a first communication link based on a first field bus protocol to a communication interface module. The module is connected via a second communication link based on a second field bus protocol to at least one field device. In the higher-ranking unit, sub-blocks are generated and stored from a data structure for configuring the field device that is stored in a device description file for the field device. A first network service transmits the parameters of the field device from the higher-ranking unit via the first communication link into a first functionality of the module that operates as a slave function. A further functionality integrated into the module evaluates parameters of the field device that are stored in sub-blocks and combines the parameters to form a single configuration block.

Abstract: A land-based or mobile phone and methods are provided for receiving inbound communications as either voice or text, and then based on the user's configuration settings, the inbound communication is provided to the user as it was received or is automatically converted into a format that is desired by the user. The phone also takes voice or text that is input by the user of the phone and converts the user's input to either voice or text based on the configuration settings stored in the user's contact list or otherwise. The outbound communication is configured according to how the intended recipient wants to receive a communication based on the configuration settings stored in the user's contact list or otherwise. The phone includes a controller that determines how the phone will handle and process inbound and outbound communications. The controller includes a speech recognition engine.

Abstract: A source-synchronous system is provided in which a non-uniform interface may exist in a data source endpoint as well as in a data sink endpoint.

Abstract: A method for handling an invalid packet for a blade server includes identifying whether a packet is valid, when the packet is identified as invalid, comparing the invalid packet with a plurality of packet data stored in a storage module, when the invalid packet is similar to a first packet datum among the plurality of packet data, executing a command indicated by the first packet datum, and ignoring the invalid packet when the invalid packet is not similar to any of the plurality of packet data.

Abstract: A method for managing the power consumption of an information handling system including a multi-lane serial link having a lane setting that identifies the number of active lanes in the multi-lane serial link. The method may include determining a number of lanes required for the multi-lane serial link based on one or more I/O devices connected to the information handling system, triggering a reduction of the lane setting of the multi-lane serial link if the lane setting of the multi-lane serial link is greater than the determined number of lanes required, and automatically reducing power to the multi-lane serial link in response to the reduction of the lane setting.

Abstract: A transceiver integrated circuit (IC) receives signals having a mix of idle characters and data via a multi-lane system-side signaling interface at a first signaling rate compliant with a standards-based signaling protocol. The transceiver IC outputs signals via a multi-lane line-side signaling interface at a second signaling rate that is lower than the first signaling rate and non-compliant with the standards-based signaling protocol and also outputs one or more requests to a remote IC source of the signals received via the system-side signaling interface to adjust a proportion of idle characters within the received signals as necessary to balance a data rate of the received signals with the second signaling rate without adjusting the first signaling rate.

Abstract: A memory device and method for content virtualization are disclosed. In one embodiment, a plurality of directories are created in the memory of the memory device, wherein each of the plurality of directories points to a same storage location of the digital content. In another embodiment, a first header for the digital content is stored in each of the different directories, wherein the first header comprises information about where to find the digital content in the memory. In yet another embodiment, the memory device comprises circuitry that receives an identification of a host device in communication with the memory device and reorganizes a directory structure of the memory in accordance with the identification of the host device, wherein the reorganization results in the digital content appearing to be located in a directory expected by the host device.

Abstract: A memory device and method for content virtualization are disclosed. In one embodiment, a plurality of directories are created in the memory of the memory device, wherein each of the plurality of directories points to a same storage location of the digital content. In another embodiment, a first header for the digital content is stored in each of the different directories, wherein the first header comprises information about where to find the digital content in the memory. In yet another embodiment, the memory device comprises circuitry that receives an identification of a host device in communication with the memory device and reorganizes a directory structure of the memory in accordance with the identification of the host device, wherein the reorganization results in the digital content appearing to be located in a directory expected by the host device.

Abstract: A data storage device including a first nonvolatile memory device having a first state information transmission block, a second nonvolatile memory device having a second state information transmission block, which shares a state information line with the first state information transmission block, and a controller having a state information reception block which is suitable for transmitting a control signal for controlling the first state information transmission block and the second state information transmission block to transmit a state information frame, and sequentially receiving a first state information frame transmitted from the first state information transmission block and a second state information frame transmitted from the second state information transmission block, through the state information line.

Abstract: An electronic assembly including a first connector having a first set of terminals physically and operationally compliant with a data transmission connector standard, such as USB 2.0, and a second set of terminals distinct from the first set of terminals physically compliant and operationally non-compliant with this data transmission connector standard. An electronic controller is connected to the first connector. The controller includes a memory device to store configuration data, such as a battery charging profile, used by the controller to control a first electronic device, such as a battery charging device. The second set of terminals receive new configuration data to update the configuration data stored in the memory device. The assembly may include a specially configured data cable to interconnect the assembly to a separate electronic device to transmit the updated configuration data. The assembly may reduce the current supplied for battery charging by monitoring a battery voltage.

Abstract: An intelligent optical transceiver able to revise a micro program by the host system is disclosed. The optical transceiver includes a MDIO interface, a CPU, and a non-volatile memory. The host system may communicate with the CPU through an external MDIO bus, the MDIO interface, and an internal bus; while the CPU communicated with the non-volatile memory through another bus. The new micro program sent from the host system is temporarily stored in the non-volatile memory through the MDIO interface and the CPU, and finally set in the flash ROM in the CPU.

Abstract: This document describes a method for synchronizing files on an expandable memory card coupled to a first computing device with an application running on a second computing device, where downloading of files is performed wirelessly without user involvement.

Abstract: Embodiments of the present invention provide a method, system and computer program product for agnostic processing of message queues and sequential files. In an embodiment of the invention, a method for agnostic processing of message queues and sequential files can be provided. The method can include receiving an access request for a resource that is uniform for both a message queue and a sequential file and identifying a resource type of the resource. In response to identifying the resource type as a message queue, a corresponding access request specific to a message queue can be invoked in the message queue. Otherwise a corresponding access request specific to a sequential file can be invoked responsive to identifying the resource type as a sequential file.

Abstract: On the basis of single-ended signals based on logic levels, and of differential, in particular common-mode-based, signals, a circuit arrangement and a corresponding method are proposed, in which a serialized signal transmission is always performed in an error-free and stable manner.

Abstract: A microprocessor includes a first hardware data prefetcher that prefetches data into the microprocessor according to a first algorithm. The microprocessor also includes a second hardware data prefetcher that prefetches data into the microprocessor according to a second algorithm, wherein the first and second algorithms are different. The second prefetcher detects that it is prefetching data into the microprocessor according to the second algorithm in excess of a first predetermined rate and, in response, sends a throttle indication to the first prefetcher. The first prefetcher prefetches data into the microprocessor according to the first algorithm at below a second predetermined rate in response to receiving the throttle indication from the second prefetcher.

Abstract: A data stream is stored in a database. An event pipe stores a sliding window of events from the data stream. A query is responded to by utilizing the sliding window of events stored in the event pipe.

Abstract: Embodiments may include a method, system and apparatus for providing for encoded dual-rail signal communications in asynchronous circuitry. A dual rail signal pair is received. The dual rail signal pair comprises a first value indicative of a first wait state, a second value indicative of a logic value of a first bit, a third value indicative of a second wait state and a first logic value of a second bit, and/or a fourth value indicative of second wait state and a second logic value of said second bit.

Abstract: An expansion unit includes a connector to which a remote unit is connected, an embedded memory that records therein information in a nonvolatile manner, an external memory I/F into which a memory card is inserted, a CPU that performs reading of the operation information set in the remote unit connected via the connector and performs writing of the operation information into the remote unit connected via the connector, and a memory switching switch that sets a writing destination of the operation information read from the remote unit connected to the connector and a reading source of the operation information to be written into the remote unit connected to the connector to any one of the memory card inserted into the external memory I/F and the embedded memory.

Abstract: Data access methods and storage subsystems thereof for reading data from storage devices in a redundant array of independent disks (RAID) system are provided. After a controller receives a read request, the target data that the controller is about to read and the sub-stripe(s) where the target data is located are determined according to the logical address block information in the read request. The controller simultaneously issues a plurality of I/O requests to all storage devices in order to read the target data and the related data distributed on the same sub-stripe(s) at the same time. If there is any target data without responses for a certain time, it is able to use the related data, which is already responded to the controller, to generate the redundant data identical to the target data for responding the read request as soon as possible so as to reduce unnecessary waiting time.

Abstract: Memory access alignment in a double data rate (‘DDR’) system, including: executing, by a memory controller, one or more write operations to a predetermined address of a DDR memory module, including sending to the DDR memory module a predetermined amount of data of a predetermined pattern along with a data strobe signal; executing, by the memory controller, a plurality of read operations from the predetermined address of the DDR memory module, including capturing data transmitted from the DDR memory module; and determining, by the memory controller, a read adjust value and a write adjust value in dependence upon the data captured in response to the read operations.

Abstract: Systems and methods are provided for allowing a multi-channel concurrent device to communicate timing information to a direct link peer, so that subsequent delivery of buffered traffic by the peer may be coordinated to minimize interference with operation of the device in another network context.

Abstract: High performance computing (HPC) and grid computing processing for seismic and reservoir simulation are performed without impacting or losing processing time in case of failures. A Data Distribution Service (DDS) standard is implemented in High Performance Computing (HPC) and grid computing platforms, to avoid the shortcomings of current Message Passing Interface (MPI) communication between computing modules, and provide quality of service (QoS) for such applications. QoS properties of the processing can be controlled. Multiple data publishers or master nodes of a cluster have access to the same data source. Each of these publishers has an ownership strength quality of service, and the publisher with the highest ownership strength number is the designated publisher of the data to subscriber processor nodes of the cluster.

Abstract: A method for managing concurrent system dumps of address spaces of memory of a computing system. The method comprises analyzing address space of memory to determine high priority areas and low priority areas of the address space. The method further comprises stopping all application threads of memory. In addition, the method further comprises performing a system dump of all the high priority areas of the address space. Moreover, the method further comprises initiating a background thread that performs a system dump of the low priority areas in background of the address space, and allowing, by the one or more computer processors, all of the application threads of memory to restart.

Abstract: A circuit for software tracing in a system on chip is described as including a plurality of components, each component having at least one local processor connected to a first communication bus; and each component being connected to a second communication bus. The circuit may further include a separate trace data bus being configured to transmit trace data generated by code running on the components. A method associated with software tracing on such a circuit is also disclosed.

Abstract: An interface apparatus is provided for exchange of different time-critical user data between a host device and a divided medium, by way of a first interface and by way of a second interface, having a resource management device and a temporary memory device. The first interface works with a first clock pulse and the second interface works with a second clock pulse. The first interface and the second interface are connected with the temporary memory device. The resource management device is set up for controlling the exchange of the different time-critical user data between the first interface and the second interface, in such a manner that collisions of the different time-critical user data within the interface apparatus and/or on the divided medium are avoided, in order to allow deterministic behavior during exchange of the different time-critical user data.

Abstract: A radio communication device enabling a serial interface to restart transmission in a short time when interface setting is changed, as well as a method for controlling RF-BB state in the device, are provided. According to the radio communication device in which a radio frequency section (20) and a baseband section (10) are connected through a serial interface, exclusive signals (Act, Act_Ack) for triggering an interface state change and for acknowledging it are provided between the radio frequency section and the baseband section, respectively. Interface state change control is performed by transmitting and receiving the interface state change trigger exclusive signal and its acknowledgement exclusive signal between the radio frequency section and the baseband section.

Abstract: A system and method are disclosed for an electronic integrated circuit to communicate with different hosts via different interfaces using the same host protocol. The system may use a host interface circuit to select a first set of electrical contacts or a second set of electrical contacts in order for a first host or a second host, respectively, to communicate with the electronic integrated circuit using a host protocol. The method may include switching from communicating with the first host using the first set of electrical contacts to communicating with the second host using the second set of electrical contacts in order for the second host to test the electronic integrated circuit.

Abstract: A memory device includes a memory bank including a plurality of word lines, and a word line controller capable of activating a first word line, which is accessed during a previous write operation, among the plurality of word lines, while activating a second word line corresponding to an input address among the plurality of word lines, during an active operation.

Abstract: An envelope detection device for detecting a transmission signal of a high speed serial communication includes: an operation circuit, for receiving the transmission signal and generating a set of operated outputs according to the transmission signal and at least one reference signal; a reference signal generating circuit coupled to the operation circuit, for providing the reference signal to the operation circuit, wherein the reference signal generating circuit is operable to provide the reference signal with different voltage levels; and a comparing circuit coupled to the operation circuit, for comparing the set of calculated outputs to generate a comparison result. The envelope detection device detects a transmission state and a disconnect state of the high speed serial communication according to the comparison result generated based on the reference signals at different voltage levels.

Abstract: A communication system (1) comprising: determining means operable to determine an attribute of a communication device; identifying means operable to identify an avatar by using the attribute, wherein the avatar is such that it conveys to a viewer thereof information about a person; and communicating means operable to communicate the avatar to the communication device.

Abstract: A method and a device for accelerating running of software are provided. The method includes: determining whether the software enters a specific scene of the software; and in the case where the software enters the specific scene, sending an incorporated I/O request corresponding to the specific scene to a file system; where the incorporated I/O request incorporates at least two first (e.g., original) I/O requests corresponding to the specific scene of the software. With the above technical solution, the number of I/O requests can be reduced, and the frequency of I/O track seeks can be reduced. The running of software can be accelerated due to reducing of the time spent on the I/O track seek.

Abstract: Methods, systems and non-transitory computer readable media are described. A system includes a shader pipe array, a redundant shader pipe array, a sequencer and a redundant shader switch. The shader pipe array includes multiple shader pipes, each of which perform rendering calculations on data provided thereto. The redundant shader pipe array also performs rendering calculations on data provided thereto. The sequencer identifies at least one defective shader pipe in the shader pipe array, and, in response, generates a signal. The redundant shader switch receives the generated signal, and, in response, transfers the data destined for each shader pipe identified as being defective independently to the redundant shader pipe array.

Abstract: A circuit arrangement for a data processing system is configured to process data in multiple modules. The circuit arrangement is configured to provide a clock as well as a time base and/or a base of at least one further physical quantity for each of the multiple modules. The circuit arrangement also comprises a central routing unit, which is connected to several of the multiple modules. Via the central routing unit, the modules can periodically exchange data based on the time base and/or on the base of the at least one further physical quantity. The several modules are configured to process data independently of and in parallel to other modules of the several modules.

Abstract: A SAS expander includes a switch core, a number of SAS expander phys coupled to the switch core, an SMP originator coupled to the switch core and an SMP receptor coupled to the switch core. In an embodiment, the SMP originator is configured to only send connection requests and the SMP receptor is configured to only receive connection requests. Program instructions stored in non-transient digital storage media include code segments detecting a new connection request, code segments determining whether the new connection request is in conflict with an existing connection request and code segments determining if there is a free destination receptor phy. In an embodiment, the free destination receptor phy is never operationally used for an origination of a connection request.

Abstract: The present invention relates to devices for exchanging data between at least two data consuming and/or emitting applications A1, A2.

Abstract: The use of asset connectivity verification and switchable asset connectivity activation techniques may reduce or eliminate occurrences of human errors with respect to the improper connection and activation of infrastructure components in a data center. Assert connectivity verification involves the acquisition of identifiers corresponding to infrastructure component interfaces that are coupled to each other, and comparing the identifiers to pairing specifications to verify that the coupling of the infrastructure components comply with pairing specifications. Asset connectivity activation involves determining whether the coupling of a switchable coupler to one or more component interfaces complies with pairing specifications based on the corresponding identifiers of each component, and activating the switchable coupler to enable the flow of data signals and/or power when the coupling of the components meets the pairing specifications.

Abstract: A computer system and a method of operating a service-processor-centric computer system. In one embodiment, the computer system includes: (1) a CPU configured to issue control signals and (2) a service processor configured for intercepting and handling the control signals, the handling including delaying, modifying or ignoring the control signals, the service processor further configuring for issuing highest-priority control signals.

Abstract: A computer system that recognizes multi-function devices and associates functions with multi-function devices. Each multi-function device may be represented by a multi-function object, allowing tools, applications or other components within the computer to take actions relating to the entire device or relating to a function based on the association of that function with other functions in the same device. These actions include displaying information about devices, instead of or in addition to information about functions. Actions also include selecting functions based on proximity within a device. Functions may be associated with a multi-function device using a unique device identifier provided by the device or generated for the function based on a connection hierarchy between functions and the computer. Devices may be configured to provide the same identifier regardless of the transport over which the device is accessed.

Abstract: A method for multiple protocol wireless communications begins by determining protocols of wireless communication devices within a proximal region. The method then continues by determining whether the protocols of the wireless communication devices within the proximal region are of a like protocol. The method continues by, when the protocols of the wireless communication devices within the proximal region are not of a like protocol, selecting a protocol of the protocols of the wireless communication devices within the proximal region based on a protocol ordering to produce a selected protocol. The method continues by utilizing the selected protocol by the wireless communication devices within the proximal region to set up a wireless communication within the proximal region.