Input/output Access Regulation Patents (Class 710/36)
  • Patent number: 8166209
    Abstract: A hypervisor acquires an I/O command that has been issued from a virtual computer. The hypervisor judges whether or not a target of an I/O that complies with the I/O command is an unassigned port associated device that is a device associated with an I/O port that is coupled to an I/O controller that is not assigned to a virtual computer that is an issuing source of the I/O command. In the case in which the result of the judgment is positive, the hypervisor does no execute an I/O to the unassigned port associated device, and returns a virtual execution result to the virtual computer that is an issuing source of the I/O command.
    Type: Grant
    Filed: November 8, 2011
    Date of Patent: April 24, 2012
    Assignee: Hitachi, Ltd.
    Inventor: Ryota Noguchi
  • Patent number: 8166211
    Abstract: Described herein are systems and methods for preventing a user mode USB driver from performing IOCTL operations other than read-safe IOCTLs on a USB device that has been claimed by a kernel mode driver or is in use by another user mode USB driver. In one method, it is determined whether a kernel mode USB driver will claim a device or whether the device will be available to be claimed by user mode USB drivers. In the event the device is claimed by a kernel mode USB driver, user mode USB drivers will be prevented from claiming the device. In the event the device is available for use by user mode USB drivers, but has been opened for write by one user mode USB driver, all other user mode USB drivers will be prevented from claiming the device. All IOCTL operations other than read-safe IOCTLs will be prevented from being performed by a user mode USB driver unless that USB driver has claimed the device.
    Type: Grant
    Filed: June 7, 2010
    Date of Patent: April 24, 2012
    Assignee: VMware, Inc.
    Inventors: Erik Cota-Robles, Igor Korsunsky
  • Patent number: 8161201
    Abstract: A method for configuring a peripheral device in communication with an information handling system (IHS) is disclosed, wherein the method includes receiving visual data associated with the peripheral device and mapping configuration data to the peripheral device based on the visual data. The method further includes utilizing the configuration data to configure the peripheral device in communication with the IHS. An information handling system (IHS) in communication with an image capturing device is further disclosed including a storage device operable to store a database, the database configured to store a standard image of a peripheral device, wherein the standard image is associated with configuration data for the peripheral device. The system further includes a memory coupled to the storage device and a processor to receive visual data associated with the peripheral device from the image capturing device.
    Type: Grant
    Filed: June 2, 2009
    Date of Patent: April 17, 2012
    Assignee: Dell Products L.P.
    Inventors: Douglas M. Anson, Yuan-Chang Lo, William Dale Todd Nix, Clint H. O'Connor
  • Patent number: 8161208
    Abstract: A processing apparatus which is capable of preventing an priority reservation for a particular period from being set for all of a plurality of apparatuses and improving convenience for a general user who does not use an priority reservation service, in a system for which the priority reservation is available. Reservation information about a reservation for priority use of peripherals (MFP-A, B, and C) is stored. The number of peripherals that are not reserved for priority use during a particular period in the peripherals with reference to the reservation information is detected. When the number of peripherals is one, an instruction not to accept a reservation for priority use during the particular period to the single peripheral that are not reserved for priority use during the particular period in the peripheral is issued.
    Type: Grant
    Filed: September 25, 2007
    Date of Patent: April 17, 2012
    Assignee: Canon Kabushiki Kaisha
    Inventor: Toshihisa Okutsu
  • Patent number: 8161161
    Abstract: A certain process included in a first execution space requests a local resource manager to allocate a resource. The local resource manager obtains the authentication ID of the process issuing the request and determines whether or not the resource can be allocated. If the resource can be allocated and the resource previously secured in the execution space can suffice the request, the local resource manager allocates the resource to the process. If the resource is insufficient, the local resource manager requests a global resource manager to allocate the resource. The global resource manager obtains the authentication ID of the first execution space issuing the request and determines whether or not the resource can be allocated. If it is determined that the resource can be allocated, the resource is allocated to the first execution space.
    Type: Grant
    Filed: October 6, 2006
    Date of Patent: April 17, 2012
    Assignee: Sony Computer Entertainment, Inc.
    Inventors: Yoichiro Iino, Atsushi Hamano, Jun Saito
  • Patent number: 8161204
    Abstract: Systems and methods for synchronizing a source and sink device are disclosed. A sink device can efficiently determine the source data rate even in cases where the sink device is not directly coupled to the source device. A method for transmitting a source data stream from a source device to a sink device includes, forming a logical channel from a source device to a sink device, where the logical channel is configured to carry the source data stream, and one or more rate parameters. The rate parameters relate a data rate of the source data stream to a data rate of the logical channel.
    Type: Grant
    Filed: April 12, 2010
    Date of Patent: April 17, 2012
    Assignee: ATI Technologies ULC
    Inventors: Nicholas J. Chorney, Collis Quinn Carter
  • Patent number: 8161207
    Abstract: A method and apparatus for handshaking using a 2-wire protocol is described. An electronic component may be divided into blocks, with the blocks performing one or more functions. The blocks may be in series with one another to form a pipeline. The blocks may use interface circuitry to transfer information upstream from or downstream to another block. The interface circuitry uses the 2-wire handshaking for the transfer including a transmit readiness wire configured to carry a signal indicative of readiness of the upstream circuit to output data and a receive readiness wire configured to carry a signal indicative of readiness of the downstream circuit to receive the data.
    Type: Grant
    Filed: May 11, 2007
    Date of Patent: April 17, 2012
    Assignee: Marvell International Ltd.
    Inventors: John D. Marshall, Douglas G. Keithley, Gregory R. Smith, Roy G. Moss
  • Patent number: 8161212
    Abstract: An embodiment of a system for implementing parallel usage of a plurality of non-volatile input/output (I/O) devices can include an interface configured to receive, from a source, a source request and a first memory coupled to the interface. The first memory can be configured to store a data unit specified by the source request. The system can include an I/O device controller coupled to the interface. The I/O device controller can be configured to correlate the source request with a plurality of I/O device requests and initiate sending of the plurality of I/O device requests to the plurality of non-volatile I/O devices in parallel. The system also can include a decoder coupled to the first memory and the I/O device controller. The decoder can be configured to receive data from the plurality of non-volatile I/O devices in parallel.
    Type: Grant
    Filed: September 22, 2010
    Date of Patent: April 17, 2012
    Assignee: Xilinx, Inc.
    Inventors: Ting Lu, Kam-Wing Li, Bradley L. Taylor
  • Patent number: 8156274
    Abstract: A method and system for transferring data between two slave devices. A system includes a master device and first and second slave devices coupled to the master device by a peripheral bus. The master device is configured to configure the first slave device as a source for a read operation, configure the second slave device as a target for a write operation, provide a clock signal to both the first slave device and the second slave device, and initiate a read operation of the first slave device. Initiation of the read operation causes the first slave device to provide data onto the peripheral bus. Responsive to the master device initiating the read operation, the second slave device receives the data provided on the peripheral bus by the first slave device. The master device is configured to ignore the data provided on the peripheral bus by the first slave device.
    Type: Grant
    Filed: February 2, 2009
    Date of Patent: April 10, 2012
    Assignee: Standard Microsystems Corporation
    Inventor: Jordan S. Kapelner
  • Patent number: 8156252
    Abstract: In various embodiments, options for data striping to FLASH memory are provided. In one embodiment, an apparatus is provided. The apparatus includes an SATA to ATA bridge, an ATA to USB bridge coupled to the SATA to ATA bridge, and a USB interface coupled to the ATA to USB bridge. The apparatus also includes a first FLASH memory controller coupled to the USB interface. The apparatus further includes a first FLASH memory module coupled to the first FLASH memory controller. The apparatus also includes a second FLASH memory controller coupled to the USB interface and a second FLASH memory module coupled to the second FLASH memory controller. A method for block striping data to or from a plurality of read or write channels.
    Type: Grant
    Filed: February 9, 2010
    Date of Patent: April 10, 2012
    Assignee: SMART Modular Technologies, Inc.
    Inventor: Ryan McDaniel
  • Patent number: 8156263
    Abstract: An information processing apparatus includes: a processor configured to run an operating system; a plurality of storage devices connected to the processor; a detection module configured to detect a boot process for installing the operating system; a determination module configured to acquire device information from each of the storage devices and determine priority rank of the storage devices based on the device information when the detection module detects the boot process being originated from a device other than the storage devices; and a control module configured to install the operating system in a target storage device that is selected from among the storage devices, the target storage device having the highest priority rank determined by the determination module.
    Type: Grant
    Filed: January 7, 2010
    Date of Patent: April 10, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Keiichi Uehara
  • Patent number: 8151006
    Abstract: A method, storage medium, and system for a managed audio bell/intercom including a controller and audio devices connected by an industry standardized network, wherein the controller contains logic to distribute action via the network to the audio devices.
    Type: Grant
    Filed: December 22, 2007
    Date of Patent: April 3, 2012
    Inventor: Terry Daniel Weidig
  • Patent number: 8151017
    Abstract: A computer system for software development and debugging for an embedded system includes a Universal Serial Bus (USB), a host computer comprising a USB driver interfaced with the USB, wherein the USB driver can multiplex application data and debug data to and from the USB, and an embedded system comprising a USB module interfaced with the USB. The USB module can multiplex the application data and the debug data to and from the host computer via the USB.
    Type: Grant
    Filed: August 23, 2010
    Date of Patent: April 3, 2012
    Assignee: Smartech World Wide Limited
    Inventor: Chi Kwok Wong
  • Patent number: 8151013
    Abstract: A host I/F unit has a management table for managing an MPPK which is in-charge of the control of input/output processing for a storage area of an LDEV, and if a host computer transmits an input/output request for the LDEV, the host I/F unit transfers the input/output request to the MPPK which is in-charge of the input/output processing for the LDEV based on the management table, an MP of the MPPK performs the input/output processing based on the input/output request, and the MP of the MPPK also judges whether the MPPK that is in-charge of the input/output processing for the LDEV is to be changed, and sets the management table so that an MPPK which is different from the MPPK that is in-charge is to be in-charge of the input/output processing for the LDEV.
    Type: Grant
    Filed: February 15, 2011
    Date of Patent: April 3, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Kazuyoshi Serizawa, Yasutomo Yamamoto, Norio Shimozono, Akira Deguchi, Hisaharu Takeuchi, Takao Sato, Hisao Homma
  • Patent number: 8145806
    Abstract: Techniques are provided for managing, within a storage system, the sequence in which I/O requests are processed by the storage system based, at least in part, on a one or more logical characteristics of the I/O requests. The logical characteristics may include, for example, the identity of the user for whom the I/O request was submitted, the service that submitted the I/O request, the database targeted by the I/O request, an indication of a consumer group to which the I/O request maps, the reason why the I/O request was issued, a priority category of the I/O request, etc. Techniques are also provided for automatically establishing a scheduling policy within a storage system, and for dynamically changing the scheduling policy in response to changes in workload.
    Type: Grant
    Filed: September 18, 2009
    Date of Patent: March 27, 2012
    Assignee: Oracle International Corporation
    Inventors: Sue K. Lee, Vivekananda C. Kolla, Akshay D. Shah, Sumanta Chatterjee, Margaret Susairaj, Juan R. Loaiza, Alexander Tsukerman, Sridhar Subramaniam
  • Patent number: 8145809
    Abstract: An embodiment of the present invention is directed to a system for synchronizing independent time domain information. The synchronization of the device resource access information allows a memory access device to reliably access memory in a time domain independent of a device issuing requests. The system may synchronize device resource information for requests made by a processor to access (e.g., read/write) locations of a memory device. The present invention synchronizes the device access information without restricting pulse width of a read/write signal or requiring a high speed clock.
    Type: Grant
    Filed: March 7, 2008
    Date of Patent: March 27, 2012
    Assignee: Cypress Semiconductor Corporation
    Inventors: Syed Babar Raza, Pradeep Bajpai
  • Patent number: 8145807
    Abstract: A computer system for software development and debugging for an embedded system includes a Universal Serial Bus (USB), a host computer comprising a USB driver interfaced with the USB, wherein the USB driver can multiplex application data and debug data to and from the USB, and an embedded system comprising a USB module interfaced with the USB. The USB module can multiplex the application data and the debug data to and from the host computer via the USB.
    Type: Grant
    Filed: January 10, 2012
    Date of Patent: March 27, 2012
    Assignee: Smartech Worldwide Limited
    Inventor: Chi Kwok Wong
  • Publication number: 20120072622
    Abstract: In general, in one aspect, the invention relates to a method for binding input/output (I/O) objects to nodes. The method includes receiving a request to use an I/O device from a process, determining a resource to service the request, generating a first I/O object corresponding to the resource, wherein the first I/O object is unbound, and generating a proc object, wherein the proc object comprises a reference to the process requesting to use the I/O device. The method also includes sending the first I/O object and the proc object to a Non-Uniform Memory Access (NUMA) I/O Framework, determining that the process is executing on a first NUMA node, selecting the first NUMA, binding the first I/O object to the first NUMA node, and servicing the request by processing, on the first NUMA node, the resource corresponding to the first I/O object.
    Type: Application
    Filed: March 31, 2011
    Publication date: March 22, 2012
    Applicant: ORACLE INTERNATIONAL CORPORATION
    Inventors: Nicolas G. Droux, Rajagopal Kunhappan, Sherman Pun
  • Patent number: 8140720
    Abstract: In a storage system having a plurality of storage apparatuses, each of the storage apparatuses stores therein a coupling mode that is information indicative of whether or not to permit setting of a communication path between each of the storage apparatuses and a plurality of other storage apparatuses. A management apparatus is provided to be coupled for communication to each of the storage apparatuses. The management apparatus has a communication path setting part that provides a user interface for setting the communication path. The communication path setting part does not permit setting of the communication path, at the time of setting the communication path, when the coupling modes of both of the storage apparatuses between which the communication path is to be set are set permissible.
    Type: Grant
    Filed: February 9, 2009
    Date of Patent: March 20, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Yoshiyuki Noborikawa, Koji Nagata, Kosuke Sakai
  • Patent number: 8140714
    Abstract: A method and apparatus for intelligently routing and managing audio signals within an electronic device is disclosed. The routing is responsive to a set of logical and physical policies which are stored in data tables which can be updated as needed.
    Type: Grant
    Filed: December 28, 2010
    Date of Patent: March 20, 2012
    Assignee: Apple Inc.
    Inventors: James D. Batson, Meriko L. Borogove, Gregory R. Chapman, Patrick L. Coffman, Anthony J. Guetta, Aram Lindahl, Andrew Rostaing
  • Patent number: 8140719
    Abstract: A data center has several dis-aggregated data clusters that connect to the Internet through a firewall and load-balancer. Each dis-aggregated data cluster has several dis-aggregated compute/switch/disk chassis that are connected together by a mesh of Ethernet links. Each dis-aggregated compute/switch/disk chassis has many processing nodes, disk nodes, and I/O nodes on node cards that are inserted into the chassis. These node cards are connected together by a direct interconnect fabric. Using the direct interconnect fabric, remote I/O and disk nodes appear to the operating system to be located on the local processor's own peripheral bus. A virtual Ethernet controller and a virtual generic peripheral act as virtual endpoints for the local processor's peripheral bus. I/O and disk node peripherals are virtualized by hardware without software drivers. Rack and aggregation Ethernet switches are eliminated using the direct interconnect fabric, which provides a flatter, dis-aggregated hierarchy.
    Type: Grant
    Filed: May 5, 2009
    Date of Patent: March 20, 2012
    Assignee: Sea Micro, Inc.
    Inventors: Gary Lauterbach, Anil R. Rao
  • Patent number: 8141077
    Abstract: A system, method and medium for reducing the number of system calls from an application program to an operating system kernel. In an embodiment, a method includes the steps of creating a list of requests issued by an application program, associating an indicia with the list indicating whether the list contains a request, querying the indicia to determine if the list contains a request, and adding a new application program request to the list when the indicia indicates that the list includes a request.
    Type: Grant
    Filed: March 12, 2010
    Date of Patent: March 20, 2012
    Assignee: Red Hat, Inc.
    Inventor: Alan Cox
  • Patent number: 8135880
    Abstract: Disclosed is a mass-storage device, comprising a Universal Serial Bus (USB) interface, a locking function coupled to the USB interface wherein the locking function is accessible via a USB device class other than a mass-storage class, and a data mass-storage memory coupled to the locking circuit.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: March 13, 2012
    Assignee: Cypress Semiconductor Corporation
    Inventors: Steven Kolokowsky, Brian Tuttle
  • Patent number: 8131892
    Abstract: A storage apparatus is provided that is capable of reducing data maintenance management costs with a performance that is both highly reliable and fast. The present invention is storage apparatus where an intermediary device is arranged between a controller and a plurality of disk devices of different performances arranged in a hierarchical manner. The controller unit carries out I/O accesses to and from the disk devices via the intermediary devices based on access requests sent from host apparatus. The intermediary device includes a power saving control function for the disk device and carries out operation control such as spin off and spin up of disk devices in accordance with conditions set in advance.
    Type: Grant
    Filed: May 7, 2010
    Date of Patent: March 6, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Hiroyuki Kumasawa, Takashi Chikusa, Satoru Yamaura
  • Patent number: 8131960
    Abstract: An automated backup and reversion system comprising at least two storage systems with one source storage system being physically connected to at least one host system during normal processing at any given time. During the backup process, involved storage devices are physically disconnected from the host system. The at least one destination storage system receiving the information backup may thereafter be connected to the host system to allow for subsequent host processing. The initial source storage system may then remain disconnected from the host system and assume the role of a destination storage system. Each storage system is located at the same logical location while being processed so that the host system is unaware that any storage system change has occurred. A plurality of storage systems may be configured with only one being processed at any given time, and the remainder may comprise successive backups after any negative event.
    Type: Grant
    Filed: May 21, 2008
    Date of Patent: March 6, 2012
    Inventor: Stephen W. Durfee
  • Patent number: 8131891
    Abstract: A hosting partition update mechanism allows updating I/O capability of a logically-partitioned computer system in a way that minimally affects the performance and availability of I/O in the computer system. When an update is needed, a new hosting partition is created with the desired update(s). I/O adapters in the current hosting partition are then migrated to the new hosting partition. The migration of an I/O adapter from the current hosting partition to the new hosting partition is relatively fast, thereby minimally impacting system performance and availability of I/O. Once all of the I/O adapters have been migrated to the new hosting partition, the current hosting partition may be kept as a backup, or may be eliminated. Providing a new or backup hosting partition allows updates to be performed in the new or backup hosting partition in a non-disruptive manner while the current hosting partition continues to service I/O requests.
    Type: Grant
    Filed: March 26, 2008
    Date of Patent: March 6, 2012
    Assignee: International Business Machines Corporation
    Inventors: David Charles Boutcher, Charles Scott Graham, Harvey Gene Kiel, Chetan Mehta, Jaya Srikrishnan
  • Patent number: 8131886
    Abstract: A disclosed image forming apparatus includes an image processing device including plural image processing units; a control device configured to control the plural image processing units; and a connection unit configured to connect the image processing device to the control device. Each of the plural image processing units is connected to the control device by one of plural channels; the image processing device is connected to the control device by a first bus including the channels; and the connection unit is provided on the first bus so that the image processing device is connected to the control device by a single connection unit.
    Type: Grant
    Filed: October 22, 2010
    Date of Patent: March 6, 2012
    Assignee: Ricoh Company, Ltd.
    Inventors: Takashi Aihara, Hidemasa Morimoto
  • Patent number: 8127054
    Abstract: A programmatic time-gap defect correction apparatus and method corrects errors which may go undetected by a computer system. Buffer underruns or overruns, which may incur errors in data transfers, yet remain undetected and uncorrected in a computer system, are corrected by an error avoidance module in accordance with the invention. Bytes transferred to and from buffers, used by an I/O controllers to temporarily store data while being transferred between synchronous and asynchronous devices, are counted and an error condition is forced based on the count. If the count exceeds the capacity of the buffer, an error condition is forced, thereby reducing chances that errors are incurred into the data transfer.
    Type: Grant
    Filed: April 6, 2011
    Date of Patent: February 28, 2012
    Inventor: Phillip M. Adams
  • Patent number: 8127048
    Abstract: A storage subsystem comprises a set of zone definitions that uses physical block addresses to divide a memory array in the storage subsystem into zones or segments. A set of zone parameters defines user access modes and security levels for each of the segments. Defining zones for the memory array provide flexibility and increased protection for data stored in the memory array. For example, data of one zone can be quickly erased without affecting data stored in other zones and critical data can be stored in read-only zones to prevent inadvertent overwrite.
    Type: Grant
    Filed: March 18, 2011
    Date of Patent: February 28, 2012
    Assignee: SiliconSystems, Inc.
    Inventors: David E. Merry, Mark S. Diggs, Gary A. Drossel, Michael J. Hajeck
  • Patent number: 8127306
    Abstract: Techniques are provided for efficiently processing SOAP requests at a Web service application (WSA) of a multi-functional device (MFP). In one technique, a WSA includes at least three threads. An external request processing thread processes SOAP requests from different client applications. A request processing thread processes a SOAP request according to the business logic of the WSA. A internal communications thread communicates with other components of the MFP that are distinct from the WSA. In another technique, a WSA processes different SOAP request differently, depending on the size of the SOAP and the resources required to process the SOAP request so that fast requests may be processed immediately while slow requests are pending. In another technique, a WS-Eventing specification is implemented within a WSA to simplify the event subscription and notification process.
    Type: Grant
    Filed: December 18, 2006
    Date of Patent: February 28, 2012
    Assignee: Ricoh Company, Ltd.
    Inventors: Alain Regnier, Lifen Tian, Yao-Tian Wang
  • Patent number: 8127047
    Abstract: Proposed is technology for shortening the time required for analyzing and processing commands issued from multiple hosts and speeding up the processing. When a controller receives a command including random IO processing and the reception of commands is complete, it determines whether the valid extents prescribed in seek parameters attached to an LOC command overlap, and executes extent exclusive wait processing which causes access to the logical volume to enter a wait state or access processing to the logical volume based on the determination result. If the reception of commands is incomplete, the controller determines whether the access ranges (extents) designated in a DX command overlap, and executes extent exclusive wait processing or access processing to the logical volume based on the determination result.
    Type: Grant
    Filed: March 6, 2009
    Date of Patent: February 28, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Ran Ogata, Akihiro Mori, Junichi Muto, Kazue Jindo
  • Patent number: 8122163
    Abstract: This invention relates to a communication system including a first apparatus having a first storage medium, and a second apparatus for transmitting data to the first apparatus, the second apparatus comprising: a second storage medium for storing management information of data to be transferred to the first storage medium; communication means for communicating data with the first apparatus; edit means capable of editing the management information; and control means for making a control to transfer data stored in the second storage medium to the first storage medium by way of the communication means on the basis of the management information edited by the edit means.
    Type: Grant
    Filed: February 20, 2008
    Date of Patent: February 21, 2012
    Assignee: Sony Corporation
    Inventor: Akihiro Morohashi
  • Patent number: 8122156
    Abstract: A method is provided for processing operation command in a computer that has a display and a host which includes a first display processing unit for local displaying and a second display processing unit for remote displaying. The operation command is from a remote data processing terminal. The method includes: receiving a first operation command from the data processing terminal, the first operation command being a power-on command; performing power-on of the computer, shielding the first display processing unit and loading only a driver of the second display processing unit according to first operation command; receiving a second operation command from the data processing terminal, the second operation command being not a power-on command; executing the second operation command to obtain operation results, the operation results being image data processed by the second display processing unit, and sending the operation results to the remote data processing terminal, for remote displaying.
    Type: Grant
    Filed: January 13, 2009
    Date of Patent: February 21, 2012
    Assignee: Lenovo (Beijing) Limited
    Inventors: Yiqiang Yan, Shaoping Peng, Bo Liu, Xiaohua Jiang, Chengkun Sun
  • Patent number: 8116226
    Abstract: Broadcast primitive filtering in a SAS expander using virtual domains. The virtual domains can be non-overlapping or overlapping logical subsets of the physical topology, or a logical construct based on the membership of a device within a group. Broadcast event propagation is handled in accordance with predetermined policies associated with the virtual domains. These policies can, for example, include limiting the broadcast traffic within the boundaries of the logical zones defined by the subsets, or routing the broadcast events in accordance with access policies, or privileges, associated with the group.
    Type: Grant
    Filed: January 30, 2006
    Date of Patent: February 14, 2012
    Assignee: PMC-Sierra, USA Inc.
    Inventors: Heng Liao, Larrie Simon Carr
  • Patent number: 8117358
    Abstract: A real-time customer relation management system is disclosed. The system can provide increased availability, reduced internal latencies, and reduced data processing and transfer. The system can provide real time processing and batch processing. The system architecture can have an in-memory write-through cache. The cache can store data that would have otherwise been sent to a database. The system can have a backup in-memory write-through cache. The system can use a warm standby, for example, to enhance data backup efficiency.
    Type: Grant
    Filed: July 28, 2006
    Date of Patent: February 14, 2012
    Assignee: Oracle International Corporation
    Inventors: David S. Labuda, Jayaprakash Krishnamoorthy, James R. Haddock, Alexander S. Rockel, Keith M. Brefczynski, Giles Douglas
  • Patent number: 8117351
    Abstract: Subject matter disclosed herein relates to techniques involving transitioning serial data into a serial parallel interface.
    Type: Grant
    Filed: December 28, 2009
    Date of Patent: February 14, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Paolo Mangalindan
  • Patent number: 8112561
    Abstract: A hosting partition update mechanism allows updating I/O capability of a logically-partitioned computer system in a way that minimally affects the performance and availability of I/O in the computer system. When an update is needed, a new hosting partition is created with the desired update(s). I/O adapters in the current hosting partition are then migrated to the new hosting partition. The migration of an I/O adapter from the current hosting partition to the new hosting partition is relatively fast, thereby minimally impacting system performance and availability of I/O. Once all of the I/O adapters have been migrated to the new hosting partition, the current hosting partition may be kept as a backup, or may be eliminated. Providing a new or backup hosting partition allows updates to be performed in the new or backup hosting partition in a non-disruptive manner while the current hosting partition continues to service I/O requests.
    Type: Grant
    Filed: December 29, 2007
    Date of Patent: February 7, 2012
    Assignee: International Business Machines Corporation
    Inventors: David Charles Boutcher, Charles Scott Graham, Harvey Gene Kiel, Chetan Mehta, Jaya Srikrishnan
  • Patent number: 8108571
    Abstract: A channel-less system and method are provided for multithreaded communications with a direct memory access (DMA) controller. The method accepts a plurality of DMA command messages directed to a fixed port address. The DMA command messages are arranged in a first-in first-out (FIFO) queue, in the order in which they are received. The DMA command messages are supplied to a DMA controller from the FIFO queue, and in response to the DMA command message, data transfer operation are managed by the DMA controller. Following the completion of each data transfer operation, a transfer complete message indicating completion is sent. In one aspect, DMA command messages are arranged in a plurality of parallel FIFO queues, and CD sets are stored in a plurality of context memories, where each context memory is associated with a corresponding FIFO queue.
    Type: Grant
    Filed: September 17, 2010
    Date of Patent: January 31, 2012
    Assignee: Applied Micro Circuits Corporation
    Inventor: Daniel L. Bouvier
  • Patent number: 8107492
    Abstract: A processing system and method for communicating in a processing system over a bus is disclosed. The processing system includes a receiving device, a bus having first, second and third channels, and a sending device configured to address the receiving device on the first channel, and read a payload from the receiving device on the second channel, the sending device being further configured to write a first portion of a payload to the receiving device on the first channel and a second portion of the payload to the receiving device on the third channel.
    Type: Grant
    Filed: August 31, 2006
    Date of Patent: January 31, 2012
    Assignee: QUALCOMM Incorporated
    Inventors: Richard Gerard Hofmann, Terence J. Lohman
  • Patent number: 8099531
    Abstract: An information processing apparatus includes a device that performs data processing; and processors, each processor including a device driver corresponding to the device. A device driver set in correspondence with at least one processor has a resource-state holding unit that manages a resource flag indicating which processor is using or is scheduled to use resources used at the time of data processing using the device. At least one processor sets the resource flag to a flag value indicating that at least one processor is scheduled to use the resources in accordance with a schedule of at least one processor to use the device. At least one processor terminates or interrupts use of the device when at least one processor refers to the resource flag and recognizes that another processor is scheduled to use the resources during a period in which at least one processor is using the device.
    Type: Grant
    Filed: April 14, 2009
    Date of Patent: January 17, 2012
    Assignee: Sony Corporation
    Inventor: Hiroshi Kyusojin
  • Patent number: 8099529
    Abstract: Systems and methods for performing native command queuing according to the protocol specified by Serial ATA II for transferring data between a disk and system memory are described. Native command queuing context for queued commands is maintained by a host controller device driver and is provided to the host controller as needed to process the queued commands. The host controller is simplified since it only stores the context of the one command being processed. The host controller generates a backoff interrupt when a command cannot be queued. The host controller generates a DMA transfer context request interrupt to request programming of the registers that store the context for the one command being processed.
    Type: Grant
    Filed: October 29, 2009
    Date of Patent: January 17, 2012
    Assignee: NVIDIA Corporation
    Inventors: Mark A. Overby, Xing Cindy Chen
  • Publication number: 20120011288
    Abstract: A specific identification information management device coupled to a feature expansion device includes: a storage unit configured to store the specific identification information of the feature expansion device; a detection unit configured to detect access to the feature expansion device; and a control unit configured to transmit the specific identification information stored in the storage unit to the source of access to the feature expansion device when the access is detected by the detection unit.
    Type: Application
    Filed: September 19, 2011
    Publication date: January 12, 2012
    Applicant: FUJITSU LIMITED
    Inventors: Manabu KANAYA, Yukio OGUMA
  • Patent number: 8095694
    Abstract: A centralized resource manager manages the routing of audio or visual information within a device, including a handheld device such as a smartphone. The resource manager evaluates data-driven policies to determine how to route audio or visual information to or from various input or output components connected to the device, including headphones, built-in speakers, microphones, bluetooth headsets, cameras, and so on. Among the data considered in the policies are connection status data, indicating if a device is connected, routing status data, indicating if a device is permitted to route information to or from a component, and grouping data, indicating logical relationships between various components. Components may be considered inherently routable, automatically routable, or optionally routable. Numerous other uses exist for such data, including providing simpler and more logical management interfaces.
    Type: Grant
    Filed: April 20, 2011
    Date of Patent: January 10, 2012
    Assignee: Apple Inc.
    Inventors: Andrew Rostaing, Anthony J. Guetta, Greg Chapman
  • Patent number: 8094330
    Abstract: An image forming apparatus is provided, in which the image forming apparatus includes service modules for performing system side processes on image formation, wherein applications can be added to the image forming apparatus separately from the service modules, and the image forming apparatus includes an application launch part for referring to launch selection information indicating at least a location that stores one or more applications, and launching the one or more applications from the at least a location according to the launch selection information.
    Type: Grant
    Filed: July 18, 2003
    Date of Patent: January 10, 2012
    Assignee: Ricoh Company, Ltd.
    Inventors: Tsutomu Ohishi, Kohji Shimizu
  • Patent number: 8090887
    Abstract: A processor determines whether a prescribed period of time has elapsed or not. When the processor has determined that the prescribed period of time has elapsed, the processor determines whether a mode 0 is set or not. When it is determined that the mode 0 is set, a wireless packet including remote controller button data, remote controller acceleration data and remote controller DPD data is generated. Then, the generated wireless packet is transmitted to a game device. When the processor has determined that a mode 1 is set, a wireless packet including remote controller information including the remote controller button data and the remote controller acceleration data and biological information including previous pulse wave data, present pulse wave data and light reception level data, instead of the remote controller DPD data, is generated.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: January 3, 2012
    Assignee: Nintendo Co., Ltd.
    Inventors: Koji Ikeno, Hitoshi Yamazaki
  • Patent number: 8086769
    Abstract: A computer implemented method, data processing system, and computer program product for detecting circular buffer overflow. When an entry in the circular buffer is read, a valid mark bit in the entry is set to an inactive state and the location of the entry is stored as an entry previously processed. A valid mark bit of a next entry and the valid mark bit in the entry previously processed are read. Responsive to determining that the valid mark bit in the entry previously processed is in the inactive state and the valid mark bit in the next entry is in an active state, the next entry is read, the valid mark bit in the next entry is set to an incactive state, and the location of the next entry is stored as the entry previously processed. Responsive to determining that the valid mark bit in the entry previously processed is in the active state, a determination is made that a circular buffer overflow has occurred.
    Type: Grant
    Filed: January 17, 2008
    Date of Patent: December 27, 2011
    Assignee: International Business Machines Corporation
    Inventor: Richard L. Arndt
  • Patent number: 8085658
    Abstract: A system and method of controlling data flow may take into account an egress port flow control configuration as well as an original ingress port flow control configuration. A queue controller may execute a flow control algorithm or a quality of service algorithm responsive to the flow control modes at either or both of the original ingress port and the egress port.
    Type: Grant
    Filed: August 20, 2010
    Date of Patent: December 27, 2011
    Assignee: Marvell International Ltd.
    Inventor: Donald Pannell
  • Patent number: 8086765
    Abstract: Illustrated is a system and method for identifying a memory page that is accessible via a common physical address, the common physical address simultaneously accessed by a hypervisor remapping the physical address to a machine address, and the physical address used as part of a DMA operation generated by an I/O device that is programmed by a VM. It also includes transmitting data associated with the memory page as part of a memory disaggregation regime, the memory disaggregation regime to include an allocation of an additional memory page, on a remote memory device, to which the data will be written. It further includes updating a P2M translation table associated with the hypervisor, and an IOMMU translation table associated with the I/O device, to reflect a mapping from the physical address to a machine address associated with the remote memory device and used to identify the additional memory page.
    Type: Grant
    Filed: April 29, 2010
    Date of Patent: December 27, 2011
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Yoshio Turner, Jose Renato Santos, Jichuan Chang
  • Patent number: 8086768
    Abstract: The storage system includes a first storage subsystem having a first logical volume to be accessed by a host computer, and a second storage subsystem connected to the first storage subsystem and having a second logical volume to be mapped to the first logical volume. The first storage subsystem includes a memory having definition information for defining a plurality of logical paths that transfer, to the second logical volume, I/O from the host computer to the first logical volume, and a transfer mode of the I/O to the plurality of logical paths. At least two or more logical paths among the plurality of logical paths are defined as active, and the controller transfers the I/O to the at least two or more logical paths set as active.
    Type: Grant
    Filed: June 9, 2008
    Date of Patent: December 27, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Yutaka Watanabe, Keishi Tamura
  • Patent number: 8078765
    Abstract: A hypervisor acquires an I/O command that has been issued from a virtual computer. The hypervisor judges whether or not a target of an I/O that complies with the I/O command is an unassigned port associated device that is a device associated with an I/O port that is coupled to an I/O controller that is not assigned to a virtual computer that is an issuing source of the I/O command. In the case in which the result of the judgment is positive, the hypervisor does no execute an I/O to the unassigned port associated device, and returns a virtual execution result to the virtual computer that is an issuing source of the I/O command.
    Type: Grant
    Filed: December 2, 2009
    Date of Patent: December 13, 2011
    Assignee: Hitachi, Ltd.
    Inventor: Ryota Noguchi