Abstract: In one aspect of the present description, a connection between a predetermined input port and a predetermined output port is created in a partition of a VSAN switch, in which the connection is a destination address independent physical layer connection conforming to the physical layer of a communication protocol. Another connection between a plurality of input ports and a plurality of output ports may be created in another partition of the VSAN switch, in which the connection is a multi-layer connection which includes a network layer connection conforming to the network layer of the communication protocol. Other features and aspects may be realized, depending upon the particular application.

Abstract: Computer security is enhanced by creating an environment in which changing the state of a general-purpose input/output (GPIO) output or changing the configuration of a GPIO is allowed only when authorized programs are executing. A storage device stores, responsive to a write signal, a state of a data signal. The GPIO is operable to respond to the state stored in the storage device. Control logic is operable to enable the write signal when a microprocessor in the computer is in a system management mode or a lock signal is not asserted, and to disable the write signal when the lock signal is asserted and the microprocessor is not in the system management mode.

Abstract: A method, system, apparatus, and computer program product are provided for providing peripheral device management. For example, a method is provided that includes receiving, from a user device, a request to access at least one peripheral device, the request comprising information regarding the user device. The method may further include determining, based at least in part on at least one compliance rule and the information regarding the user device, whether to grant the request, and, in an instance in which it is determined to grant the request, causing access to the at least one peripheral device by the user device to be facilitated.

Abstract: A system is described in which a plurality of host computers are coupled to a storage system for storing and retrieving data in the storage system. The storage system includes individually addressable units of storage such as volumes or logical unit numbers. A security management system controls access to each of the individually addressable units of storage based upon the identification of the host permitted to access that unit of storage.

Abstract: The present disclosure provides an improved point-to-point serial peripheral interface, a system comprising an improved point-to-point serial peripheral interface, and a method for use in a system comprising an improved point-to-point serial peripheral interface. A master comprises a SPI initiating port. Each slave comprises at least one SPI receiving port and at least one SPI forwarding port. The master provides a set of SPI signals to the SPI receiving port of the first slave in the chain, and the entire SPI signals are forwarded via the SPI forwarding port of each of the slaves until the SPI transaction reaches a target slave, which is identified by an in-band device addressing mechanism.

Abstract: The storage system includes a first storage subsystem having a first logical volume to be accessed by a host computer, and a second storage subsystem connected to the first storage subsystem and having a second logical volume to be mapped to the first logical volume. The first storage subsystem includes a memory having definition information for defining a plurality of logical paths that transfer, to the second logical volume, I/O from the host computer to the first logical volume, and a transfer mode of the I/O to the plurality of logical paths. At least two or more logical paths among the plurality of logical paths are defined as active, and the controller transfers the I/O to the at least two or more logical paths set as active.

Abstract: The present disclosure includes methods, devices, and systems for controlling a memory device. One method for controlling a memory device embodiment includes storing device class dependent information and a command in one or more of host system memory and host controller memory, setting a pointer to the command in a register in a host controller, directing access to the one or more of host system memory and host controller memory with the memory device via the host controller; and executing the command with the memory device.

Abstract: An integrated circuit comprises a predefined logic area including a microprocessor coupled to a plurality of peripheral devices including an external bus interface over a system bus. A customizable logic area is accessible by the microprocessor over the system bus. A first I/O bus sends data to an external device. A second I/O bus receives data from an external device. A first set of multiplexers in the predefined logic area have first inputs coupled to an output of the external bus interface, second inputs coupled to the customizable logic area, and an output coupled to a first I/O bus. A second set of multiplexers in the predefined logic area have first inputs coupled to the customizable logic area, second inputs coupled to the second I/O bus, and an output coupled to an input of the external bus interface.

Abstract: A rendering process for rendering an image frame and a postprocess for adapting the image frame to a display are separated. A rendering processing unit 42 generates an image frame sequence by performing rendering at a predetermined frame rate regardless of a condition that the image frame should meet for output to the display. A postprocessing unit 50 subjects the image frame sequence generated by the rendering processing unit to a merge process so as to generate and output an updated image frame sequence that meets the condition. Since the rendering process and the postprocess are separated, the image frame sequence can be generated regardless of the specification of the display such as resolution and frame rate of the display.

Abstract: In one embodiment, a system includes logic adapted for receiving a command from a first system, logic adapted for determining which resources are required to process the command, logic adapted for checking for the required resources before receiving data associated with the command, logic adapted for receiving the data from the first system, logic adapted for checking for the required resources after receiving the data when the checking for the required resources before receiving data indicated that the required resources were not available before receiving the data, logic adapted for sending a status to the first system if the required resources are not available after receiving the data, and logic adapted for processing the command if the required resources are available either before receiving the data or after receiving the data. In more embodiments, a method and computer program product for processing a command are also presented.

Abstract: An information processing apparatus includes a memory and a processor coupled to the memory. The processor is configured to execute a process including acquiring control information of a first application program of which execution result is displayed, extracting a dependency relationship between the first application program and a second application program on a basis of the control information, and determining whether an access request for a device from the second application program is granted on a basis of the dependency relationship.

Abstract: There is provided a data transmission apparatus, an image processing apparatus and a program, capable of preventing data from being transmitted to a destination to which the data should not be transmitted, in the case where there is a possibility that the data is forwarded to a destination other than the destination designated at the time of the transmission. When an address designated as a transmission destination has a possibility that data is forwarded to another address, such as an address of a mailing list, a forward destination information determining/acquiring unit acquires the information of the forward destination. When the forward destination includes the address that does not correspond to the transmission-permitted address held in a transmission-permitted address holder unit, an e-mail transmission canceling unit cancels the transmission to the address to which the transmission is not permitted.

Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

Abstract: A stream data control server includes: a processable flow rate managing unit which manages a processable flow rate corresponding to an amount of data per unit time, which can be processed in each of storage units serving as storing destinations; a classified data flow rate managing unit which manages a data flow rate corresponding to an amount of data processed per unit time for each class of data to which a data priority is attached; and a storing destination control unit which controls the storing destinations of respective data based upon the processable flow rate of each of the storage units and the data flow rate for each class in such a manner that the data having higher data priorities are stored in the storage units having higher priorities within a range of the processable flow rate of each of the storage units.

Abstract: A method, apparatus, and computer program product for discovering network paths between network devices in a distance-vector network are provided. The method may include providing a node model of network devices in a distance-vector network. The node model may include a network address corresponding to a network device. The network address may be used to query the network device for routing information. This routing information may be used to identify another network address corresponding to a second network device, and to identify a path from the first network device to the second network device. These devices and the path therebetween may be mapped in the node model. Finally, the second network device may be queried for subsequent routing information to identify and map subsequent devices and paths.

Abstract: A system, a controller, and a method for transmitting and distributing a data stream from a host to a storage device having a non-volatile memory and a chip are provided. A specific mark is added into a data stream which is transmitted from the host to the storage device, such that the data stream can be dispatched to the chip by transmitting a write command. Then, a response message generated by the chip can be received inerrably by executing a plurality of read commands.

Abstract: Systems and methods for establishing a data connection between a mobile device and a peripheral. The mobile device is configured to determine whether to handle user approval of the data connection between the mobile device and the peripheral. Through the mobile device, an input mechanism is provided for the user to provide input. The input is used in determining whether to approve the data connection between the mobile device and the peripheral.

Abstract: A smart flash drive has one or more levels of smart storage switches and a lower level of single-chip flash devices (SCFD's). A SCFD contains flash memory and controllers that perform low-level bad-block mapping and wear-leveling and logical-to-physical block mapping. The SCFD report their capacity, arrangement, and maximum wear-level count (WLC) and bad block number (BBN) to the upstream smart storage switch, which stores this information in a structure register. The smart storage switch selects the SCFD with the maximum BBN as the target and the SCFD with the lowest maximum WLC as the source of a swap for wear leveling when a WLC exceeds a threshold that rises over time. A top-level smart storage switch receives consolidated capacity, arrangement, WLC, and BBN information from lower-level smart storage switch. Data is striped and optionally scrambled by Redundant Array of Individual Disks (RAID) controllers in all levels of smart storage switches.

Abstract: An accessory for use with a portable computing device is provided. The accessory includes a keypad and a pedestal to house the control circuitry and provide mechanical stability for the accessory. The accessory includes a metal mass that performs dual functions of providing the mass for stability as well as acting as a ground connection for the keypad and other control circuitry. The accessory includes a connector for interfacing with a portable computing device and an additional connector for interfacing with an additional accessory.

Abstract: A SAS expander configured to operate as a SAS expander hub receives IO requests from connected SAS expanders and relays the IO requests to SAS expanders connected to data storage devices capable of servicing such IO requests.

Abstract: A system and method for determining media to be exported out of a media library is described. In some examples, the system determines a media component to be exported, determines the media component is in the media library for a specific process, and exports the media component after the process is completed.

Abstract: A method and apparatus for resource management in a multicore processor is disclosed. A system management controller (130) provides omnipresent scheduling, synchronization, load balancing, and power and memory management services to each processing resource (150) within in a multicore processor (10), via a plurality of system management clients (120) implemented in hardware or software. The controller (130) allocates the tasks executing in each processing resource (150) by means of interrupt control signals, which interact directly with the system management clients (120), enabling processing resources (150) to autonomously create, execute and distribute tasks around a parallel system architecture whilst monitoring and policing the use of shared system resources (140).

Abstract: An apparatus for peer-to-peer communication over a Universal Serial Bus (USB) link, the apparatus comprising a USB 3.0 compliant switch to be coupled between a first peer unit and a second peer unit to form a first path, wherein each of the first peer unit and the second peer unit supports a USB type of communication a USB 2.0 compliant bridge to be coupled between the first peer unit and the second peer unit to form a second path a detector to detect the USB type of each of the first peer unit and the second peer unit and a controller to establish the USB type of communication between the first peer unit and the second peer unit over a USB link via the first path or the second path, wherein the controller is configure to selectively switch the USB link to the first path or the second path based on the USB types of the first peer unit and the second peer unit.

Abstract: A SAS expander or initiator places PHYs in a wide port into a persistent reduced power state by signaling to the connected SAS device that the SAS expander or initiator intends to route data traffic through other PHYs in the wide port. The SAS expander or initiator and connected SAS device agree to disuse certain PHYs so that the PHYs enter a reduced power state according to SAS standards.

Abstract: In a virtualized computer system in which a guest operating system runs on a virtual machine of a virtualized computer system, a computer-implemented method of providing the guest operating system with direct access to a hardware device coupled to the virtualized computer system via a communication interface, the method including: (a) obtaining first configuration register information corresponding to the hardware device, the hardware device connected to the virtualized computer system via the communication interface; (b) creating a passthrough device by copying at least part of the first configuration register information to generate second configuration register information corresponding to the passthrough device; and (c) enabling the guest operating system to directly access the hardware device corresponding to the passthrough device by providing access to the second configuration register information of the passthrough device.

Abstract: A method for communication between an initiator system and a block storage cluster may include receiving a first command at a first storage system included in a plurality of storage systems of the block storage cluster. The method may also include transmitting a referral response from the first storage system to the initiator system when at least a portion of the data associated in the first command is stored by a second storage system. The method may further include obtaining a segment start value and a corresponding port identifier based on the referral response, and directing a second command to at least a second storage system included in the plurality of storage systems of the block cluster.

Abstract: Peripherals and data processing systems are disclosed which can be configured to interact based upon sensor data. In one embodiment, a peripheral, which is configured to be used with a data processing system, includes an interface to couple the peripheral to the data processing system, and at least one sensor, such as a proximity sensor, to sense a user of the peripheral, and a processor coupled to the interface and to the at least one sensor, wherein the processor configures the peripheral in response to data from the at least one sensor. The peripheral may communicate sensor data from its sensors to the data processing system, which may be a wireless PDA, and the data processing system analyzes the sensor data from its sensors and from the peripheral's sensors to decide how to configure the peripheral and/or the data processing system based on the sensor.

Abstract: Techniques are provided for managing, within a storage system, the sequence in which I/O requests are processed by the storage system based, at least in part, on one or more logical characteristics of the I/O requests. The logical characteristics may include, for example, the identity of the user for whom the I/O request was submitted, the service that submitted the I/O request, the database targeted by the I/O request, an indication of a consumer group to which the I/O request maps, the reason why the I/O request was issued, a priority category of the I/O request, etc. Techniques are also provided for automatically establishing a scheduling policy within a storage system, and for dynamically changing the scheduling policy in response to changes in workload.

Abstract: A circuit including a first memory and a processor. The processor is configured to receive data from a host device and transfer the data from the circuit to a storage drive. The processor is configured to receive the data back from the storage drive when a second memory in the storage drive does not have available space for the data, and prior to the data being transferred from the second memory to a third memory in the storage drive. The processor is configured to: store the data received from the storage drive in the first memory or transfer the data received from the storage drive back to the host device; and based on a request received from the storage drive, transfer the data from the first memory or the host device back to the storage drive. The request indicates that space is available in the second memory for the data.

Abstract: Methods and systems for direct device access are disclosed. Aspects of one method may include a plurality of GOSs directly accessing a first network interface device, where the first network interface device may provide access to a network. One or more of the GOSs may be migrated to directly access a second network interface device, based on state information for each of the GOSs, where the state information may be maintained by the host. The GOSs may communicate data to a device coupled to the network by direct accessing the first and/or second network interface device. Similarly, the first and/or second network interface device may communicate data received from a device coupled to the network to one or more of the plurality of GOSs via direct access of the first and/or second network interface device.

Abstract: A queue overflow prevention method and apparatus for Hard Disk Drive (HDD) protection in a computer system is provided. The queue overflow prevention method includes measuring acceleration information of the system, determining if the system is in a stable status or an unstable status using the acceleration information, and, while the system is in the unstable status, restricting the generation of a disk Input/Output (I/O) request.

Abstract: Memory associated with a mobile communication device, such as memory removably inserted into a memory card slot, may be accessed, in the alternative, by a mobile communication platform or by a remote USB host. A memory access module connected to the memory card slots is operative in one of two modes: a pass-through mode and a USB mode. In the pass-through mode, the memory card slots are directly connected, via switching circuits, to memory interfaces on the mobile communication platform. A USB interface on the mobile communication platform may additionally be connected, in pass-through mode, via a USB hub to a remote USB host. In the USB mode, the memory card slots are connected, via switching circuits, second memory interfaces, and a controller, to a USB hub supporting USB 3.0 transfer protocols, and accessible by a remote host.

Abstract: A method and apparatus for intelligently routing and managing audio signals within an electronic device is disclosed. The routing is responsive to a set of logical and physical policies which are stored in data tables which can be updated as needed.

Abstract: A buffer management mechanism in a multi-core processor for use on a modem in a telecommunications network is described herein. The buffer management mechanism includes a buffer module that provides buffer management services for one or more Layer 2 applications, wherein the buffer module at least provides a user space application interface to application software running in user space. The buffer management mechanism also includes a buffer manager that manages a plurality of separate pools of tokens, wherein the tokens comprise pointers to memory areas in external memory. In addition, the buffer management mechanism includes a custom driver that manages Data Path Acceleration Architecture (DPAA) resources including buffer pools and frame queues to be used for user plane data distributing.

Abstract: In a set device having a card host LSI, high-speed data transmission to a removable card or the like is realized without hindering a reduction in size and weight. The card host LSI and the removable card are connected to a card bus complying with predetermined card bus specifications. A microcomputer module and the card host LSI are connected also by a card bus complying with the predetermined card bus specifications.

Abstract: The computer system includes a server being configured to manage a first virtual machine to which a first part of a server resource included in the server is allocated and a second virtual machine to which a second part of the server resource is allocated. The computer system also includes a storage apparatus including a storage controller and a plurality of storage devices and being configured to manage a first virtual storage apparatus to which a first storage area on the plurality of storage devices is allocated and a second virtual storage apparatus to which a second storage area on the plurality of storage devices is allocated. The first virtual machine can access to the first virtual storage apparatus but not the second virtual storage apparatus and the second virtual machine can access to the second virtual storage apparatus but not the first virtual storage apparatus.

Abstract: A system and method for configuring expansion bus links to generate a double-bandwidth link slot are disclosed. An information handling system includes a central processing unit (CPU) and memory operable to store program instructions executable by the CPU. A chip set operably couples the CPU and the memory to a first slot and a second slot. The chipset includes a root port that generates a first link coupled to the first slot and a second link coupled to the second slot. An adapter card is inserted into either of the first or second slots such that the adapter card routes either the first or second link to the slot not populated by the adapter card.

Abstract: Machine implemented method and system is provided. The method includes sending a packet to a device by a computing system; determining an address for the packet, where an interface logic for the device determines the address; updating a location associated with the address; where the interface logic for the device updates the location; updating a bitmap value associated with the location to indicate to a processor for the device that a location associated with the address has been updated; where the interface logic updates the bitmap value; clearing the bitmap value by writing a same value that is read by the processor for the device; and processing the packet received by the device.

Abstract: It is an object of the invention to ensure the reliable and flawless operation of a storage means that is connected to a data reproduction system. This object will be met by a method for controlling the admission of a storage means to a peripheral bus of a data reproduction system, wherein a storage means is connected to the peripheral bus of a data reproduction system, the read latency of the storage means is determined, and it is decided based on the determined read latency whether the storage means is admitted to the peripheral bus or rejected. The latency for read requests from the storage means, for instance a USB mass storage device, will be analyzed on first insertion and the results of this analysis will be used to carry out a compatibility check of the storage means with the data reproduction system, for example a car audio system.

Abstract: Methods and systems for migrating data between storage tiers may include various operations, including, but not limited to: determining at least one activity index of at least one data storage region; receiving an input/output request addressing at least one data segment included in the at least one data storage region; qualifying a data segment addressed by the input/output request for migration to at least one higher-performing storage device; and adding a data segment reference associated with a qualified data segment to a priority queue according to the at least one activity index.

Abstract: A communication apparatus includes a radio frequency circuit that operates on a radio frequency signal and a digital processing circuit coupled to the radio frequency circuit. The digital processing circuit includes a plurality of bus masters coupled to a shared bus. A bus arbiter is provided for arbitrating between requests to access the bus by a first bus master and one or more other bus masters. Accesses by the one or more other bus masters to the bus are restricted in response to a signal indicative of a change in a mode of operation of the RF circuit. In one particular implementation, a communication apparatus employs time domain isolation wherein the digital processing circuit may be placed in a shutdown mode when the radio frequency circuit is active.

Abstract: A fieldbus gateway using a virtual serial fieldbus port and a data transmission method thereof are provided. By receiving a fieldbus frame containing target data through a virtual serial fieldbus port connected to a source device or a target device via a fieldbus gateway and sending another fieldbus frame containing the target data via other fieldbus port to target devices or source devices, the system and the method can provide two or more remote devices to control one controlled device at the same time. The invention also achieves the effect of using one virtual serial fieldbus port to transmit data between multiple source devices and target devices concurrently.

Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

Abstract: Systems and methods of re-enumerating peripheral devices operatively connected to a computer system are provided. In one example, a system is configured to disable an existing connection between an operating system and a peripheral device established through a device driver by re-describing the peripheral device to the OS. In another example, the system can be further configured to execute operation(s) on the peripheral device without new driver installation using communication channels native to the OS. Once the operation(s) are complete, the system can be configured to restore the existing connection.

Abstract: A method of enabling access to resources includes detecting an input to access a resource of a multi-mode processing module coupled to a host processor and a control module. The method can further include detecting an operating mode of the host processor and the control module and an availability of independent peripheral resources of the multi-mode processing module. Additionally, the method can enable the multi-mode processing module in response to the detecting the operating mode and the availability of the independent peripheral resources.

Abstract: Various embodiments include fault tolerant memory apparatus, methods, and systems, including a memory manager for supplying read and write requests to a memory device having a plurality of addressable memory locations. The memory manager includes a plurality of banks. Each bank includes a bank queue for storing read and write requests. The memory manager also includes a request arbiter connected to the plurality of banks. The request arbiter removes read and write requests from the bank queues for presentation to the memory device. The request arbiter includes a read phase of operation and a write phase of operation, wherein the request arbiter preferentially selects read requests for servicing during the read phase of operation and preferentially selects write requests for servicing during the write phase of operation.

Abstract: An input display device comprises an operation panel including a first display operation area that enables operation screens to be switched hierarchically based on a selected operation key and to display a fixed-arrangement of operation keys in respective layers, and a second display operation area that displays an operation history indicating that the operation key has been selected; a selected key use determination unit configured to determine which of the operation keys has been selected when the operation key is selected from one of the first display operation area and the second display operation area; a storage processing unit configured to successively store results determined by the selected key use determination unit into a storage device as operation history information; and a selected key use history display control unit configured to display the operation history information stored in the storage device into the second display operation area.

Abstract: Described embodiments provide a host subsystem that generates a host context corresponding to a received host data transfer request. A programmable sequencer generates one or more sequencer contexts based on the host context. Each of the sequencer contexts corresponds to at least part of the host data transfer request. The sequencer contexts are provided to a buffer subsystem of the media controller. For host read requests, the buffer subsystem retrieves the data associated with the sequencer contexts of the read request from a corresponding buffer or a storage media and transmits the data associated with the sequencer contexts to the host device. For host write requests, the buffer subsystem receives the data associated with the host context from the host device and stores the data associated with the sequencer contexts of the write request to a corresponding buffer or the storage media.

Abstract: A wireless mesh includes a plurality of user devices. A list is formed that includes information regarding peripheral devices associated with the user devices. One of the user devices identifies one or more of the peripheral devices that correspond to a particular type of peripheral device and selects, from the identified peripheral devices, a particular peripheral device. The particular peripheral device is associated with another user device, and the user device forms a session, with the other user device, that enables the user device to provide commands to the particular peripheral device via the other user device.

Abstract: The present invention is directed to a method and system for efficient write journal entry management maintaining minimum write journal information stored in a nonvolatile memory through utilizing an additional structure in a fast volatile memory. The method and system may manage write journaling of a file volume including multiple fixed sized regions and assign a persistent 1-bit synchronization status (the write journal information) to each data region. In addition, a non-persistent I/O counter (the additional structure) for each region to manage the persistent 1-bit synchronization status during run-time. The present invention may provide a mechanism to determine when write I/O operations have not successfully completed to a specific region of the file volume.