Abstract: Methods for Error Correction Code (ECC) decoding include producing syndromes from a set of bits, which represent data that has been encoded with the ECC. An Error Locator Polynomial (ELP) is generated based on the syndromes. At least some of the ELP roots are identified, and the errors indicated by these roots are corrected. Each syndrome may be produced by applying to the bits vector operations in a vector space. Each syndrome is produced by applying vector operations using a different basis of the vector space. The ELP may be evaluated on a given field element by operating on ELP coefficients using serial multipliers, wherein each serial multiplier performs a sequence of multiplication cycles and produces an interim result in each cycle. Responsively to detecting at least one interim result indicating that the given element is not an ELP root, the multiplication cycles are terminated before completion of the sequence.

Abstract: A method for controlling a message-passing algorithm (MPA) based decoding operation includes: gathering statistics data of syndromes obtained from executed iterations; and selectively adjusting a decoding operation in a next iteration to be executed according to the statistics data. A control apparatus for controlling an MPA based decoder includes an adjusting circuit and a detecting circuit. The detecting circuit is coupled to the adjusting circuit, and used for gathering statistics data of syndromes obtained from executed iterations, and selectively controlling the adjusting circuit to adjust a decoding operation in a next iteration to be executed according to the statistics data.

Abstract: An ECC circuit can operate in a plurality of error correction modes with different correcting capabilities for data stored in a memory. The ECC circuit calculates a syndrome with respect to information data in accordance with an error correction mode set by a control part and adds a syndrome of a fixed length in which dummy bits are added to the calculated syndrome, to the information data. When code data is read out, the ECC circuit performs a correction process on the code data by using the syndrome included in the code data.

Abstract: A method and an apparatus for transmitting and receiving a packet in a broadcasting and communication system are provided. The method and apparatus allows a receiver to recognize data in a packet lost due to data loss occurring in a network. To this end, Forward Error Correction (FEC) control-related information is generated, a packet including the generated FEC control-related information is generated, and the packet is transmitted. The FEC control-related information includes at least one of FEC configuration-related information and FEC encoding configuration-related information.

Abstract: The invention disclosed in this application describes a diversity combiner that operates as a maximal ratio combiner (MRC) when no interference is detected and as a selection combiner when OFDM symbol errors are detected with high probability.

Abstract: The invention discloses a method and an apparatus for data check processing, the method comprises: acquiring data to be checked; acquiring a first polynomial matrix F according to a generator polynomial; acquiring a second generator polynomial matrix Fi according to Fi=Fi, wherein i is the digit of the data; generating a CRC code of the data from the second generator polynomial matrix Fi, initial CRC register value X(0) and the data; and sending the data and the CRC code to a receiver for being checked by the receiver. Through the present invention, the problem that the load of registers is increased when the number of digits of the data needing to be checked is not the nth power of 2 in the conventional art is solved, and the effect of reducing the load of registers is achieved.

Abstract: A device and method for attaching a CRC code to a transport block and turbo encoding the CRC attached transport block, where the transport block has a predetermined size.

Abstract: Exemplary embodiments for providing multi-bit error correction based on a BCH code are provided. In one such embodiment, the following operations are repeatedly performed, including shifting each bit of the BCH code rightward by 1 bit while filling the bit vacated due to the rightward shifting in the BCH code with 0, calculating syndrome values corresponding to the shifting of the BCH code, and determining a first error number in the BCH code under the shifting based on the syndrome values corresponding to the shifting of the BCH code. In the case where the first error number is not equal to 0, modified syndrome values are calculated corresponding to the shifting of the BCH code. The modified syndrome values are those corresponding to the case that the current rightmost bit of the BCH code under the shifting is changed to the inverse value. Additional operations are performed as described herein.

Abstract: A non-volatile memory device includes addressable sectors and an ancillary volatile memory array. The ancillary volatile memory array stores protection information in the addressable sectors that is not accessible to users of the memory. The protection information is downloaded in the memory array at every power-on of the memory device. The memory array includes at least two additional columns containing preset logic information physically adjacent to the columns containing the downloaded information. A logic circuit is input with the logic information read from the additional check columns for checking the integrity of the preset logic information content of the check columns. An integrity check signal is output by the logic circuit.

Abstract: A method of wireless data communication between a hearing instrument and another device, includes receiving N data packages A1, A2, . . . , AN, wherein the N data packages are obtained by dividing a data package D, receiving data package C, wherein the data package C is formed as a function of A1, A2, . . . , AN in accordance with a relationship C=(A1, A2, . . . , AN), performing error detection, and recovering AE, one of the data packages A1, A2, . . . , AN that contains an error, in accordance with a relationship AE=(A1, A2, . . . , C, . . . , AN), in which A1, A2, . . . , C, . . . , AN indicates that the data package C is used in place of AE in a list of arguments for the function .

Abstract: A method and memory device is provided for reading data from an ECC word of a plurality of reference bits associated with a plurality of memory device bits and determining if a double bit error in the ECC word exists. The ECC word may be first toggled twice and the reference bits reset upon detecting the double bit error.

Abstract: An exemplary method of communicating with a safety device includes obtaining a key from the safety device that is useable for only a single communication session with the safety device. A plurality of messages are sent to the safety device during the single communication session. Each of the plurality of messages includes the obtained key, an identifier of the source of the message, an identifier of the safety device, a sequence number indicating how many of the plurality of messages preceded the message during the communication session, a command for the safety device, and at least one cyclic redundancy code (CRC) based on content of the message. A next one of the plurality of messages is sent only after confirming that the safety device has accepted a most recently sent one of the plurality of messages.

Abstract: Apparatus and methods for generating checksums may process two or more segments of a message in parallel, and may be used with a communications channel having time slots. An apparatus may include a cumulative checksum generator to generate a cumulative checksum for a message, a partial checksum generator to generate one or more partial checksums from one or more respective message segments, and a speculative checksum generator to generate a speculative checksum for each of one or more time slots. In one aspect, a partial checksum corresponding with an initial segment of the message may be generated from at least an initialization vector. A speculative checksum selector may select a first speculative checksum for use in determining whether the message was transmitted without error. The generating of partial and speculative checksums results in a maximally pipe-lined architecture with speed limited only by a minimal cumulative CRC calculation that is fundamentally unavoidable.

Abstract: Single CRC polynomial for both turbo code block CRC and transport block CRC. Rather than employing multiple and different generation polynomials for generating CRC fields for different levels within a coded signal, a single CRC polynomial is employed for the various levels. Effective error correction capability is achieved with minimal hardware requirement by using a single CRC polynomial for various layers of CRC encoding. Such CRC encoding can be implemented within any of a wide variety of communication devices that may be implemented within a wide variety of communication systems (e.g., a satellite communication system, a wireless communication system, a wired communication system, and a fiber-optic communication system, etc.). In addition, a single CRC check can be employed within a receiver (or transceiver) type communication device for each of the various layers of CRC of a received signal.

Abstract: Techniques for generating soft values for parity bits in a convolutional decoding process are disclosed. An exemplary method comprises, for each of at least one iteration in at least one soft-input soft-output decoder, calculating intermediate probability values for each possible transition between a first plurality of candidate decoder states at a first time and a second plurality of candidate decoder states at a second time. Two or more partial sums are then computed from the intermediate probability values, wherein the partial sums correspond to possible combinations of two or more systematic bits, two or more parity bits, or at least one systematic bit and at least one parity bit. Soft values, such as log-likelihood values, are then estimated for each of at least one systematic bit and at least one parity bit of the received communications data corresponding to the interval between the first and second times, based on the partial sums.

Abstract: A storage device disclosed in the present application includes a device-error-codes table, first-information indicating a process-setting that can be changed by a device-state, and second-information indicating a process-setting that is a previously determined by a device-error-type, are associated with each other; a management-unit that adds information indicating a change in the second-information to the second-information stored in the table; a determining-unit that determines the device-error-type; an acquiring unit that acquires, from the table, the first-information; an information-converter that determines whether or not information indicating a change in the second-information, and changes the first-information by the acquiring unit; a transmitter that transmits the first-information by the acquiring unit or changed by the information-converter to a storage-device-controller; and an information-transmitter that receives, from the controller, a request to transmit the second-information and transmits,

Abstract: In a multi-antenna communication system using LDPC codes, a simple method is used to effectively improve the received quality by performing a retransmittal of less data without restricting applicable LDPC codes. In a case of a non-retransmittal, a multi-antenna transmitting apparatus transmits, from two antennas, LDPC encoded data formed by LDPC encoding blocks. In a case of a retransmittal, the multi-antenna transmitting apparatus uses a transmission method, in which the diversity gain is higher than in the previous transmission, to transmit only a part of the LDPC encoded data as previously transmitted. For example, the only the part of the LDPC encoded data to be re-transmitted is transmitted from the single antenna.

Abstract: An apparatus generates a checksum for a payload having a number of payload symbols. The apparatus includes a coder for coding the payload. The coder is configured to combine a current payload symbol and a previous coding symbol or an initialization symbol to obtain a combined symbol, and map the combined symbol using a mapping rule to obtain a current coding symbol. The mapping rule is based on a power of two or more of a companion matrix of a characteristic polynomial of a linear feedback shift register. The apparatus is configured such that the checksum corresponds to the current coding symbol, when the number of payload symbols is processed by the coder, the number being one or greater than one.

Abstract: An amount of time and an error rate function are received, where the error rate function defines a relationship between a number of iterations associated with iterative decoding and an error rate. A testing error rate is determined based at least in part on the amount of time. The number of iterations which corresponds to the testing error rate in the error rate function is selected to be a testing number of iterations; the testing error rate and the testing number of iterations are associated with testing storage media using iterative decoding.

Abstract: A method which makes use of the syndrome information at each iteration, combined with the bit reliability information available at a FEC decoder, to extract the minimum estimated bit error configuration, i.e. the block which is closest to the transmitted codeword during the decoding process, and to select such block if the result at the final decoding iteration has a higher number of estimated bit errors.

Abstract: Techniques are described to store and retrieve an encoded info bit stream, and appropriate first and second sets of parity bits to perform interleaving and rate matching, prior to transmission. On the receiver side, a recovery technique is provided which operates on the same principle as that of encoding, but decoding occurs in reverse. In accordance with an exemplary embodiment, three dedicated logical memories are provided for each of the encoded info bit stream and two sets of parity bits, respectively. The proposed solution provides an alternative methodology and/or hardware implementation for performing LTE compliant rate matching and de-rate matching when required to interleave info bits and parity bits.

Abstract: A technique for reducing parity bit-widths for check bit and syndrome generation through the use of additional check bits to increase the number of minimum weighted codes in the Hamming Code H-Matrix. The technique of the present invention may be implemented while adding no additional correction/detection capability, in order to reduce the number of data bits that are used for each check bit/syndrome generation and to reduce the width of the parity generating circuitry.

Abstract: Adaptive error resilience for streaming video transmission over a network is provided. In one embodiment, a method of transmitting a plurality of packets comprises generating a first proactive repair redundancy information for a first data packet; adding the first proactive repair redundancy information to a second data packet; generating a second proactive repair redundancy information for the first data packet; adding the second proactive repair redundancy information to a repair packet; and transmitting the plurality of packets, wherein the plurality of packets includes the first data packet and at least one of the second data packet and the repair packet.

Abstract: A method for processing Forward Error Correction, FEC, data, which includes: a sender encapsulates the FEC data to be a Transport Stream, TS, message, sets FEC identification information in the TS message, and encapsulates the TS message to be a Real-time Transport Protocol, RTP, message; then sends the RTP message to a terminal side. The reception end receives the RTP message; if the reception end has a function for FEC decoding, the reception end identifies the FEC data according to the FEC identification information in the TS message of the received RTP message, and recovers the missed media message according to the FEC data; if the reception end does not have the function for FEC decoding, the reception end processes the RTP message after removing the message header. The embodiments of the present invention also provide a transmission and processing device.

Abstract: The present disclosure relates to a method for detecting a parity error in a sequence of DQPSK symbols of a digital transmission system, comprising determining a first demodulated symbol r1; determining a second demodulated symbol r2; determining a first parity symbol p1; determining a second parity symbol p2; determining a super-parity symbol q1; and detecting a parity error in the sequence of DQPSK symbols by comparing a combination of the first parity symbol p1 and the second parity symbol p2 against the super-parity symbol q1, wherein a parity between two DQPSK symbols describes a phase difference between the two DQPSK symbols.

Abstract: A method and apparatus generates a forward error correcting code for use with a plurality of source packets to be transmitted over a network. In one exemplary embodiment, the method comprises identifying a plurality of candidate packet masks and selecting that one of the masks that has the lowest expected residual packet loss value (“RPL”). RPL is calculated using an effective recovery rate, which is in turn is a function of at least one network performance parameter (such as packet loss) and one or more channel code parameters such as the number of source packets and/or FEC packets. The error correcting code can be generated using the selected packet mask and at least one of the source packets.

Abstract: A controller to control a memory system including a memory device. The controlling the memory system may include calculating an error location polynomial in a received read vector with a key equation solving unit of the memory system to read data from the memory device, estimating the number of errors in the received read vector with a control unit of the memory system according to at least one of the calculated error location polynomial and information on the error location polynomial, searching error locations of the received read vector according to the calculated error location polynomial with a chien search unit of the memory system with the control unit. A cycle-per power consumption of the chien search unit may be adjusted with the control unit. A maximum correction time may be adjusted according to the number of errors of the read vector.

Abstract: Apparatus and methods are disclosed, such as those that store data in a plurality of non-volatile integrated circuit memory devices, such as NAND flash, with convolutional encoding. A relatively high code rate for the convolutional code consumes relatively little extra memory space. In one embodiment, the convolutional code is spread over portions of a plurality of memory devices, rather than being concentrated within a page of a particular memory device. In one embodiment, a code rate of m/n is used, and the convolutional code is stored across n memory devices.

Abstract: A method is disclosed for updating parity information in a RAID 6 system wherein only one parity block is read during each write operation. Both parity blocks may be updated from the new data, the data being overwritten and either of the old blocks of parity information. A method for load balancing in a RAID 6 system using this method is also disclosed.

Abstract: A low-density parity check (LDPC) code decoding method may be provided. The LDPC code decoding method may linearize or perform step-approximation on a natural logarithm hyperbolic cosine function included in a check node updating equation of a sum-product algorithm used for decoding an LDPC code, and may convert the linearized function to correspond to a check node updating equation of a min-sum algorithm.

Abstract: Methods and apparatus are provided for processing a data value in a read channel of a memory device. The data value provided to a general purpose processor for processing. The data value is not decoded data and may comprise one or more of a raw data value and an intermediate data value. The data value can be provided to the general purpose processor, for example, upon a detection of one or more predefined trigger conditions. A data value can be obtained from a memory device and then be redirected to a general purpose processor. The data value is not decoded data. The redirection can be conditionally performed if one or more predefined bypass conditions exist. The general purpose processor is optionally time-shared with one or more additional applications.

Abstract: Techniques are provided for receiving a transmitted first packet that was formatted using a known scrambling algorithm with an unknown scrambling seed. An encoded packet payload is extracted from the first packet header. The encoded packet payload header is decoded to obtain a first scrambled packet payload header. For each potential value of the unknown seed, the first scrambled packet payload header is descrambled to produce a first set of descrambled packet payload headers and for each potential value of initial register values associated with a cyclic redundancy check, the cyclic redundancy check is executed comprising polynomial division on each of the descrambled packet payload headers such that when the polynomial division results in a zero remainder, a potential unscrambled payload header for the first packet is obtained. Information about the first packet is obtained from the potential unscrambled payload header.

Abstract: According to one embodiment, a wireless communications device includes a low-density parity check (LDPC) decoder configured to receive a codeword associated with a parity check H-matrix. The LDPC decoder includes multiple processing elements coupled to a memory for storing the parity check H-matrix comprising R rows and C columns. Each processing element is configured to perform LDPC decoding on different rows of the H-matrix during multiple sub-iterations. A first portion of the processing elements are configured to process certain rows in an upward direction in the H-matrix relative to other rows and a second portion of the processing elements are configured to process other certain rows in a downward direction in the H-matrix relative to the other rows.

Abstract: An apparatus and a method for transmitting and receiving a signal in a communication system are provided. The method includes checking a type of the signal to be transmitted; determining a number of puncture bits according to the type of the signal; and puncturing an encoded signal to be transmitted according to the number of puncture bits.

Abstract: Overlapping sub-matrix based LDPC (Low Density Parity Check) decoder. Novel decoding approach is presented, by which, updated bit edge messages corresponding to a sub-matrix of an LDPC matrix are immediately employed for updating of the check edge messages corresponding to that sub-matrix without requiring storing the bit edge messages; also updated check edge messages corresponding to a sub-matrix of the LDPC matrix are immediately employed for updating of the bit edge messages corresponding to that sub-matrix without requiring storing the check edge messages. Using this approach, twice as many decoding iterations can be performed in a given time period when compared to a system that performs updating of all check edge messages for the entire LDPC matrix, then updating of all bit edge messages for the entire LDPC matrix, and so on. When performing this overlapping approach in conjunction with min-sum processing, significant memory savings can also be achieved.

Abstract: A semiconductor memory device includes a plurality of data input/output pads configured to transmit and receive data to and from memory cells, an alert pad configured to output data error information while the data is transmitted and received, and a monitoring device configured to output the data error information to the alert pad in a first mode and to output monitoring information to the alert pad in a second mode.

Abstract: A decoding apparatus for performing decoding processing of encoded data by using non-binary LDPC codes, includes: a logarithmic Fourier transform processing section, a variable node processing section, an edge coefficient processing section, and a check node processing section, wherein the logarithmic Fourier transform processing section performs Fourier transform processing and logarithmization processing on a probability vector of a symbol of an encoded frame data to output an initial value of logarithmic Fourier domain probability vector, and the variable node processing section, the edge coefficient processing section, and the check node processing section perform iteration processing by using a logarithmic Fourier domain probability vector.

Abstract: Disclosed is an error correcting method which includes detecting an error of meta data having a seed used to randomize user data; correcting the error of the meta data when the error is detected from the meta data; receiving the user data based upon seed confirmation information associated with an error existence of the seed or an error correction result of the seed; detecting an error of the user data; and correcting the error of the user data when the error is detected from the user data.

Abstract: Various embodiments of the present invention provide systems and methods for variable iteration data processing.

Abstract: Systems and methods are provided for implementing various aspects of a Reed-Solomon (RS) error-correction system. A detector can provide a decision-codeword from a channel and can also provide soft-information for the decision-codeword. If the decision-codeword corresponds to an inner code and an RS code is the outer code, a soft-information map can process the soft-information for the decision-codeword to produce soft-information for a RS decision-codeword. A RS decoder can employ the Berlekamp-Massey algorithm (BMA), list decoding, and a Chien search, and can include a pipelined architecture. A threshold-based control circuit can be used to predict whether list decoding will be needed and can suspend the list decoding operation if it predicts that list decoding is not needed.

Abstract: Disclosed are a decoding method and device for concatenated code, for the decoding of concatenated code composed of low density parity code (LDPC) and Reed-Solomon (RS) code. The method includes: carrying out LDPC soft decision iterative decoding on bit de-interleaved data flow, and carrying out check decision on LDPC codeword obtained from decoding by using a check matrix; carrying out de-byte-interleave on an information bit of the LDPC codeword obtained from decoding and converting check information of the LDPC codeword into puncturing information of RS codeword; selecting a decoding mode according to the puncturing information of the RS codeword to carry out RS decoding. By way of the solution of the present invention, the RS decoding performance can be improved without increasing the computation complexity, thus greatly improving the receiving performance of the CMMB terminal as compared to the conventional method.

Abstract: A description is given of an apparatus that includes a division unit configured to receive a data stream and to divide the received data stream into a plurality of data segments. The apparatus further includes a plurality of first CRC check units, wherein each of the first CRC check units is configured to perform a first CRC check of a respective one of the plurality of data segments, the plurality of first CRC checks being performed concurrently, and wherein each of the first CRC check units is configured to perform a second CRC check based on an output of the respective first CRC check unit.

Abstract: Disclosed is an RFID tag that is provided with a laminate forming a layered structure; an antenna disposed with respect to the laminate so as to enable external communication; and an RFID circuit electrically connected to the antenna. The laminate has a shielding member for shielding from radiation, and the RFID circuit is arranged in the laminate so as to be covered by the shielding member.

Abstract: A method of storing a set of metadata bits associated with each of multiple data words includes combining the set of metadata bits with each of the multiple data words to generate multiple extended data words. The method includes encoding each of the multiple extended data words to generate multiple codewords and puncturing each of the multiple codewords to generate multiple punctured codewords, where in each of the punctured codewords the set of metadata bits is removed. The method includes storing the multiple punctured codewords, transforming the set of metadata bits to generate a set of transformed metadata bits, and storing the set of transformed metadata bits.

Abstract: The disclosed technology provides systems and methods for encoding data based on a run-length-limited code and an error correction code to provide codewords. The codewords include RLL-encoded data that are produced based on the RLL code, and parity information that are produced based on the error correction code. The parity information is interleaved among the RLL-encoded data. In one embodiment, the codeword is produced by separately producing the RLL-encoded data and the parity information, and interleaving the parity information among the RLL-encoded data. In one embodiment, the codeword is produced by producing the RLL-encoded data, and using erasure decoding to compute the parity information.

Abstract: A storage medium includes at least one data unit defining a plurality of symbol-based inner code words and a plurality of symbol-based outer code words. Each symbol included in one of the inner code words is also included in one of the outer code words. A processor is configured to perform a first iteration of inner code error correction on the plurality of symbol-based inner code words, a first iteration of outer code error correction on the plurality of symbol-based outer code words and a second iteration of inner code error correction on the plurality of symbol-based inner code words. In the first iteration of outer code error corrections, at least one of the outer code words is correctable. In the second iteration of inner code error correction, at least one of the inner code words is correctable.

Abstract: A signal is encoded by receiving input data. A first portion of the input data is encoded to obtain a first set of encoded data. At least some part of the input data is processed to determine which one of a plurality of subsets the input data corresponds to. In the event the input data corresponds to a first subset having a greater signal margin (SM) than a second subset, the first set of encoded data and a second portion of the input data are output. In the event the input data corresponds to the second subset, the second portion of the input data is encoded to obtain a second set of encoded data and the first set of encoded data and the second set of encoded data are output.

Abstract: A method begins by a processing module receiving a plurality of record requests to record a broadcast of data. The method continues with the processing module encoding the data using an error coding dispersal storage function to produce a plurality of sets of encoded data slices. The method continues with the processing module generating a list of requesting device identities corresponding to the plurality of requests and storing the plurality of sets of encoded data slices and the list of requesting device identities in a dispersed storage network memory. The method continues with the processing module receiving a playback request from a device identified in the list of requesting device identities, generating a unique retrieval matrix for the device, and outputting a unique plurality of sets of encoded data slices from the plurality of sets of encoded data slices in accordance with the unique retrieval matrix.

Abstract: A wireless communications receiver for receiving data blocks, the receiver comprising: a reception unit arranged to receive a wireless signal, to recover from the wireless signal a data frame containing packets; and an LDPC decoder arranged to recover a data block by LDPC decoding one of the packets. A wireless communications receiver for receiving data blocks, the receiver comprising: a reception unit arranged to receive a wireless signal, to recover a data frame from the wireless signal and to recover an encoded block from the data frame; and an LDPC decoder arranged to recover a data block by LDPC decoding the encoded block. A wireless communications transmitter for transmitting data blocks, the transmitter comprising: an encoder arranged to create an encoded block by LDPC encoding a data block; and a transmit unit arranged to load the encoded block into a data frame as a, or as part of a, packet and transmit the data frame wirelessly.

Abstract: A forward error correction (FEC) block size is maintained at a constant size. Coding rate adjustments may be made by changing the number of information bits per symbol, or Forward Error Code (FEC) coding rate. Therefore, as the number of information bits per symbol is changed, the number of output bits is always maintained. The scheme permits for a greater flexibility and selection of effective data rates.