Abstract: A termination indication is computed during an iteration of an iterative decoding of a representation of a codeword according to a schedule. The termination indication is tested to see if the decoding has converged or is not likely to converge. The testing of the termination indication shows convergence or lack of likelihood thereof even if a codeword bit estimate was flipped during an immediately preceding traversal of the schedule. Preferably, the termination indication includes an error correction syndrome weight, a zero value whereof indicates convergence, and the computing of the termination indication includes, in response to the flipping of a codeword bit estimate, flipping the error correction syndrome bits that are influenced by that codeword bit estimate.

Abstract: Multiple data permutation operations in respective different dimensions are used to provide an overall effective data permutation using smaller blocks of data in each permutation than would be used in directly implementing the overall permutation in a single permutation operation. Data that has been permuted in one permutation operation is block interleaved, and the interleaved data is then permuted in a subsequent permutation operation. A matrix transpose is one example of block interleaving that could be applied between permutation operations.

Abstract: A method for encoding data bits includes computing checksum parity bits based on the data bits. A set of equations satisfied by the data bits and the checksum parity bits corresponds to a dense parity-check matrix. The dense parity-check matrix comprises sums of permutation sub-matrices.

Abstract: A sequence of data packets is received within an integrated circuit device and stored within a first memory thereof Error descriptor values are updated within a second memory of the integrated circuit device based on error information associated with the sequence of data packets. The error descriptor values each include an address field to specify a corresponding storage region of the first memory and an error field to specify an error status of data values stored within the storage region. A sequence of multiple-bit error values are generated based, at least in part, on the error fields and address fields within respective subsets of the error descriptor values. Concurrently with generation of at least one of the multiple-bit error values the state of one or more bits of the data values stored in the first memory based are changed based on a previously-generated one of the multiple-bit error values.

Abstract: A data reading method is provided. The data reading method includes: utilizing a first sense voltage to read a data unit from a flash memory block; performing an error detection operation on the data unit and calculating an error polynomial according to a detection result; and determining whether the error polynomial conforms to a predetermined condition and deciding whether to perform read retry on the data unit according to a determining result.

Abstract: Various embodiments of the present invention provide data processing circuits that include: a data detector circuit, a data decoder circuit, and a modification circuit. The data detector circuit is operable to apply a data detection algorithm to a data input to yield a detected output. The data decoder circuit is operable to apply a data decode algorithm to a decode input to yield a decoded output. The decode input is selected between at least the detected output, and a modified version of the detected output. The modification circuit is operable to receive the detected output and to provide the modified version of the detected output.

Abstract: Providing for single and multi-bit error correction of electronic memory is described herein. As an example, error correction can be accomplished by establishing a suspect region between bit level distributions of a set of analyzed memory cells. The suspect region can define potential error bits for the distributions. If a bit error is detected for the distributions, error correction can first be applied to the potential error bits in the suspect region. By identifying suspected error bits and limiting initial error correction to such identified bits, complexities involved in applying error correction to all bits of the distributions can be mitigated or avoided, improving efficiency of bit error corrections for electronic memory.

Abstract: A wireless communication system includes: a dividing unit to divide data into a plurality of first code blocks; a generation unit to generate first error detection information for each of the plurality of code blocks; a transmission unit to wirelessly transmit at least one of the plurality of first code blocks using a first channel and the first error detection information using a second channel; a reception unit to receive a plurality of second code blocks and second error detection information transmitted wirelessly; and a detection unit to execute error detection on each of the plurality of second code blocks using the second error detection information and to control a continuation of the error detection for the code blocks based on a result of the error detection.

Abstract: A memory storage device, a memory controller thereof, and a method for programming data thereof are provided. The memory storage device having an error checking and correcting (ECC) circuit and a rewritable non-volatile memory chip is coupled to a host system. The method includes determining whether write data to be written into the rewritable non-volatile memory chip belongs to a specific type. The method also includes generating at least one first type ECC code with a first length by the ECC circuit according to the write data if the write data belongs to the specific type. The method further includes generating at least one second type ECC code with a second length by the ECC circuit according to the write data if the write data does not belong to the specific type. In which, the first length is longer than the second length.

Abstract: A method and device for segmenting, CRC encoding and turbo encoding a CRC attached transport block.

Abstract: A method of identifying and protecting the integrity of a set of source data which produces and combines an identification signature with a detection and correction remainder and extends the existing capability of some information assurance methods.

Abstract: According to one embodiment, a system includes a plurality of ring-connected devices. The system includes a first device and a second device. The second device is connected to receive a signal from the first device. When the first device is a data relay station and receives the data containing an error, the first device replaces a part of the data with internally generated data and transmits the resultant data to the second device.

Abstract: Method and a receiver in a communication system for receiving a transport block. The transport block comprises code blocks, each of the code blocks includes an error detection code and an error correction code. Reliability metrics are determined using an input generated during processing of the code blocks after the transport block is received. Each of the reliability metrics corresponds to each of the code blocks. A code block reorderer reorders the code blocks in an order based on the reliability metrics and a selection criterion. A decoder decodes each of the code blocks using the error correction code in the order. A verifier verifies each of the decoded code blocks using the error detection code.

Abstract: A method and apparatus for transmitting a Forward Error Correction (FEC) packet block including a plurality of FEC packets in a multimedia system are provided. The method includes generating a plurality of first FEC packet blocks by performing a first FEC encoding on a plurality of source symbols, each of the plurality of first FEC packet blocks including at least one source packet and at least one repair packet for repair of each of the at least one source packet, generating a second FEC packet block by performing a second FEC encoding on the plurality of first FEC packet blocks, the second FEC packet block including at least one repair packet for the plurality of first FEC packet blocks, and transmitting the second FEC packet block that includes, in header information of each of the at least one source packet and the at least one repair packet.

Abstract: Methods and apparatus are provided for encoding input data for recording in s-level storage of a solid state storage device, where s f 2. Input data words are encoded in groups of M input data words in accordance with first and second BCH codes to produce, for each group, a set of M first codewords of the first BCH code. The set of M first codewords is produced such that at least one predetermined linear combination of the M first codewords produces a second codeword of the second BCH code, this second BCH code being a sub-code of the first BCH code. The sets of M first codewords are then recorded in the s-level storage. If each of the first and second codewords comprises N q-ary symbols where q=pk, k is a positive integer and p is a prime number, the q-ary code alphabet can be matched to the s-ary storage by ensuring that q and s are uth and vth powers respectively of a common base r, where u and v are positive integers and k f u, whereby p(k/u)v=s.

Abstract: A semiconductor memory includes multi-mode reporting signals, a state register, and parity detectors. The parity detector determines whether signals received on a communication bus contain a desired parity. The multi-mode reporting signals enable reporting of communication faults without adding additional signals to the semiconductor memory by being configured in a normal operating mode or a parity fault mode for reporting communication faults to an external memory controller. The state register enables storing of received values from the communication bus. With the state register, a memory controller may determine correctly received signal patterns and failing signal patterns. Parity may be defined as even or odd and may be generated based on various signal configurations. The embodiments may be configured as a computing system comprising a processor, an input device, an output device, the memory controller, and at least one semiconductor memory.

Abstract: Example methods are disclosed for encoding variable sized data using a low-density parity-check (LDPC) code, and transporting the encoded variable sized data in modulated symbols. Example methods involve calculating a minimum number of modulated symbols capable of transmitting a data packet; selecting a codeword size suitable for transmitting the data packet; calculating a number of shortening Nshortened bits; and calculating a number of puncturing Npunctured bits, to thereby produce a shortened and punctured expanded parity check matrix for transmitting the data packet.

Abstract: Different transmissions based on different content blocks which were segmented from the same digital content according to different segmentation schemes, where each of the content blocks has any substring in common with at least one of the other content blocks, are received by a receiving radio communication station, for example a mobile telephone or a mobile network base station. Certain encoded received bits derived from different ones of the transmissions are combined into combined bits. Other encoded received bits derived from one or more of the different transmissions are provided together with the combined bits to a decoder.

Abstract: A method and system of decoding a ccnvolutionally encoded data block having known padding bits. A Viterbi decoder is constrained to a state corresponding to k?1 padding bits immediately adjacent to data bits of the data block, where k is a constraint length of a convolution encoder used to encode the data block. Symbols of the encoded data block that have influence only from the padding bits are discarded.

Abstract: Example methods are disclosed for decoding low-density parity-check (LDPC) encoded data, involving applying an expanded parity check matrix to generate decoded data, wherein ?1 represents an 81×81 all-zero square matrix, and any other integer, Sij, represents an 81×81 identity matrix circularly right shifted by a shift amount equal to Sij.

Abstract: Embodiments of the present disclosure describe methods, apparatus, and system configurations for cyclic redundancy check circuits using Galois-field arithmetic.

Abstract: Provided is an error correction code decoding apparatus capable of performing a decoding process efficiently for various interleaver sizes while suppressing an increase in apparatus size.

Abstract: A data processing device including a controller configured to control the data processing device to execute steps of: receiving a data packet comprising a group identification information that identifies a restoration group, with which the data packet is associated, and redundant data for restoring a lost data packet, which is associated with the restoration group identified by the group identification information; determining whether a received amount of data packet associated with the restoration group identified by the group identification information is equal to or greater than a predetermined value; and restoring the lost data packet associated with the restoration group identified by the group identification information when the received amount of data packet associated with the restoration group identified by the group identification information is equal to or greater than the predetermined value.

Abstract: Techniques for decoding levels in non-volatile memory. A level of a cell in a multi-bit non-volatile memory is read. A minimum of Log-Likelihood Ratio (LLR) and a modified LLR to decode the level, wherein the modified LLR is a function of a misplacement probability is used. A value corresponding the decoded level is written to a volatile memory.

Abstract: Presented is a data channel with selectable components, such as encoders or decoders. Also, data having different data signal characteristics can be processed through a data channel based on the data signal characteristics. Further, a data channel may have independent encoding path and an independent decoding path. For example, a first data transmission having first data signal characteristics may be processed via a data channel based on a first selected set of components of the data channel and a second data transmission having second data signal characteristics different than the first data signal characteristics may be processed via the data channel using a second selected set of components in the data channel. The first selected set of components may be different than the second selected set of components, but may share one or more common components.

Abstract: In one embodiment, device for early stopping in turbo decoding includes a processor configured to receive a block of data to be decoded, compare hard decision bits resulting from decoding iterations and compare a minimum value of log likelihood ratio (LLR) of decoded bits against a threshold. The processor configured to match hard-decisions with previous iteration results. The processor may be configured to set an early stop rule after the matching hard-decisions with previous iteration results is matched. The processor may be configured to set an early stop rule when the minimum reliability of the output bits exceeds the threshold.

Abstract: Methods and apparatus for tail termination are provided that include a decoder that includes a processor configured to a forward state metric and a backward state metric wherein each iteration of an initial state of the backward state metric is fetched from a memory and is pre-computed without feedback from a decoding iteration. Each decoding iteration is substantially identical, and the backward state metric that is pre-computed is used for a subsequent iteration. The decoder may include a turbo decoder or a radix-4 decoder.

Abstract: Various embodiments of the present invention provide systems and methods for stochastic stream decoding of binary LDPC codes. For example, a data decoder circuit is discussed that includes a number of variable nodes and check nodes, with serial connections between the variable nodes and the check nodes. The variable nodes are each operable to perform a real-valued computation of a variable node to check node message for each neighboring check node. The check nodes are operable to perform a real-valued computation of a check node to variable node message for each neighboring variable node. The messages are passed iteratively between the variable nodes and the check nodes.

Abstract: An apparatus, system, and method for generating and decoding a longer linear block codeword using a shorter block length. The method comprises receiving data from a storage area and generating a codeword from the received data with an encoder, the codeword having a data portion and a parity portion, wherein the codeword has a first block length, and wherein the encoder applies a linear block code, the linear block code having a second block length that is shorter than the first block length.

Abstract: There is provided an error correction control method of a transmission system on which a signal is transmitted from a first transmission apparatus to a second transmission apparatus, the error correction control method including: transmitting a signal for a mode change request to change an error correction mode from the second transmission apparatus to the first transmission apparatus; transmitting signals having a change timing value in a specific order with a specific period from the first transmission apparatus to the second transmission apparatus when the first transmission apparatus receives the mode change request; changing the error correction mode of the first transmission apparatus when the change timing value to be transmitted becomes a specific value in the first transmission apparatus; and changing the error correction mode of the second transmission apparatus in response to the change timing value received with the specific period from the first transmission apparatus.

Abstract: A method for decoding an LDPC (low-density parity check) code word. The method includes receiving a plurality of LLR (log likelihood ratio) terms from a demodulation unit of a receiver and generating a scaling factor in accordance with at least one parameter descriptive of communication channel conditions for the receiver. The scaling factor is applied to each of the plurality of LLR terms to compute a corresponding plurality of scaled LLR terms. An iterative layered belief propagation algorithm is then executed by using the plurality of scaled LLR terms to generate decoded information.

Abstract: An error correcting code decoding device includes a first decoding circuit, a word-length reduction circuit configured to reduce bit lengths of a first external values corresponding to a plurality of bits obtained after decoding process performed by the first decoding circuit a first predetermined number of times and to reduce bit lengths of words included in word string, and a second decoding circuit configured to decode the bit string by executing a decoding process a second predetermined number of times for calculating second external values and posterior values of the bits included in the bit string in accordance with the word string including the words having the reduced bit lengths using the first external values having the reduced bit lengths as second prior probabilities that corresponding bits among the plurality of bits are the predetermined value.

Abstract: In one aspect, a communication system transmitter comprises an adaptive error correction encoder. The adaptive error correction encoder is configured to generate a plurality of error correction frames with each such error correction frame comprising a plurality of data packets and one or more error correction packets. A given one of the error correction packets comprises information relating to the plurality of data packets of its corresponding frame and additional information relating to a different one of the error correction frames. For example, the additional information relating to the different one of the error correction frames may be inserted into a header of the given error correction packet, and may comprise a next frame sequence number indicator and a corresponding next frame mask value for a subsequent one of the error correction frames.

Abstract: A memory system includes a memory and a memory controller coupled to the memory. The memory controller includes a data buffer configured to store a full data word as a result of a partial write operation, wherein for a subsequent partial write operation, data is read from the data buffer.

Abstract: The device may include a check bit generator, a memory cell array, an error calculator, and an error corrector. The check bit generator may generate check bits based on input data. The memory cell array may store combined data including the input data and the check bits. The error calculator may be configured to generate syndrome bits based on first data and the check bits received from the memory cell array, calculate an error based on the syndrome bits, and generate error data. The error corrector may be configured to correct the first data based on the error data, and generate second data. The check bits and syndrome bits may include normal check bits, additional check bits, normal syndrome bits, and additional syndrome bits, where the additional check bits are not be normal check bits, and the additional syndrome bits are not normal syndrome bits.

Abstract: In cable modem termination systems (CMTS) and other information transmission systems, a method for changing the interleave depth associated with each data stream is provided. This may be done dynamically, and for any subset of downstream devices such as modems. The interleave depth may be set on an individual device level. Embodiments may decrease data receiving latency on devices that do not suffer from error rates, such as caused by burst noise, while maintaining throughput on devices with high error rates.

Abstract: Embodiments of the invention relate to storing data in a storage array. An aspect of the invention includes receiving write data. The write data is arranged into “r” rows and “n” columns of pages, with each page including a plurality of sectors. The write data is encoded using a plurality of horizontal and vertical erasure correcting codes on the pages. The encoding allows recovery from up to tr erasures in any one of the r rows, up to tr-1 erasures in any one of the remaining r-1 rows, up to tr-2 erasures in any one of the remaining r-2 rows, and so on, such that the encoding allows recovery from up to t1 erasures in the last remaining row. Encoded write data is output from the encoding. The encoded write data is written as a write stripe across n storage devices in a storage array.

Abstract: Various embodiments of the present invention provide systems and methods for generating a code format. One method discussed includes: receiving a first matrix having a row width and a column height that is greater than one; incorporating a circulant into a first column of the first matrix; testing the first column for trapping sets, wherein at least one trapping set is identified; selecting a value to mitigate the identified trapping set; and augmenting the first matrix with a second matrix to yield a composite matrix. The second matrix has the selected value in the first column, and wherein the identified trapping set is mitigated.

Abstract: A 4B5B encoder converts an inputted 4-bit data into a pattern of a 5-bit data in which (i) the number of bits of consecutive “0” data values is permitted to be maximum two, and, simultaneously, (ii) maximum one bit of head end two bits is permitted to have a “0” data value and maximum one bit of tail end two bits is permitted to have a “0” data value. A 5N-bit command encoder converts a command into a command pattern in which the number of bits contained in consecutive “0” data values is permitted to be maximum two. The data after the conversion and the command after the conversion are converted into NRZI codes by an NRZI encoder.

Abstract: A method includes generating first and second data units corresponding to first and second PHY modes, respectively. Generating the first data unit includes FEC encoding first information bits, mapping the FEC-encoded bits to first constellation symbols, and generating first OFDM symbols to include the first constellation symbols. The first OFDM symbols utilize a first tone spacing, and include a first number of non-zero tones collectively spanning a first bandwidth. Generating the second data unit includes FEC encoding second information bits, block encoding the FEC-encoded bits, mapping the block-encoded bits to second constellation symbols, and generating second OFDM symbols to include the second constellation symbols. The second OFDM symbols utilize the first tone spacing, and include a second number of non-zero tones collectively spanning a second bandwidth less than the first bandwidth. The second number of non-zero tones is less than the first number of non-zero tones.

Abstract: A semiconductor device in related art has a problem that security at the time of writing data cannot be sufficiently assured. A semiconductor device of the present invention has: a unique code generating unit generating an initial unique code which is a value unique to a device and includes an error in a random bit; a first error correcting unit correcting an error in the initial unique code to generate an intermediate unique code; a second error correcting unit correcting an error in the intermediate unique code to generate a first determinate unique code; and a decrypting unit decrypting, with the first determinate unique code, transmission data obtained by encrypting confidential information with key information generated on the basis of the intermediate unique code by an external device to generate confidential information.

Abstract: Described embodiments provide for a frame check sequence (FCS) module with a cyclic redundancy check (CRC) unit that receives a data block (padded, if necessary, to a maximum width) and a first state vector and computes an internal vector based on an extended CRC transition matrix. The FCS module further includes a set of matrix units, each matrix unit configured to multiply the internal vector by a corresponding correction matrix wherein the multiplications result in a set of products. A multiplexer selects, by a control signal determined by a maximum number of bytes and the original width, a second state vector from the set of products.

Abstract: Various embodiments of the present invention provide systems and methods for data processing system. As one example, a data processing circuit is described that includes an analog to digital converter, an online timing loop, and an offline timing loop. The analog to digital converter receives an analog input and provides a first series of data samples Each bit of the first series of data samples corresponds to the analog input at a time controlled by an updated sampling clock. The online timing loop modifies the updated sampling clock based at least in part upon a processed version of the first series of data samples.

Abstract: Viterbi decoding may be performed on a microcontroller by initializing a state-metric array by executing load instructions to load state-metric data from a memory module into a set of registers in the microcontroller. Butterfly processing on the state-metric array is performed by executing Viterbi processing instructions fetched from a program storage module to manipulate the state-metric (SM) data in the set of registers for each Viterbi butterfly in a stage of Viterbi decoding to form a final set of state-metric data and trace bits. After completing each stage, a final set of state-metric data may be stored in the memory module by executing store instructions.

Abstract: An iterative PCCC encoder includes a first delay line operative to receive at least one input data sample and to generate a plurality of delayed samples as a function of the input data sample. The encoder further includes a second delay line including a plurality of delay elements connected in a series configuration. An input of a first one of the delay elements is adapted to receive a sum of first and second signals, the first signal generated as a sum of the input data sample and at least one of the delayed samples, and the second signal generated as an output of a single one of the delay elements. A third delay line in the encoder is operative to generate an output data sample as a function of the sum of the first and second signals and a delayed version of the sum of the first and second signals.

Abstract: A method of powerline communications including a first node and at least a second node on a powerline communications (PLC) channel in a PLC network. The first node sends a physical layer (PHY) data frame on the PLC channel including a preamble, a PHY header, a MAC header and a MAC payload. The MAC header includes a Cyclic Redundancy Check (CRC) field (MH-CRC field). The second node receives the data frame, parses the MAC header to reach the MH-CRC field, and performs CRC verification using the MH-CRC field to verify the MAC header. If the CRC verification is successful, (i) the second node parses another portion of the MAC header to identify a destination address of the data frame and (ii) to determine whether the data frame is intended for the second node from the destination address.

Abstract: A co-hosted cyclical redundancy check (CRC) calculations system is arranged to use a processor to generate initial addresses for reading the data from a mirrored device that has address ranges over which a CRC result is to be calculated. An memory mapping unit detects when the initial address falls within an address range over which the CRC result is to be calculated. A read snoop unit snoops the data read from a mirrored memory that has data stored using a mirrored address. A CRC co-generator receives the snooped data read from mirrored memory and uses the snooped data read from the mirrored memory to calculate the CRC result.

Abstract: A communication device includes a turbo encoding section including a plurality of component encoders, wherein the plurality of component encoders within the turbo encoding section use different constraint lengths.

Abstract: A decoding device allowing a high-speed decoding operation. In a decoding section (215), if a degree of a check equation by a check matrix is D and the relationship between the check equation of the j+first row of the check matrix and the cheek equation of the jth row is shifted by n-bit, row processing operation sections (405#1 to 405#3) and column processing operation sections (410#1 to 410#3) perform the operation of a protograph in which the columns of the check matrix are delimited for each “(D+1)×N (N: natural number),” and the rows of the check matrix are delimited for each “(D+1)×N/n,” and formed as the processing unit of the row processing operation and column processing operation.

Abstract: Methods and apparatus are provided for N+1 packet level mesh protection. An error correction encoder is provided for encoding message symbols, m0 through mN?1, to generate a codeword that includes the message symbols, m0 through mN?1, and one or more check symbols. The error correction encoder comprises a linear feedback shift register having one or more flip-flops to generate the check symbols after shifting the message symbols, m0 through mN?1, through the linear feedback shift register. An error correction decoder is also provided for decoding a codeword that includes message symbols, m0 through mN?1, and one or more check symbols. The error correction decoder comprises a linear feedback shift register having one or more flip-flops to generate an error symbol based on a remainder after shifting the message symbols, m0 through mN?1, and the one or more check symbols through the linear feedback shift register.