Abstract: The present invention provides a distributed clustering method to allow multiple active instances of consistency management processes that apply the same encoding scheme to be cooperative and function collectively. The techniques described herein facilitate an efficient method to apply an erasure encoding and decoding scheme across dispersed data stores that receive constant updates. The technique can be applied on many forms of distributed persistent data stores to provide failure resiliency and to maintain data consistency and correctness.

Abstract: There is disclosed apparatus and processes which address problems in the area of providing high availability and disaster recovery for computing systems and the data in them. These apparatus and processes can be used to provide high availability and disaster recovery for a computing system to be protected. The protected computing systems may be virtual computing systems.

Abstract: A memory system according to the present invention includes, in addition to an computing device, a plurality of first blocks that are provided to store information including user information, and first physical addresses not overlapping one another are assigned to, respectively, and a plurality of second blocks that are provided to store first physical addresses of initial defect blocks out of the plurality of first blocks, respectively, wherein the computing device finds the first physical address corresponding a inputted given logical address, based on a given mirror logical address corresponding to the given logical address, and information stored in the second blocks.

Abstract: A program updating system having correction storage units and methods thereof are described. The control unit checks the first setting section of the first storage unit to determine whether the first setting data associated with the second storage unit is stored in the first setting section. When the first setting data is stored in the first setting section, the control unit reads the first setting data and writes the first setting data to the second storage unit. The first setting data includes a first correcting address and a first correcting code corresponding to the first correcting address. The second storage unit stores a first setting data transmitted from the first setting section. The control unit compares an executed address of the original program with the first correcting address. When the executed address is identical to the first correcting address, the control unit replaces a first error code corresponding to the executed address with the first correcting code.

Abstract: Methods and techniques are disclosed for correcting the effect of cycle slips in a coherent communications system. A signal comprising SYNC bursts having a predetermined periodicity and a plurality of known symbols at predetermined locations between successive SYNC bursts is received. The received signal is partitioned into data blocks. Each data block encompasses at least data symbols and a set of check symbols corresponding to the plurality of known symbols at predetermined locations between a respective pair of successive SYNC bursts in the signal. Each data block is processed to detect a cycle slip. When a cycle slip is detected, the set of check symbols of the data block are examined to identify a first slipped check symbol, and a phase correction applied to data symbols of the data block lying between the first slipped check symbol and an end of the data block.

Abstract: A semiconductor device includes a memory module provided with a plurality of memory cells, a verify determination unit that performs quality determination of read data that have been read from the memory cells on the basis of the read data and an expected value prepared in advance, and a power source monitoring circuit that detects fluctuations equal to or greater than a predetermined variation rate in a power source voltage supplied to the memory module and outputs a power source abnormality detection signal. Furthermore, the verify determination unit invalidates a result of the quality determination when the power source abnormality detection signal indicates an abnormal state of the power source voltage.

Abstract: A method for a model checking algorithm is provided. The method includes determining whether a class representative for a state has been processed, and generating a successor state for the state when the class representative for the state has not been processed. The method also includes determining which of a plurality of nodes is assigned to process the successor state, and processing the successor state at a node of the plurality of nodes that is assigned to process the successor state. Additionally another method for checking a model of a system is provided. This method processes a plurality of states for the model with a plurality of nodes using a distributed model checking technique. Each of the plurality of nodes uses symmetry reduction techniques to check if a representative state for a first state has been processed prior to processing the first state.

Abstract: A method and system for writing in flash memory, the system operative for, and the method comprising, writing data onto a plurality of logical pages characterized by a plurality of different probabilities of error respectively, the writing including encoding data intended for each of the plurality of physical pages using a redundancy code with a different code rate for each individual physical page, the code rate corresponding to the probability of error in the individual logical page.

Abstract: Embodiments disclosed herein related to a system used for disaster recovery backup. The system converts the operating system in the system preparing for disaster recovery into a virtualized system which will be disaster-recovery-ready. The system includes: a device to be converted on which a physical operating system is installed; a USB converting device which is coupled to the device to be converted, which includes a USB disc operating system, a converting unit and a virtual system, and which is used to convert the physical operating system in the device to be converted into a virtual system for making backup of the virtual system. Embodiments disclosed herein are further related to a method for disaster recovery backup and a method for installing the disaster recovery system. The disaster recovery system based on the virtualization technology may be deployed rapidly without making any changes to the physical operating system itself.

Abstract: A system for auto-operating backup firmware I disclosed, which includes a baseboard management controller, a first BIOS ROM, a second BIOS ROM, and an inverter. The baseboard management controller has an I/O pin. The first BIOS ROM is electrically connected to the I/O pin of the baseboard management controller. The inverter is electrically connected to the I/O pin, and the second BIOS ROM is electrically connected to the inverter. A method for auto-operating backup firmware is also disclosed.

Abstract: The present invention intends to hold safely string information such as secret information, or the like, and also to lessen user's burden of storing the information in connection to the string information. In registering the secret information, a coding section 16 synthesizes input correct secret information SD and individual characteristic information under a predetermined rule, and produces a code word S16. A check symbol for error correction is produced in the course of the coding of the coding section 16, and this check symbol is stored in a storing section 20. In reproducing the secret information, an error correcting section 22 applies an error correcting process using the check symbol stored in the storing section 20 to a code word, which is produced by the coding section 16 based on the input secret information SD and the individual characteristic information, as the object. Accordingly, the correct secret information is reproduced.

Abstract: A flash memory controller having a configuring unit of error correction code (ECC) capability and method thereof are described. The flash memory controller includes a control unit, a buffer, an ECC module, and a configuring unit. The flash memory has a data area for storing the data content and a first spare area for storing a first ECC value corresponding to the data content. The ECC module utilizes the data content for generating a second ECC value and comparing the second ECC value with the first ECC value to determine whether the data content comprises a plurality of errors based on the compared result of the first ECC value and the second ECC value. The configuring unit computes the amount of the errors if the data content has the errors to determine whether the amount of the errors exceeds a predetermined threshold.

Abstract: A link table recovery method for a flash memory having a plurality of blocks is provided. The method includes: selecting one block from the blocks; selecting a last page containing data of the selected block; checking the last page to determine whether the last page has errors; moving the correct data in the selected block to one of the spare blocks when the last page of the selected block detects errors; and updating a link table of the flash memory.

Abstract: A technique for selecting an erasure code from a plurality of erasure codes for use in a fault tolerant system comprises generating a preferred set of erasure codes based on characteristics of the codes' corresponding Tanner graphs. The fault tolerances of the preferred codes are compared based at least on the Tanner graphs. A more fault tolerant code is selected based on the comparison.

Abstract: A technique is provided for determining an allocation of the symbols of an erasure code across a plurality of devices. A list of erasure patterns is provided for the erasure code and, based on the list, minimal erasures of minimal weight are identified for the code's symbols. Precedences of the symbols are determined based on the size of the corresponding MEMW. An allocation of the symbols across a plurality of devices is determined based on the precedences.

Abstract: Provided are data processing methods for a non-volatile memory. The data processing methods include obtaining read data and erasure information from the non-volatile memory and correcting an error in the read data by referencing the erasure information obtained from the non-volatile memory. Memory systems may be provided. Such memory systems may include a non-volatile memory and a memory controller that is operable to perform an error correction operation according to the methods described herein.

Abstract: True bit level decoding of TTCM (Turbo Trellis Coded Modulation) of variable rates and signal constellations. A decoding approach is presented that allows for decoding on a bit level basis that allows for discrimination of the individual bits of a symbol. Whereas prior art approaches typically perform decoding on a symbol level basis, this decoding approach allows for an improved approach in which the hard decisions/best estimates may be made individually for each of the individual bits of an information symbol. In addition, the decoding approach allows for a reduction in the total number of calculations that need to be performed as well as the total number of values that need to be stored during the iterative decoding. The bit level decoding approach is also able to decode a signal whose code rate and/or signal constellation type (and mapping) may vary on a symbol by symbol basis.

Abstract: An audio data interpolating device includes: a reception module configured to receive content data; an extraction module configured to extract first audio data and second audio data corresponding to the first audio data from the content data; an interpolation data detection module configured to detect error data in the first audio data and detect interpolation data corresponding to the error data from the second audio data; and an output module configured to output the first audio data and output the interpolation data in place of the error data included in the first audio data.

Abstract: A data processing method for loading data from a non volatile memory to a memory is disclosed. A template data and a data block corresponding thereto in the non volatile memory are loaded to a buffer. A reference value of the template data and a corresponding reference value of the data block are compared to determine whether the reference value and the corresponding reference value are matched. If not, a modification algorithm is performed to adjust the data format of the loaded data block based on the reference value of the template data. Then, system related information is generated and stored to the memory according to data in the template data and the adjusted data block in the buffer.

Abstract: A stored data processing apparatus includes: a format controller that adds an error correction code to data written onto a disk medium for each first block; a redundant data generation section that performs calculation for each bit position using data of all the first blocks in a second block and outputs a result of the calculation as calculation data, the second block being constituted by a plurality of the first blocks each including the error correction code added by the format controller and specified as an update target; and an MPU that writes the calculation data output from the redundant data generation section in a third block associated with the second block as the update target.

Abstract: Disclosed herein is a coding apparatus handling quasi-cyclic codes in which a given code word cyclically shifted by p symbols provides another code word, wherein parallel processing is executed in units of mp (a multiple of p) symbols; mp generator polynomials are used; and the generator polynomials gj(x) are selected such that a coefficient of degree deg(gi(x)) of x becomes zero for all gi(x) lower in degree than that and circuits in which these generator polynomials gj(x) are combined are connected with each other.

Abstract: In one embodiment, a turbo equalizer has a channel detector that receives equalized samples and generates channel soft-output values. An LDPC decoder attempts to decode the channel soft-output values to recover an LDPC-encoded codeword. If the decoder converges on a trapping set, then an adjustment block selects one or more of the equalized samples based on one or more specified conditions and adjusts the selected equalized samples. Selection may be performed by identifying the locations of unsatisfied check nodes of the last local decoder iteration and selecting the equalized samples that correspond to bit nodes of the LDPC-encoded codeword that are connected to the unsatisfied check nodes. Adjustment of the equalized samples may be performed using any combination of scaling, offsetting, and saturation. Channel detection is then performed using the adjusted equalized samples to generate an updated set of channel soft-output values, which are subsequently decoded by the decoder.

Abstract: The disclosed subject matter provides low power layered LDPC decoders and related systems and methods. Exemplary embodiments of the disclosed subject matter can achieve significant reduction in memory access of the associated memories by bypassing the associated memories depending on the decoding algorithm (e.g., code rate) and the characteristic of the LDPC parity check matrix, thereby providing significant reductions power consumption of LDPC decoders. According to various embodiment, an optimal decoding order can be determined and scheduled to maximize the power reduction available by bypassing the associated memories. In addition, various algorithms are disclosed that determine optimal search orders under various constraints. According to the disclosed subject matter, particular embodiments can further reduce power consumption by employing the disclosed thresholding to further reduce memory access.

Abstract: The present invention discloses a candidate list augmentation apparatus with dynamic compensation in the coded MIMO systems. The proposed path augmentation technique in the present invention can expand the candidate paths derived from the detector to a distinct and larger list before computing the soft value of each bit. Consequently, the detector is allowed to deliver a smaller list, leading to reduction in computation complexity. Moreover, an additive correction term is introduced to dynamically compensate the approximation inaccuracy in the soft value generation, which improves the efficiency and performance of the coded MIMO systems.

Abstract: A method is provided which defends a computer program against attacks independently of the complexity of the program. A request to invoke the application is received. A process execution state is set to indicate a first execution. The application is executed in response to the request, and application data and control information calculated by the application is stored while the application is executed. The process execution state is set to indicate a subsequent execution. At least part of the application is executed for at least one subsequent time. Application data and control information calculated by the application during subsequent executions is compared with the data/information stored during first execution. The comparison is done by operation system services which are responsive to the process execution state. When the comparison shows a discrepancy in the compared application data and control information, appropriate error handling takes place.

Abstract: The invention teaches a media container file comprising media data organized into media source blocks. Forward error correction (FEC) redundancy data is pre-calculated for the different source blocks and organized into the container file as different FEC reservoirs. The container file also comprises meta data providing an association between the media source blocks and the respective FEC reservoirs. The container file can be employed by a media server in a media session for compiling media data packets to be transmitted to requesting clients without the need of extensive data processing and FEC calculation.

Abstract: The present invention is related to the checking of encryption. Embodiments of the present invention are based on the discovery that sufficiently high reliability may be established without checking every encryption block. Instead, embodiments of the present invention provide that data being encrypted may be sampled at certain rate (which may be constant or varying) and only the sampled data may be checked. In general, embodiments of the present inventions are applicable to a fast encryption circuit that may encrypt an entire stream of incoming data into a stream of encrypted data and one or more slower (or slow) encryption circuit and/or one or more slow decryption circuit that operate(s) only on selected samples of the incoming or encrypted data in order to check the encryption of the fast circuit. Thus, encryption can be verified without incurring the costs of exhaustively checking all encrypted data.

Abstract: An apparatus accepts an injustice (grievance) report containing injustice report source terminal information for identifying a terminal device transmitting the injustice report and injustice content holding terminal information identifying a terminal device holding the content altered from the original content and content identification information for identifying the content; accesses a correspondence relation recording unit recording, in association with content identification information identifying the content, notification destination terminal information identifying a terminal device to which the content holding terminal information is notified, and content holding terminal information notified to the notified terminal device; determines that the injustice report accepted by the injustice report accepting is false and discards the false injustice report, when the injustice report source terminal information contained in the injustice report is not coincident with the notification destination terminal in

Abstract: A method, apparatus, and system of improved handling of clustered media errors in raid environment are disclosed. In one embodiment, a method includes starting a command timer when a firmware accepts a command from a host, tracking an amount of time the command spends on handling of a clustered media error through the command timer, and stopping the command timer when at least one of the command is completed and a time limit expires. The method may complete a read as a success when a host IO is a read command. The method may complete a write as a success, after writing parity, and data when the host IO may be a write command.

Abstract: Methods, apparatus, and products are disclosed for error recovery during execution of an application on a parallel computer that includes a plurality of compute nodes. Such error recovery includes: storing, by the application during execution on the nodes, application restore data in a restore buffer at predetermined points during execution of the application, the restore data specifying an execution state of the application at one or more points during application execution; encountering, by at least one of the nodes executing the application, a recoverable error during application execution; determining, by the application, the nodes affected by the recoverable error; restarting, by each of the affected nodes, execution of the application; retrieving, by the restarted application executing on each of the affected nodes, the restore data from the restore buffer; and continuing, by each affected node, execution of the application with the execution state specified by the retrieved restore data.

Abstract: The system and method are for efficient detection and restoration of data storage array defects. The system may include a data storage subsystem, wherein the data storage subsystem includes a data storage array, read-write logic coupled to the data storage array, a parity generator for producing and storing check data during write operations to the data storage array and generating check data during read operations on the data storage array, and a parity checker for verifying the stored check data with generated check data and identifying defective data read-write elements during read operations on the data storage array. The subsystem may further include a Built-in Self Test (BIST) generator operating only on the identified defective data read-write elements for determining defective data storage elements in the defective data read-write elements, and a restoration mechanism for restoring the valid operation of data access elements containing the defective data storage elements in the data storage array.

Abstract: A method of supporting a hybrid automatic retransmission request (HARQ) in an orthogonal frequency division multiplexing access (OFDMA) radio access system is disclosed. Preferably, the method comprises receiving a downlink data frame comprising a data map information element and a data burst comprising a plurality of layers, wherein each layer is encoded with a corresponding channel encoder, and wherein the data map information element is configured to support multiple antennas to achieve space time transmit diversity by providing control information associated with each one of the plurality of layers, wherein the control information comprises allocation of acknowledgement status channels corresponding to the plurality of layers, and transmitting in an uplink data frame a plurality of acknowledgement status, each acknowledgement status being associated with whether a corresponding layer of the plurality of layers is properly decoded.

Abstract: A search key lookup system including a hash table having a plurality of entries and a function generator is disclosed. The function generator can be coupled to the hash table and configured to receive a key and to provide a first function and a second function. The first function can be a Cyclic Redundancy Code (CRC) type function and the second function can be an Error Checking and Correcting (ECC) type function. Further, an address of the table can include a concatenation of the results of the CRC and the ECC type functions.

Abstract: Methods and corresponding systems in a Viterbi decoder include selecting an input symbol in an input block, wherein the input block has a plurality of input symbols, wherein each input symbol has a Boolean value, a quality value, and an associated stage, and wherein the selected symbol is selected based upon the quality value of the selected symbol relative to a quality value of other input symbols in the input block. Thereafter, the Boolean value of the selected symbol is complemented to produce a complemented symbol. The complemented symbol is substituted for the selected symbol to produce an alternate input block. A Viterbi algorithm is executed using the alternate input block to produce an alternate decoded bit sequence, which is then checked for errors using an error check. The alternate decoded bit sequence is output in response to the alternate decoded bit sequence passing the error check.

Abstract: Methods and structure described herein provide for reducing the overall delay of an RS encoder/decoder without changing the essential functionality of the RS encoder/decoder. In one embodiment, a cascade module reduces the combinatorial logical delay by reducing the total number of logical devices. In doing so, the cascade module couples encoder/decoder slices into blocks. A first block of the encoder/decoder slices is selectively operable in parallel with a second block of encoder/decoder slices. The number of encoder/decoder blocks is less than the overall number of encoder/decoder slices. The cascade module may also include a switch that selects encoder/decoder slices as needed, thereby providing for the implementation of the RS encoder/decoder with fewer logical devices.

Abstract: A circuit is presented for determining whether or not to invert a bus, for example a data bus that is operable having multiple widths. The circuit includes comparison circuitry that can receive both the current and next values for the bus and individually compare the current and next values of the bits on the bus to determine whether these have changed. A voting circuit receives the result of these determinations and also receives an indication of width with which the bus is being operated. The voting circuit then determines a bus inversion values based upon whether the number of bits on the data that have changed exceed a value that depends upon the indication of bus width.

Abstract: A decoding method performs turbo decoding on data that includes a first value before transmission and that includes a second value after received, the second value changed from the first value due to the influence of a transmission path. The decoding method includes performing the turbo decoding on the data to obtain a log-likelihood ratio for the second value, converting the second value to a third value that is obtained by correcting the second value to become closer to the first value when a decoded result from the turbo decoding on the data includes an error and when an absolute value of the log-likelihood ratio is equal to or greater than a predetermined threshold value; and performing the turbo decoding on the data including the third value to obtain a decoded result of the data.

Abstract: Methods and apparatus are provided for performing SOVA detection at higher data rates than achievable with conventional designs. A received signal is processed by (i) determining at least three selection signals that define a plurality of paths through a multiple-step trellis into a given state, wherein a first of the plurality of paths is a winning path for each single-step-trellis period of a multiple-step-trellis cycle, a second path is a winning path for a first single-step-trellis period and is a losing path for a second single-step-trellis period of a multiple-step-trellis cycle and a third path is a losing path for a first single-step-trellis period and is a winning path for a second single-step-trellis period of a multiple-step-trellis cycle; and (ii) determining at least one reliability value (such as a reliability value for a bit decision associated with a maximum-likelihood path through the multiple-step trellis or a plurality of reliability values for each multiple-step-trellis cycle).

Abstract: A method of controlling interference between communication terminals involves sending a notification of a desire to transmit a transmission over a wireless network from a first terminal; determining whether any terminal in the process of receiving has sent an objection in response to the notification; sending the transmission if no objection is received, and modifying the transmission if an objection is received.

Abstract: A method for controlling input and output of a virtualized computing platform is disclosed. The method can include creating a device interface definition, assigning an identifier to a paging device and configuring commands useable by a virtual input output server. The commands can be sent to the input output server and can be converted by the input output server into paging device commands. A hypervisor can assist in facilitating the communication configuration. Other embodiments are also disclosed.

Abstract: A transmission apparatus receives information used to identify data unsuccessfully received by a reception apparatus. Then, the transmission apparatus determines whether the data corresponding to the received identification information should be retransmitted based on whether the reception apparatus has a function of displaying the display area of the data corresponding to the identification information by using data having the display area corresponding to the data corresponding to the identification information.

Abstract: According to one embodiment, an electronic apparatus includes a timing detection module which detects a timing of notification to a user in association with execution of an application, a photographing module which captures an image at the timing of notification, which is detected by the timing detection module, a face image detection module which detects a face image of a person from the image which is captured by the photographing module, a direction detection module which detects a direction of the face on the basis of the face image, a setting module which sets a notification method in accordance with the direction of the face, which is detected by the direction detection module, and a notification module which gives a notice according to the notification method which is set by the setting module.

Abstract: An integrated circuit (2) includes a signal source (4, 6) and a signal destination (10, 12) linked by a signal path (8). Error correction codes (e.g. Hamming codes) are applied to the signals to be transmitted. Errors detected in the signal transmission are used to control an operating parameter of the signal path, such as signal voltage level, body bias voltage, clock frequency and/or temperature. The control applied is closed-loop feedback control seeking to maintain a finite non-zero predetermined error rate. The technique can also be used between a memory accessing integrated circuit (54) and a separate memory integrated circuit (56). Furthermore, the technique can be used to provide fixed, but differing operating parameters for signal lines within a signal path.

Abstract: A method includes determining a length of a file and storing the length of the file in a first memory location. An endpoint of a last complete record within the file is determined and the endpoint is stored in a second memory location. The length of the file stored in the first memory location is compared to a current length of the file, and a data structure associated with the file is updated beginning at the endpoint if the current length of the file exceeds the length of the file stored in the first memory location.

Abstract: Systems and methods for providing relay in communications systems are disclosed. The relay may receive signals from user equipments (UEs) transmitting coded signals. The relay may receive turbo coded signals from the UEs. The relay station may encode a network channel for transmission to the base station using a recursive systematic convolutional (“RSC”) code. The use of RSC for the network code enables the base station to form as well a distributed turbo code as one can with the UE coded signals. In this manner the base station may recover the signal estimates for the UE signals with lower error probability when estimates at the relay station include errors due to imperfect reception. The use of the relay station and the RSC network code enables the base station to receive UE signals with lower error probability even when the transmission path from the UE is imperfect.

Abstract: The present invention relates to a receiver device and method of detecting a block length of a data block in a data network, wherein a respective theoretical maximum value for a metric of a decoding operation is calculated for each of a plurality of candidate block lengths, and the calculated respective theoretical maximum value is compared to a respective actual value of the metric obtained for each of the plurality of candidate block lengths by the decoding operation. The candidate block length with the highest ratio between the respective actual value and the respective theoretical maximum value is then selected from the plurality of candidate block lengths to determine the block length of the data block.

Abstract: A device for soft decoding contains a set of operational elements, each being capable of performing one of several different functions. The operational elements may be dynamically configured with input and output connections to registers, memory locations, and other operational elements to perform various steps in a soft decoding scheme. In many cases, the operational elements may be configured to operate in a pipeline mode where many sequences of operations may be performed in parallel. Some embodiments may be reconfigured at each clock cycle to perform different steps during a decoding operation. The device may be used to perform several different soft decoding schemes with the flexibility of a programmable processor but the throughput of a hardware implementation.

Abstract: A programmable signal processing circuit has an instruction processing circuit (23, 24, 26), with an instruction set that comprises a depuncture instruction. The instruction processing circuit (23, 24, 26) forms the depuncture result by copying bit metrics from a bit metrics operand and inserting one or more predetermined bit metric values between the bit metrics from the bit metric operand in the depuncture result. The instruction processing circuit (23, 24, 26) changes the relative locations of the copied bit metrics with respect to each other in the depuncture result as compared to the relative locations of the copied bit metrics with respect to each other in the bit metric operand, to an extent needed for accommodating the inserted predetermined bit metric value or values.

Abstract: A method for data protection includes, in a first operational mode, sending data items for storage in a primary storage device and in a secondary storage device, while temporarily caching the data items in a disaster-proof storage unit and subsequently deleting the data items from the disaster-proof storage unit, wherein each data item is deleted from the disaster-proof storage unit upon successful storage of the data item in the secondary storage device. An indication of a fault related to storage of the data in the secondary storage device is received. Responsively to the indication, operation is switched to a second operational mode in which the data items are sent for storage at least in the primary storage device and are cached and retained in the disaster-proof storage unit irrespective of the successful storage of the data items in the secondary storage device.

Abstract: A receiver is provided that comprises a decoder. The decoder comprises: means for slicing a signal; means for encoding data/messages to a code word among a predetermined number of code words; and means for determining a distance associated with the code word.