Error Detection Or Correction By Redundancy In Data Representation, E.g., By Using Checking Codes, Etc. (epo) Patents (Class 714/E11.03)

  • Publication number: 20090276683
    Abstract: A transmitter communicates with a receiver and an error corrector corrects bit errors generated during data transmission. The transmitter has a scrambler unit that scrambles data so that a running disparity of 0 and 1 in the input data is substantially zero. A bit-string converting unit 15 that adds bit data for ensuring a maximum run length of a serial bit string of the scrambled data and converts control information to bit data of a fixed value. A synchronization timing generating unit 16 divides the transmitted data by a constant interval and converts the transmission data to a data block. A bit-string converting unit extracts a fixed-value bit pattern of the control data from the bit string of the data block, converts the bit pattern to the control information, and discriminates the data and the control information. A descrambler unit reconverts the data-scrambled data to the data before scrambling.
    Type: Application
    Filed: November 17, 2006
    Publication date: November 5, 2009
    Applicant: ALAXALA NETWORKS CORPORATION
    Inventors: Hidehiro Toyoda, Takayuki Muranaka, Takeshi Matsumoto, Naohisa Koie
  • Publication number: 20090276677
    Abstract: A radio communications device includes a first error detection part configured to perform error detection on a header included in a packet; a determination part configured to determine whether there is consistency with respect to the length of the packet based on the header in response to the first error detection part detecting no error in the header; a decryption part configured to decrypt the packet in response to the determination part determining that there is consistency with respect to the length of the packet; and a second error detection part configured to perform error detection on the packet in response to the determination part determining that there is consistency with respect to the length of the packet, wherein the decryption part is configured to start to decrypt the packet before completion of the error detection by the second error detection part.
    Type: Application
    Filed: March 19, 2009
    Publication date: November 5, 2009
    Applicant: FUJITSU LIMITED
    Inventors: Miyoshi Saito, Koichi Suzuki
  • Publication number: 20090276670
    Abstract: A reception apparatus that receives a signal, including, a correction section, an error detection section, a filtering section, and a setting section is provided.
    Type: Application
    Filed: April 15, 2009
    Publication date: November 5, 2009
    Applicant: SONY CORPORATION
    Inventors: Ryo Hasegawa, Katsumi Takaoka
  • Publication number: 20090271656
    Abstract: Provided are a stream distribution system and a failure detection method capable of easily identifying the cause of quality loss in stream distribution. This stream distribution system includes a first server for communicating with a client terminal via a router and sending stream data, and a second server configured as a redundant server of the first server and connected to the first server. The first server has a communication status notification unit for sending a connection management table concerning the communication with the client terminal to the second server. The second server has a packet recording unit for acquiring a mirror packet, which is a copy of a packet sent to the first server, from the router, and a network failure monitoring unit for detecting a failure in a network between the first server and the client terminal based on the connection management table and a packet buffer.
    Type: Application
    Filed: June 17, 2008
    Publication date: October 29, 2009
    Inventors: Daisuke YOKOTA, Aritoki Takada, Tadashi Takeuchi, Yoshihiro Hayashi
  • Publication number: 20090271660
    Abstract: A motherboard, a method for recovering a BIOS thereof, and a method for booting a computer are provided. In the method for booting the computer, a first boot block of a first BIOS unit is executed first, and then a second boot block of a second BIOS unit is executed. Afterwards, BIOS main program codes of the second BIOS unit are executed. When the second BIOS unit is down, a recovery mechanism of the first boot block is used to overwrite data in the second BIOS unit with a backup file.
    Type: Application
    Filed: December 12, 2008
    Publication date: October 29, 2009
    Applicant: ASUSTEK COMPUTER INC.
    Inventors: Chung-Ta Chin, Shu-Jen Lin, Pei-Hua Sun, Ren-Shiang Tsai
  • Publication number: 20090265601
    Abstract: Methods are disclosed for improving communications on feedback transmission channels, in which there is a possibility of bit errors. The basic solutions to counter those errors are: proper design of the CSI vector quantizer indexing (i.e., the bit representation of centroid indices) in order to minimize impact of index errors, use of error detection techniques to expurgate the erroneous indices and use of other methods to recover correct indices.
    Type: Application
    Filed: April 21, 2008
    Publication date: October 22, 2009
    Applicant: TR TECHNOLOGIES INC.
    Inventors: Bartosz Mielczarek, Witold A. Krzymien
  • Publication number: 20090259916
    Abstract: Data accessing method for a flash memory, and a controller and a storage system using the same are provided. The data accessing method includes reading data from a physical address of a flash memory according to a physical address to be read corresponding to a logical address to be read in a read command, and determining whether or not the read physical address is the physical address to be read. The data accessing method also includes transmitting the data only if the read physical address is the physical address to be read. Accordingly, it is possible to ensure the transmitted data is data to be accessed by the read command.
    Type: Application
    Filed: June 30, 2008
    Publication date: October 15, 2009
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Chih-Jen Hsu, Yi-Hsiang Huang
  • Publication number: 20090259925
    Abstract: A method for transmitting data between components of a digital broadcasting system includes: receiving payload data, adding a content layer header to the payload data to form a content layer data frame, adding a transmission and authentication layer header and a cyclic redundancy check field to the content layer data frame to form a transmission and authentication layer data frame, adding an application framing layer header to the transmission and authentication layer data frame to form an application framing layer data frame, and transmitting the application framing layer data frame to a destination component.
    Type: Application
    Filed: April 10, 2008
    Publication date: October 15, 2009
    Applicant: iBiquity Digital Corporation
    Inventors: Muthu Gopal Balasubramanian, Rodney Burke, Russell Iannuzzelli, Steven Andrew Johnson, Stephen Douglas Mattson
  • Publication number: 20090249132
    Abstract: According to one embodiment, an information processing apparatus includes a plurality of execution modules, a system memory shared by the plurality or execution modules, and a scheduler which controls assignment of a plurality of basic modules to the plurality of execution modules in order to execute a program in parallel by the plurality of execution modules. The scheduler saves data items, which is to be input by the execution modules as input data items of the basic modules and is stored in the storage areas of the system memory, in other storage areas of the system memory before the basic modules are executed, and compares the data items stored in the storage areas of the system memory and accessed by the execution modules with the data items saved in the other storage areas of the system memory after the basic modules have been executed.
    Type: Application
    Filed: March 3, 2009
    Publication date: October 1, 2009
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Ryuji Sakai
  • Publication number: 20090249148
    Abstract: Improved apparatus, systems and methods, such as those for testing an error correction code (ECC) encoder/decoder for solid-state memory devices, are provided. In one or more embodiments, the improved systems and methods deliberately inject errors into memory storage areas of memory devices to test the operation of the ECC encoder/decoder.
    Type: Application
    Filed: March 25, 2008
    Publication date: October 1, 2009
    Applicant: Micorn Technology, Inc.
    Inventors: Yutaka Ito, Adrian Drexler, Brandi Jones
  • Publication number: 20090235146
    Abstract: Various embodiments of the present invention provide systems and methods for data regeneration. For example, a system for data regeneration is disclosed that includes a data input derived from the medium. A data detector and a data recovery system receive the data input. The data detector provides a first soft output, and the data recovery system provides a second soft output. The first soft output and the second soft output are provided to a multiplexer. A media defect detector performs a media defect detection process, and provides a defect flag that indicates whether the data input is derived form a defective portion of the medium. The defect flag is provided to the multiplexer where it is used to select whether the first soft output or the second soft output is provides as an extrinsic output.
    Type: Application
    Filed: April 29, 2008
    Publication date: September 17, 2009
    Applicant: Agere Systems Inc.
    Inventors: Weijun Tan, Shaohua Yang, George Mathew, Kelly Fitzpatrick, Hao Zhong, Yuan Xing Lee
  • Publication number: 20090228756
    Abstract: An iterative decoder circuit includes an N number of sub-decoders, N?1 of the sub-decoders each being responsive to a baseband signal from one of M number of signal processing circuits. Each of the N?1 number of sub-decoders includes, an inner delay responsive to a baseband signal provided by a corresponding signal processing circuit for generating an inner delayed signal, a modified decoder that receives the inner delayed signal and generates a set partition signal, some of which have less errors than previous set partition signals. An Nth inner delay is responsive to the baseband signal and provides an Nth inner delayed signal. An Nth modified decoder is responsive to the Nth inner delayed signal and to the set partition signal and provides an output signal, wherein the probability of error of the output signal is reduced by correcting errors in some of the set partition signals.
    Type: Application
    Filed: March 6, 2008
    Publication date: September 10, 2009
    Applicant: AUVITEK INTERNATIONAL LTD.
    Inventors: Jordan Christopher COOKMAN, Ping DONG, Tao YU
  • Publication number: 20090222690
    Abstract: A system and method for automatic disaster recovery of a computing appliance including reconstruction of its previous operational state. A configuration bundle that includes configuration data, software revision level and a list of system updates is used to recover the device's operation state. The system and method can also be utilized to recover a not fully functional member of a clustered computing system from the configuration information stored on other members of the cluster.
    Type: Application
    Filed: November 25, 2008
    Publication date: September 3, 2009
    Applicant: Secure Computing Corporation
    Inventors: David Seelig, Stephen Czeck
  • Publication number: 20090217124
    Abstract: Data bits to be encoded are split into a plurality of subgroups. Each subgroup is encoded separately to generate a corresponding codeword. Selected subsets are removed from the corresponding codewords, leaving behind shortened codewords, and are many-to-one transformed to condensed bits. The final codeword is a combination of the shortened codewords and the condensed bits. A representation of the final codeword is decoded by being partitioned to a selected subset and a plurality of remaining subsets. Each remaining subset is decoded separately. A subset whose decoding is terminated is decoded again, at least in part according to the selected subset. If the encoding and decoding are systematic then the selected subsets are of parity bits.
    Type: Application
    Filed: February 21, 2008
    Publication date: August 27, 2009
    Applicant: RAMOT AT TEL-AVIV UNIVERSITY LTD.
    Inventors: Simon Litsyn, Eran Sharon, Idan Alrod, Menahem Lasser
  • Publication number: 20090217085
    Abstract: An embodiment relates generally to a method of restoring data in storage systems. The method includes providing for a current snapshot of a primary storage system at a secondary storage system and mounting an empty volume in the primary storage system. The method also includes receiving a request for a selected block of data in the primary storage system and retrieving a restore block from the secondary storage system, where the restore block encompasses the selected block of data. The method further includes writing the restore block to the empty volume in the primary storage system as an incremental restore process.
    Type: Application
    Filed: February 27, 2008
    Publication date: August 27, 2009
    Inventors: Henri H. Van Riel, Herman Robert Kenna
  • Publication number: 20090213923
    Abstract: The invention proposes a method for joint detection and channel decoding of binary data employing a trellis-based detector where the trellis describes RLL encoding, NRZI preceding, the influence of the channel, and PR equalization. In order to improve performance for the case of exchanging soft information with an outer soft-in soft-out channel decoder or ECC decoder under the presence of correlated noise, the trellis is extended to also comprise and model a Noise Prediction.
    Type: Application
    Filed: February 20, 2009
    Publication date: August 27, 2009
    Inventors: Xiao-Ming Chen, Oliver Theis
  • Publication number: 20090217142
    Abstract: Rate control adaptable communications. A common trellis is employed at both ends of a communication system (in an encoder and decoder) to code and decode data at different rates. The encoding employs a single encoder whose output bits may be selectively punctured to support multiple modulations (constellations and mappings) according to a rate control sequence. A single decoder is operable to decode each of the various rates at which the data is encoded by the encoder. The rate control sequence may include a number of rate controls arranged in a period that is repeated during encoding and decoding. Either one or both of the encoder and decoder may adaptively select a new rate control sequence based on a variety of operational parameters including operating conditions of the communication system, a change in signal to noise ratio (SNR), etc.
    Type: Application
    Filed: May 9, 2009
    Publication date: August 27, 2009
    Applicant: BROADCOM CORPORATION
    Inventors: Kelly Brian Cameron, Ba-Zhong Shen, Hau Thien Tran
  • Publication number: 20090210744
    Abstract: A method and system of method and system of enhanced RAID level 3 is disclosed. In one embodiment, a method includes allocating three times a physical storage capacity of a data drive to a dedicated parity drive of a ‘n’ physical drives of a redundant array of independent disks, recovering n?1 physical drive failures of the ‘n’ physical drives through a parity-in-parity technique in which certain number of parities generated during an initial write of data may be physically stored and using an XOR function applied to the stored parities to recreate un-stored parities which enable recovery of the n?1 physical drive failures. The method may include creating a superior read/write access capability and/or a superior parity data redundancy through the mirroring. The method may also include recreating the un-stored parities after a time interval that may be specified by a user.
    Type: Application
    Filed: February 19, 2008
    Publication date: August 20, 2009
    Inventor: HARIHARAN KAMALAVANNAN
  • Publication number: 20090199062
    Abstract: Virtual limited buffer modification for rate matching. A reduced-size memory module is employed within a communication device to assist in storage of log-likelihood ratios (LLRs) employed in accordance with turbo decoding. This architecture is also applicable to other types of error correction code (ECC) besides turbo code as well. The memory size is selected to match the number of coded bits (e.g., including information bits and redundancy/parity bits) that is included within a transmission. The received signals may be various transmissions made in accordance with hybrid automatic repeat request (HARQ) transmissions. When the LLRs calculated from a first HARQ transmission is insufficient to decode, those LLRs are selectively stored in the memory module. When LLRs corresponding to a second HARQ transmission is received, LLRs corresponding to both the first HARQ transmission and the second HARQ transmission are passed from the memory module for joint use in decoding.
    Type: Application
    Filed: January 30, 2009
    Publication date: August 6, 2009
    Applicant: BROADCOM CORPORATION
    Inventors: Ba-Zhong Shen, Sirikiat Lek Ariyavisitakul, Tak K. Lee
  • Publication number: 20090199048
    Abstract: A non-volatile memory device comprises an application code sector of sufficient size to store a first copy of an application code and a second copy of the application code; and a boot sector having a boot loader code embodied therein. The boot loader code is configured to cause a processor to check the integrity of both the first and second copies of the application code; if the first copy is corrupted, overwrite the first copy of the application code with the second copy; and if the second copy is corrupted, overwrite the second copy of the application code with the first copy.
    Type: Application
    Filed: February 4, 2008
    Publication date: August 6, 2009
    Applicant: HONEYWELL INTERNATIONAL INC.
    Inventors: Yogesha Aralakuppe Ramegowda, Srinivasa R. Dangeti, Puja Chopra, Narasimha Rao Pesala, Puri Gautam, Shruti Kop, Darshan Raj, Mani Sivaraman, Yugandhar Kumar Puppala, Kaarthikeyan Muthusamy, Sachin Jethe, Mugdalbetta Rajesh Suresh
  • Publication number: 20090187797
    Abstract: Full text index-ability, indexing, and container extraction status of files in a collection repository is displayed to a user in connection with content management in EDiscovery. Thus, the user knows which files failed to index and explode and which files that are not indexable. The user also knows which files have not been indexed yet, so they are not omitted from an analysis. Accordingly, users can start working on collected files without waiting for the maximum possible indexing period. Further, users can start working immediately on the collected content, thus avoiding slowing down the work during frequent updates to the content repository. Only indexing and extraction status information that is relevant to the search query is displayed, thus minimizing the time needed to analyze the files that are not indexed or not exploded manually.
    Type: Application
    Filed: January 21, 2008
    Publication date: July 23, 2009
    Inventors: Pierre RAYNAUD-RICHARD, Andrey POGODIN
  • Publication number: 20090182953
    Abstract: This is invention comprises a method and apparatus for Infinite Network Packet Capture System (INPCS). The INPCS is a high performance data capture recorder capable of capturing and archiving all network traffic present on a single network or multiple networks. This device can be attached to Ethernet networks via copper or SX fiber via either a SPAN port (101) router configuration or via an optical splitter (102). By this method, multiple sources or network traffic including gigabit Ethernet switches (102) may provide parallelized data feeds to the capture appliance (104), effectively increasing collective data capture capacity. Multiple captured streams are merged into a consolidated time indexed capture stream to support asymmetrically routed network traffic as well as other merged streams for external consumption.
    Type: Application
    Filed: April 1, 2009
    Publication date: July 16, 2009
    Applicant: SOLERA NETWORKS. INC.
    Inventors: JEFFREY V. MERKEY, BRYAN W. SPARKS
  • Publication number: 20090183056
    Abstract: Objects stored in a storage system (such as a file server system) are protected by multiple levels of validation. Each chunk of an object is associated with a chunk validator, and an object validator is computed for the object based on the chunk validators. The object validator is stored in the storage system and may be used at various times to validate the object, for example, upon a startup of the storage system, upon taking a checkpoint or “snapshot” of the status of the storage system, or at other appropriate times.
    Type: Application
    Filed: January 16, 2008
    Publication date: July 16, 2009
    Applicant: BlueArc UK Limited
    Inventor: Christopher J. Aston
  • Publication number: 20090177947
    Abstract: An information recording apparatus includes a writing system for writing the datasets to the recording medium, so that each of the datasets can be identified from a certain number indicating an order that each of the datasets was sequentially written to the recording medium, and from the number of writing operations (WP) carried out for a dataset of the certain number, the writing system writing a first dataset; the writing system being configured for substantially appending a second dataset onto the first dataset, the second dataset having the same certain number as the first dataset, and for setting a value obtained by incrementing the WP of the first dataset as the WP of the second dataset.
    Type: Application
    Filed: January 5, 2009
    Publication date: July 9, 2009
    Inventors: Setsuko Masuda, Kenji Nakamura, Yutaka Oishi
  • Publication number: 20090177950
    Abstract: A rate matching method is provided for a mobile communication system that performs an adjustment to a code rate based on an optimal level by puncturing or repetition to respective bit streams of transport channels. The rate matching method is preferably applicable to uplink and downlink rate matching for channel coding including turbo coding, convolutional coding and the like. The rate matching method for uplink can include executing coding for bits of a transport channel, and branching off the bits into a plurality of sequences, constructing a first interleaving pattern for the plurality of sequences, constructing a virtual interleaving pattern for at least one sequence based on a mapping rule with a corresponding first interleaving pattern and calculating different bit shifting values in each column of each virtual interleaving pattern. Then, a bit position to be punctured is determined in each constructed virtual interleaving pattern using the calculated bit shifting values.
    Type: Application
    Filed: March 6, 2009
    Publication date: July 9, 2009
    Inventors: Young Woo YUN, Ki Jun KIM, Sung Lark KWON, Young Jo LEE, Sung Kwon HONG
  • Publication number: 20090172467
    Abstract: An information processing apparatus includes: a nonvolatile memory that has a start block for storing a boot program and a spare block for storing a spare of the boot program; and a system controller that reads out the boot program from the start block and executes start-up process in accordance with the boot program, the system controller exclusively performs error correction and detection on the nonvolatile memory, wherein when the boot program is read out from the start block and a read error that cannot be corrected based on an error correction code occurs, the system controller performs recovery process for recovering the start block using the spare of the boot program stored in the spare block.
    Type: Application
    Filed: November 11, 2008
    Publication date: July 2, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Katsuhiko ARAKI
  • Publication number: 20090158130
    Abstract: A method and apparatus for turbo encoding and method and apparatus for turbo decoding are disclosed, by which encoding and decoding speeds of turbo codes and performance thereof can be enhanced. In performing turbo encoding on inputted information bits by a unit of an information frame including a predetermined number of bits, the present invention includes dividing the information frame into at least two information sub-blocks, encoding each of the at least two information sub-blocks independently, rearranging information bits configuring the information frame by interleaving the information frame, dividing the rearranged information frame into at least two information sub-blocks, and encoding each of the at least two information sub-blocks independently.
    Type: Application
    Filed: September 5, 2006
    Publication date: June 18, 2009
    Inventors: Kyung whoon Cheun, Yong sang Kim, Wang rok Oh
  • Publication number: 20090158114
    Abstract: A communications system includes an encoder that produces a plurality of redundant symbols. For a given key, an output symbol is generated from a combined set of symbols including the input symbols and the redundant symbols. The output symbols are generally independent of each other, and an effectively unbounded number of output symbols (subject to the resolution of the key used) can be generated, if needed. The output symbols are information additive such that a received output symbol is likely to provide additional information for decoding even when many symbols are already received. The output symbols are such that a collection of received output symbols can provide probabilistic information to support error correction.
    Type: Application
    Filed: October 15, 2008
    Publication date: June 18, 2009
    Applicant: Digital Fountain, Inc.
    Inventor: M. Amin Shokrollahi
  • Publication number: 20090150623
    Abstract: The present invention provides a semiconductor device which sufficiently ensures the security and prevents the decline of the yield even when the failure or the like causes a bit change in the data of the test mode control flag stored in the nonvolatile memory. The semiconductor device of the present invention includes: a nonvolatile memory which stores a test mode control code in a predetermined address; a generation unit which generates a fixed value indicating permission for or prohibition of a test mode; and a Hamming distance determination circuit which controls switching to the test mode depending on whether or not a Hamming distance between the control code and the fixed value is equal to or less than a predetermined number.
    Type: Application
    Filed: August 7, 2006
    Publication date: June 11, 2009
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventor: Kazuki Yoshioka
  • Publication number: 20090144582
    Abstract: An anti-virus method based on a security chip according to the present invention is provided. The method comprises the following steps: a hash value obtained by a hashing operation for a computer key file and a system control program are stored in a memory of the security chip, and a backup file of the computer key file is stored in a backup storage area. When power up, the integrity of the system control program is verified by using the hash value of the system control program stored in the memory of the security chip. If the system control program is integral, a control is executed by the system control program, and the system control program verifies the integrity of the computer key file using the hash value of the computer key file stored in the memory of the security chip.
    Type: Application
    Filed: March 23, 2006
    Publication date: June 4, 2009
    Applicant: Lenovo (Beijing) Limited
    Inventors: Jun Li, Kai Wang, Rongfeng Feng, Na Xu
  • Publication number: 20090138754
    Abstract: The present invention provides a method of protecting against errors in a boot memory, the method comprising initiating booting of a processor by executing primary boot code from a primary boot memory, and based on the execution of the primary boot code: accessing a data structure comprising a plurality of redundant portions of boot information stored on a secondary boot memory; performing an error check on a plurality of the portions to determine whether those portions contain errors and, based on the error checks, to identify a valid portion; and booting the processor using the valid portion of boot information.
    Type: Application
    Filed: November 26, 2008
    Publication date: May 28, 2009
    Inventors: David Alan Edwards, Joe Woodward
  • Publication number: 20090138780
    Abstract: A method of decoding a received systematic code encoded block corresponding to an original block of information, wherein the received systematic code encoded block may include soft systematic values, may include detecting an error condition in the received systematic code encoded block. The method may also include decoding the received systematic code encoded block for retrieving the original block of information if the error condition in the received systematic code encoded block is detected and processing the soft systematic values to retrieve the original block of information instead of the decoding if the error condition in the received systematic code encoded block is not detected.
    Type: Application
    Filed: November 26, 2008
    Publication date: May 28, 2009
    Applicant: STMicroelectonics N.V.
    Inventors: Friedbert Berens, Cem Derdiyok, Franck Kienle, Timo Lehnigk-Emden, Norbert Wehn
  • Publication number: 20090132897
    Abstract: An approach to reducing processing of soft output is disclosed. Candidate sequences of bits can be compared to soft output decisions to reduce at least one of the candidate sequences. Branch metric calculations can be performed for remaining candidate sequences and a most likely path can be selected from the remaining candidate sequences.
    Type: Application
    Filed: November 19, 2007
    Publication date: May 21, 2009
    Applicant: Seagate Technology LLC
    Inventors: GuoFang Xu, Michael John Link, William Michael Radich
  • Publication number: 20090125784
    Abstract: A memory system has a plurality of operation modes corresponding to current drawn and accessibility. The system includes a nonvolatile memory which stores a transition log of an operation mode, and a controller which, whenever accessing a predetermined amount of data of the nonvolatile memory in the same operation mode, adds the operation mode to the transition log, and determines a present operation mode by using the transition log.
    Type: Application
    Filed: November 13, 2008
    Publication date: May 14, 2009
    Inventor: Takashi OSHIMA
  • Publication number: 20090119570
    Abstract: The present invention relates to a method, apparatus and computer program product for detecting a transport format of a multiplexed transport channel used for transferring binary data, wherein a path metric value which estimates likelihood for a hypothetical trellis path to end at a predetermined state is determined for every state of a trellis stage of a possible end bit position of a data block of the transport channel. Then, for each possible end bit position a number of path metric values which indicate higher likelihood for the hypothetical trellis path to end at said predetermined state than an initial state is calculated, and the best end bit positions which lead to highest values of the calculated number are selected and error checking is performed for the selected best end bit positions to detect the transport format. The proposed selection of best end bit positions leads to a reduced number of decoding operations and thus to a reduced processing complexity.
    Type: Application
    Filed: December 16, 2005
    Publication date: May 7, 2009
    Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V.
    Inventors: Franz Eder, Pierre Demaj
  • Publication number: 20090113270
    Abstract: For the coded data that was transmitted via a communication channel, a known code portion thereof that is a code portion corresponding to known data is detected. When the known code portion is not detected from the coded data, the coded data will be decoded. When the known code portion is detected from the coded data, at least a part thereof will be replaced with normal data, and the decoding will be performed on the coded data after the substitution.
    Type: Application
    Filed: October 14, 2008
    Publication date: April 30, 2009
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Masao Orio, Mitsunori Takanashi
  • Publication number: 20090106624
    Abstract: According to an error correction method of the present invention, in the case of decoding a code word (104) which is doubly encoded by adding first and second inspection data (102,103) having minimum distances d1 and d2 from other data, respectively, a position Ex of an erasure symbol X for which an error was detected using the second inspection data (103) but the error could not be corrected is regarded as an erasure position, and a pseudo erasure symbol Y for which an error was detected using the second inspection data (103) and the error was corrected is regarded as being erroneously corrected and a position Ey of this pseudo erasure symbol is also regarded as an erasure position in first-time decoding, and erasure corrections for up to (d1?d) pieces of symbols are performed at one time using the first inspection data (102) when performing second-time decoding using these position information Ex and Ey.
    Type: Application
    Filed: August 31, 2006
    Publication date: April 23, 2009
    Inventors: Hiroaki Kondo, Shiro Shimizu
  • Publication number: 20090106584
    Abstract: Provided is a storage apparatus that can dramatically shorten the time for recovery from a fault in a storage device. In a storage apparatus provided with one or more storage devices and a method for controlling the storage apparatus, when a fault occurs in the storage device, whether or not the fault is a predetermined specific fault is judged, and the storage device is rebooted if the fault is the predetermined specific fault. As a result, recovery from the fault can be achieved in a dramatically shorter amount of time than the time required for replacement of the storage device. Accordingly, the time for recovery from the fault in the storage device can be shortened dramatically.
    Type: Application
    Filed: February 1, 2008
    Publication date: April 23, 2009
    Inventors: Yosuke NAKAYAMA, Hiromi Matsushige, Hiroshi Suzuki
  • Publication number: 20090103649
    Abstract: Embodiments are directed to transmitting L1 pre-signaling information with predetermined modulation and code rate such that L1 pre-signaling information can be received without preliminary knowledge on the network. L1 pre-signaling information makes it possible to receive the L1 signaling information, data link layer information, and notification data that may have configurable code rates and modulation. Therefore, L1 pre-signaling information can be thought of as signaling metadata (i.e., information about other signaling information). L1 signaling is divided into pre-signaling and signaling parts. The pre-signaling part includes parameters used for receiving the L1 signaling information. L1 pre-signaling signaling enables the receiver to receive the signaling itself (L1 signaling and data link layer information) by informing the receiver about the type of modulation, coding, and the like, used to transmit the L1 signaling, data link layer, and notification information.
    Type: Application
    Filed: October 22, 2007
    Publication date: April 23, 2009
    Applicant: Nokia Corporation
    Inventors: Jani Vare, Jussi Vesma, Tero Jokela
  • Publication number: 20090100310
    Abstract: An apparatus and a method for Hybrid Automatic Repeat reQuest (HARQ) in a wireless communication system are provided. A receiver includes a Media Access Control (MAC) layer part for error-checking each MAC Packet Data Units (PDUs) extracted from a physical layer burst, and generating HARQ combination control information according to a result of the error check; a receiving part for receiving a retransmit burst; and a combiner for selecting one or more Forward Error Correction (FEC) blocks from the retransmit burst according to the HARQ combination control information, and HARQ-combining the selected one or more FEC blocks.
    Type: Application
    Filed: October 8, 2008
    Publication date: April 16, 2009
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Kyung-Chul Yoo, Jin-Woo Roh, Bong-Gee Song, Dong-Min Kim, Jung-Ho Lee
  • Publication number: 20090094489
    Abstract: A method and apparatus for identifying a device associated with a transmission error. The method generally comprising including a device identification information upon detection of a transmission error and further modifying an error check parameter according to a predefined rule.
    Type: Application
    Filed: October 9, 2007
    Publication date: April 9, 2009
    Inventor: Soon Seng Seh
  • Publication number: 20090083504
    Abstract: A data storage method comprises storing first data in at least a first data chunk, wherein the first data chunk is a logical representation of one or more sectors on at least a first disk drive in a storage system; storing first metadata, associated with the first data, in at least a first appendix, wherein the first appendix is a logical representation of a sector region on at least the first disk drive in the storage system, and wherein the first metadata comprises first atomicity metadata (AMD) and first validity metadata (VMD) associated with the first data; and storing a copy of the first VMD for the first data in at least one low latency non-volatile storage (LLNVS) device.
    Type: Application
    Filed: September 24, 2007
    Publication date: March 26, 2009
    Inventors: Wendy Belluomini, John Edward Bish, Kenneth Day, III, James Hafner, Bret S. Weber
  • Publication number: 20090077457
    Abstract: The iterative decoding of blocks may be continued or terminated based on CRC checks. In an example embodiment, one iteration of an iterative decoding process is performed on a block whose information bits are covered by a CRC. The iterative decoding process is stopped if the CRC checks for a predetermined number of consecutive iterations. In another example embodiment, a decoding iteration is performed on a particular sub-block of multiple sub-blocks of a transport block, which includes a single CRC over an entirety of the transport block. The CRC is checked using decoded bits obtained from the decoding iteration on the particular sub-block and decoded bits obtained from previous decoding iterations on other sub-blocks of the multiple sub-blocks. The decoding iteration is then performed on a different sub-block if the CRC does not check. Also, the decoding iterations for the sub-blocks may be terminated if the CRC checks.
    Type: Application
    Filed: September 19, 2008
    Publication date: March 19, 2009
    Inventors: Rajaram Ramesh, Havish Koorapaty, Jung-Fu Thomas Cheng, Kumar Balachandran
  • Publication number: 20090077448
    Abstract: A present invention discloses a method for performing forward error correction (FEC) in long-haul submarine transmission systems. Data is encoded at a transmitter by serially concatenated, binary Bose-Ray-Chaudhuri-Hochquenghem (BCH) error correcting codes. The invention encodes a stream of data employing a plurality of serially concatenated, binary Bose-Ray-Chaudhuri-Hochquenghem (BCH) error correcting codes, arranging said data into a frame of parallel data blocks (the outer frame) with redundancy bits appended by a BCH(3896, 3824) code; the outer frame is then interleaved to produce a frame of serial data blocks (the intermediate frame); and the final frame (the inner frame) is produced by appending the redundancy bits of the BCH(2040, 1952) code to the intermediate frame. The data, once encoded, is transmitted across a datapath and decoded at the receiver.
    Type: Application
    Filed: November 29, 2007
    Publication date: March 19, 2009
    Applicant: Avalon Microelectronics, Inc.
    Inventors: Wally Haas, Chuck Rumbolt
  • Publication number: 20090070637
    Abstract: An apparatus comprises a memory with a matrix (10) with rows and columns of memory cells. A read access circuit (14, 16, 18) executes a read command to read a retrieval unit comprising data from a row of the memory cells from the matrix (10) and to output data from the retrieval unit. A processing circuit (12) coupled to the read access circuit (14, 16, 18) is configured to execute an extra read operation involving issuing the read command, receiving the extra data (24), performing error detection on only the extra data (24), using an error detecting code in which the extra data is coded, conditionally performing error correction on the data from the extra data (24) using data from the retrieval unit including the payload data (22), according to an error correcting code in which the retrieval unit is coded, if the error detection indicates an error in the extra data (24).
    Type: Application
    Filed: March 5, 2007
    Publication date: March 12, 2009
    Applicant: NXP B.V.
    Inventors: Victor M.G. Van Acht, Nicolaas Lambert
  • Publication number: 20090070658
    Abstract: During decoding using a Viterbi based detector, erasures are detected when surviving paths do not merge in an associated decoding window.
    Type: Application
    Filed: September 12, 2007
    Publication date: March 12, 2009
    Inventors: Ara Patapoutian, Rose Y Shao
  • Publication number: 20090064176
    Abstract: In one embodiment, the present invention includes a method for executing a first reduction operation on data in an input buffer, executing a second reduction operation on the data, where the second reduction operation has a higher reliability than the first reduction operation, and comparing the first and second results. Other embodiments are described and claimed.
    Type: Application
    Filed: August 30, 2007
    Publication date: March 5, 2009
    Inventors: Patrick Ohly, Victor Shumilin
  • Publication number: 20090055709
    Abstract: A data Interface for transferring digital data between a host and a client over a communication path using packet structures linked together to form a communication protocol for communicating a pre-selected set of digital control and presentation data. The signal protocol is used by link controllers configured to generate, transmit, and receive packets forming the communications protocol, and to form digital data into one or more types of data packets, with at least one residing in the host device and being coupled to the client through the communications path. The interface provides a cost-effective, low power, bi-directional, high-speed data transfer mechanism over a short-range “serial” type data link, which lends itself to implementation with miniature connectors and thin flexible cables which are especially useful in connecting display elements such as wearable micro-displays to portable computers and wireless communication devices.
    Type: Application
    Filed: October 28, 2008
    Publication date: February 26, 2009
    Applicant: QUALCOMM Incorporated
    Inventors: Jon James ANDERSON, Brian Steele, George Alan Wiley, Shashank Shekhar
  • Publication number: 20090044075
    Abstract: An arrangement for storing data has a plurality of N storage devices S1 . . . SN, wherein at least one of the storage devices has a storage capacity that not equal to a storage capacity of others of the storage devices. A storage device SMAX has a largest capacity of the plurality of storage devices S1 . . . SN. A fountain encoder encodes the data into F fountain codewords, wherein F = ? K = 1 N ? F K with K being a counting integer; and the fountain encoder distributes the fountain codewords among the N storage devices S1 . . . SN in approximate proportion to the storage capacity CK of each of the N storage devices S1 . . . SN subject to the constraint that enough fountain codewords are stored in each of the N storage devices, to assure that all of the data in all of the N storage devices can be recovered if any one of the N storage devices SP is lost using the fountain codewords stored in the remaining storage devices S1 . . . SN excluding SP.
    Type: Application
    Filed: March 20, 2008
    Publication date: February 12, 2009
    Inventor: Christopher Jensen Read
  • Publication number: 20090037750
    Abstract: A system comprises a storage device comprising code that is executable to cause recovery of at least one of an operating system and system firmware. Logic coupled to the storage device is also provided to cause the storage device to be unusable until a request is provided to recover at least one of the operating system and system firmware.
    Type: Application
    Filed: July 31, 2007
    Publication date: February 5, 2009
    Inventor: Paul BOERGER