Abstract: In an information recording medium for recording and reproducing data thereon on a sector-by-sector basis, the recorded data being managed as at least one file by using a file structure, the file structure includes unused space management information for identifying a used region and an unused region. At least one defective region is registered as an unused region in the unused space management information, the at least one defective region being a region on the information recording medium which is incapable of proper reproduction of the recorded data.

Abstract: A decoding method is presented for error-correcting codes based on the syndrome decoding scheme, which means the set of all syndromes is one-to-one corresponding to the set of all correctable error patterns. The improvement in the high-speed error-correcting capability is achieved by searching a syndrome-error table, which is built upon the mathematical basis: there is a one-to-one correspondence between the set of all syndromes and the set of all correctable error patterns. Two embodiments of the present invention are described. The first embodiment uses a full syndrome-error table, whereas the second uses a partial syndrome-error table. The method includes the following steps: calculating a syndrome corresponding to the received bit string; determining whether the syndrome is a zero bit string; when the syndrome is not a zero bit string, determining an error pattern from the syndrome-error table; and correcting the corrupted codeword using the error pattern.

Abstract: A system comprising communication logic capable of receiving data signals from a network. The signals comprise both erasure error and random error. The system also comprises processing logic coupled to the communication logic and adapted to partition parity check bytes of the received signals into a first portion and a second portion. The processing logic uses the first portion for random error correction and the second portion for erasure error correction.

Abstract: A memory system includes a plurality of memory devices; and a memory controller having a plurality of communication channels for communicating data with the plurality of memory devices. The memory controller includes an error correction encoder that is adapted to encode data to be communicated from the memory controller via the plurality of communication channels, and/or an error correction decoder that is adapted to detect and correct errors in data communicated to the memory controller via the plurality of communication channels.

Abstract: This invention provides an error correction system whereby codes, including codes known to be optimum, may be concatenated together so that a longer code is produced which may be decoded by decoding the individual codes using any type of error correcting decoder including list decoders, Dorsch decoders in particular, and iterative decoders. The concatenated code consists of one or more codes having replicated codewords to which are added codewords from one or more other codes. The code construction is utilised in the receiver with a decoder that firstly decodes one or more individual codewords from a received vector. The detected codewords from this first decoding are used to undo the code concatenation within the received vector to allow the replicated codewords to be decoded. Examples of the performance benefits of the invention in comparison to the well known state of the art coding arrangement of LDPC codes, and turbo codes using iterative decoders are given for (256,128) and (512,256) codes.

Abstract: The ability to accurately and efficiently calculate and report communication errors is becoming more important than ever in today's communications environment. More specifically calculating and reporting CRC anomalies in a consistent manner across a plurality of communications connections in a network is crucial to accurate error reporting. Through a normalization technique applied to a CRC computation period (e.g., the PERp value), accurate error identification and reporting for each individual connection can be achieved.

Abstract: To reset only the CPU in a component in an abnormal condition without affecting CPUs of components in a normal condition, a multi-component system, in which a plurality of components each including at least a CPU are connected via a common bus to each other, includes a first reset signal generating unit which generates a reset signal by a switch operation to send the reset signal to respective components and a judge unit which is disposed in each component to determine whether or not resetting of a CPU is allowed. The judge unit inhibits, if the CPU is in a normal condition, the resetting of the CPU in response to the reset signal and resets, if the CPU is in an abnormal condition, the CPU in response to the reset signal.

Abstract: Apparatus and methods store error recovery data in different dimensions of a memory array. For example, in one dimension, block error correction codes (ECC) are used, and in another dimension, supplemental error correction codes, such as convolutional codes, are used. By using separate dimensions, the likelihood that a defect affects both error recovery techniques is lessened, thereby increasing the probability that error recovery can be performed successfully. In one example, block error correction codes are used for data stored along rows, and this data is stored in one level of multiple-level cells of the array. Supplemental error correction codes are used for data stored along columns, such as along the cells of a string, and the supplemental error correction codes are stored in a different level than the error correction codes.

Abstract: Apparatus and methods store stream-based error recovery data for a memory array, such as a NAND flash array. Conventionally, data is block coded per industry specification and stored in the memory array. Within the limits of the block code, this technique provides for correction of errors. By applying a stream-based inner code, that is, concatenating the outer block code with an outer code, the error correction can be further enhanced, enhancing the reliability of the device. This can also permit a relatively small-geometry device to be used in a legacy application.

Abstract: Described is processing a manifest associated with a software component (such as for installation purposes) to determine whether the manifest has errors, and if so, providing a corrected manifest. To process the manifest, an identifier associated with the manifest is used to consult a correction data store to determine whether the manifest is known to require correction. The identifier may be generated via a hash (e.g., of the manifest contents) if one is not appropriately associated with the manifest. If the manifest is known to require correction, a corrected manifest is used, such as from a substitute corrected manifest, or a set of deltas that modify the manifest into the corrected manifest. The substitute manifest or deltas may be in the data store or obtained via a link. A corrected manifest may also be provided by evaluating the manifest for rule violations, and fixing any rule violations that are found.

Abstract: An image data-processing apparatus (100) includes an image data-decoding unit (10) operable to execute pipeline processing-assisted image decoding processing, a pipeline controller (20) operable to control pipeline processing in the image data-decoding unit (10), a memory (30), and an input/output interface (40). The pipeline controller (20) executes control over the pipeline processing on the basis of information on the start-up of pipeline stages. The information is stored in a start-up table storage unit (23). The present configuration makes it feasible to provide an image data-processing apparatus operable to suppress degradation in decoded images to a minimum degree when pipeline control is disturbed upon the occurrence of decoding errors during the decoding processing, whereby high-quality images are realized.

Abstract: Memory devices that, in a particular embodiment, receive and transmit analog data signals representative of bit patterns of two or more bits such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming error correction code (ECC) and metadata into such memory devices includes storing the ECC and metadata at different bit levels per cell based on an actual error rate of the cells. The ECC and metadata can be stored with the data block at a different bit level than the data block. If the area of memory in which the block of data is stored does not support the desired reliability for the ECC and metadata at a particular bit level, the ECC and metadata can be stored in other areas of the memory array at different bit levels.

Abstract: In a method for error correction of packet data, in particular DAB data packets, code words being used over multiple data packets, redundancy information for error correction is added while maintaining the original packet data structure, at the cost of a free data field or a useful data field. The cycle of the error protection is selected as a multiple of a minimum size for a packet length.

Abstract: In one aspect, a memory device includes a memory cell array, parallel internal data paths which transmit internal data to and from the memory cell array, a data driver which transmits and receives external data, and a data buffer which delays and transfers the external data received by the data driver to the internal data paths, and which delays and transfers the internal data transmitted from the memory cell array to the data driver. The memory device further includes an error correction code generator which generates an error correction code (EC) based on the internal data transmitted on the internal data paths, an EC buffer which delays the error correction code generated by the error correction code generator, an EC driver which transmits the error correction codes delayed by the EC buffer, and a latency controller which variably controls a delay time of at least one of the data buffer and the EC buffer.

Abstract: An architecture and a method are provided for decoding codewords for codes such as low density parity check (LDPC) codes. An iterative decoding algorithm such as the Belief Propagation Algorithm (BPA) is employed that attempts to correct errors in an input block of symbols via a structure containing two sets of nodes through node processing and the passing of messages between nodes. Message passing and node processing is performed in a digit-serial manner instead of a bit-parallel manner.

Abstract: A fixed-length block is repetitively generated. The fixed-length block includes a sync information piece, “n-m” information pieces following the sync information piece, an ID information piece following the “n-m” information pieces, and “m” information pieces following the ID information piece, where “n” denotes a natural number equal to or greater than 2, and “m” denotes a natural number smaller than “n” and equal to or greater than 1. The generated fixed-length block is recorded on a recording medium. The ID information piece is placed in an intermediate portion of the fixed-length block.

Abstract: According to an aspect of the embodiment provides a method for controlling a processing device for distributing jobs among a plurality of job processing devices for executing the jobs, respectively. The method comprises the steps of: transmitting a job to one of the job processing devices to have the job executed by the one of the job processing devices; generating a procedure information for transmitting a continuation data from the one of the job processing devices before completion of execution of the job back to the processing device, the continuation data enabling another job processing device to continue execution of the job; and transmitting the procedure information to and receiving the continuation data from the one of the job processing devices.

Abstract: A data structure for a flash memory and data reading/writing method thereof are disclosed. A 512 bytes data and a redundant code derived from the data encoded with a 6-bit error correcting code scheme are stored in a first sector and a second sector with sequential address in a block of the flash memory respectively. A logic block address information of this block is divided into two parts that are stored in the first sector and the second sector respectively.

Abstract: In a mobile communication system, an error detection code or a quality frame indicator (e.g., CRC) is generated using selectively frame information, and at least one of a WCA identifier of another terminal, and a corresponding terminal identifier. And the terminal identifier can be implicitly transmitted to the receiver.

Abstract: An Error Control Code (ECC) apparatus applied to a memory of a Multi-Level Cell (MLC) method may include: a bypass control signal generator generating a bypass control signal; and an ECC performing unit that may include at least two ECC decoding blocks, determining whether to bypass a portion of the at least two ECC decoding blocks based on the bypass control signal, and/or performing an ECC decoding. In addition or in the alternative, the ECC performing unit may include at least two ECC encoding blocks, determining whether to bypass a portion of the at least two ECC encoding blocks based on the bypass control signal, and/or performing an ECC encoding. An ECC method applied to a memory of a MLC method and a computer-readable recording medium storing a program for implementing an EEC method applied to a memory of a MLC method are also disclose.

Abstract: A digital lighting control network protocol with forward and backward frames, each of the frames including an error check code. A no-acknowledgment (NAK) signal is sent from a receiving node to a transmitting node responsive to the error check code. An interface circuit of the receiving node may include an energy storage section to store at least some energy from the network while receiving digital signals, and an output section to transmit digital signals to the network using the stored energy. The interface circuit may also include a high voltage buffer circuit. The transmitting node may send forward frames to receiving nodes based on device type.

Abstract: An E2PR4 Viterbi detector includes a recovery circuit and receives a signal that represents a sequence of values, the sequence having a potential state. The recovery circuit recovers the sequence from the signal by identifying a surviving path to the potential state and, after identifying the surviving path, adding a modified branch metric to the path metric of the surviving path to generate an updated path metric for the potential state. Updating the path metric of the surviving path after the surviving path is selected allows the E2PR4 Viterbi detector to be smaller and/or faster than an E2PR4 Viterbi detector that updates the path metric before selecting the surviving path.

Abstract: To improve the availability of a data processing system despite possible memory errors, when reading a data word from a memory cell, the integrity of the data word is checked on the basis of redundant additional information, and if the data word turns out to be corrupted, an error correction procedure is performed in which the reliability performance of the memory cell is checked and, if the memory cell is found to be operational, its contents are restored.

Abstract: In order to provide an error detection/correction circuit (100; 100?) as well as a method for detecting and/or for correcting at least one error of at least one data word, said data word comprising—information in the form of at least one information bit or at least one pay load data bit, and—redundancy in the form of at least one check bit or at least one redundant bit, wherein the number of the one or more check bits or redundant bits being supplemented to the respective data word is optimized, in particular wherein at least one physical memory space can be used in an optimized way depending on the requirements of the application, it is proposed—to perform at least one first error correction scheme being assigned to at least one first data path (30; 30?), and—to perform at least one second error correction scheme—being assigned to at least one second data path (40; 40), and—being designed for increasing the information and/or the redundancy, in particular—for increasing the number of the one or more informat

Abstract: The invention relates to a method of transmitting digital data packets protected by error correction packets and more precisely the manner of inserting these correction packets into the data packet stream so as to increase the correction effectiveness of the error correction method while limiting the latency introduced into the transmission. The packets are set out in matrix form, error packets are computed on lines and columns and are inserted regularly into the stream at a sufficient distance from the data packets that they protect.

Abstract: There have been proposals to extend the MPE protocol to support different FEC schemes on the MPE layer. Examples of these proposals include: TM-SSP0178 describing a multiburst sliding encoding scheme based on Reed-Solomon (RS) codes, TM-SSP0199r1 describing a block-based encoding scheme based on multi-stage chain reaction (MSCR) codes, and TM-SSP0222 describing a multiburst sliding encoding scheme based on MSCR codes. A framework for harmonizing and integrating those techniques is described herein.

Abstract: A method for protecting the integrity of a set of memory pages to be accessed by an operating system of a data processing system, includes running the operating system in a virtual machine (VM) of the data processing system; verifying the integrity of the set of memory pages on loading of pages in the set to a memory of the data processing system for access by the operating system; in response to verification of the integrity, designating the set of memory pages as trusted pages and, in a page table to be used by the operating system during the access, marking non-trusted pages as paged; and in response to a subsequent page fault interrupt for a non-trusted page, remapping the set of pages to a region of the data processing system memory which is inaccessible to the virtual machine.

Abstract: Systems, methods, and computer program products that can be used concurrently or alternatively to detect errors in data as well as to protect access to data are provided. Embodiments enable a coherent data set (CDS) which is a data set guaranteed to be genuine and error-free at run-time. Embodiments provide systems, methods, and computer program programs to create a CDS, identify a CDS, and verify the coherency of a data set purported to be a CDS. Embodiments further enable privileged functions which are functions that can only be accessed by a restricted set of other privileged functions. Embodiments provide systems, methods, and computer program products to create, identify, and protect access to privileged functions.

Abstract: An error determining apparatus includes an Error Detection Code (EDC) error detector to detect an EDC error of data read from an optical disk, a continuity error detector to detect a continuity error of a currently decoded address by comparing the currently decoded address and a previously decoded address, and an error determiner to receive information on the previously determined error state and to determine a final error state of the currently decoded address of the optical disk based on the EDC error detected by the EDC error detector, the continuity error detected by the continuity error detector, and the previously determined error state.

Abstract: A method, computer program product and system for switching a defective signal line with a spare signal line without shutting down the computer system. A service processor monitors error correction code (ECC) check units configured to detect an error in a signal line. If an ECC check unit detects an error rate that exceeds a threshold, then the signal line with such an error rate may be said to be “defective.” The service processor configures switch control units in the driver/receiver pair associated with the defective signal line to be able to switch the defective signal line with a spare line upon receipt of a command from a memory controller switch control unit. In this manner, the system is not deactivated in order to switch a defective signal line with a spare line thereby reducing the time that the processor cannot send information to the memory buffers.

Abstract: A method, computer program product, and data processing system for providing optional failure recovery features in operating system kernel code are disclosed. In accordance with a preferred embodiment, a segment of mainline code may designate a recovery routine for that segment by calling a kernel service provided for that purpose. The kernel service allocates a “footprint” region on the recovery stack for storing state information arising from the execution of the recovery-enabled code. In the event of an exception, a recovery manager routine uses information from the recovery stack to recover from the exception. Recovery may be disabled altogether for performance purposes by way of boot-time patching to disable the use of the recovery stack and to allow state information to be written to a static “scratchpad” area, which unlike the recovery stack, is allowed to be overwritten, its contents being ignored.

Abstract: A system and method of error recovery for backup applications that utilizes error recovery logic provided in the storage controller itself are provided. With the system and method, error recovery logic is provided in the storage controller for generating and maintaining error recovery logs for one or more backup operations of one or more backup applications running on one or more host systems. The backup applications may utilize an established set of commands/API function calls to invoke the error recovery logic on the storage controller. At the initiation of the backup operation, the storage controller assigns a unique identifier to the backup operation and returns this identifier to the backup application. The backup application may then use this identifier to initiate error recovery operations or commit changes made during the backup operation via the storage controller. Thus, the storage controller offloads the burden of error recovery from the backup applications.

Abstract: A method, system, and computer program product for simultaneous multi-channel upload of a file to one or more servers while ensuring data integrity. A validation scheme employs hashes to allow segments of the data file to be separately validated. Thus, if the upload process is interrupted or otherwise corrupted, segments of previously transferred data which have been transferred correctly may be validated, eliminating the need for re-transmission of that correctly transferred data.

Abstract: The invention provides a method of decoding a decided signal received from a decision circuit to supply a decoded signal, said method comprising: a step of detecting a word of N bits in said received decided signal to supply a detected word; a step of selecting an admissible word of N bits in a dictionary of the error correction code used for encoding in accordance with a criterion of the shortest distance between said detected word and said selected admissible word; and a step of decoding a word of L bits constituting said decoded signal from said selected admissible word. According to the invention, the distance used in the selection step takes account of the relative reliabilities of 2K sequences of K bits, 0<K<N.

Abstract: An apparatus, system, and method are disclosed for data storage with progressive redundant array of independent drives (“RAID”). A storage request receiver module, a striping module, a parity-mirror module, and a parity progression module are included. The storage request receiver module receives a request to store data of a file or of an object. The striping module calculates a stripe pattern for the data. The stripe pattern includes one or more stripes, and each stripe includes a set of N data segments. The striping module writes the N data segments to N storage devices. Each data segment is written to a separate storage device within a set of storage devices assigned to the stripe. The parity-mirror module writes a set of N data segments to one or more parity-mirror storage devices within the set of storage devices. The parity progression module calculates a parity data segment on each parity-mirror device in response to a storage consolidation operation, and stores the parity data segments.

Abstract: There are provided an optical line terminal and an optical network terminal, which can process with the same forward error correction code even if an EFC frame size of G-PON descending signals is different between two types of 255 and 120. The optical network terminal includes a photoelectric converter, a PON transceiver, and a physical layer. The PON transceiver includes an error correction code encoder including a shortening compensation parameter table and a shortening compensation calculator for calculating compensated data by referring to the shortening compensation parameter table. Also the optical line terminal includes a photoelectric converter, a PON transceiver, and a physical layer. The optical line terminal includes an error correction code encoder including a shortening compensation parameter table and a shortening compensation calculator for calculating compensated data by referring to the shortening compensation parameter table.

Abstract: A unit and method for distributing data from at least one data source in a system provided with at least two computer units, containing switching means which are used to switch between at least two operating modes of the system, wherein data distribution and/or selection of a data source is dependent upon the operating mode.

Abstract: A system, method, and computer program product for recovering from data errors. In a SCSI hard drive system, when a unrecoverable data error condition is encountered, the logical block address is reassigned using information provided by the data scrubbing functionality of the SCSI hard drive.

Abstract: An apparatus, system, and method are disclosed for managing data in a solid-state storage device. A solid-state storage and solid-state controller are included. The solid-state storage controller includes a write data pipeline and a read data pipeline The write data pipeline includes a packetizer and an ECC generator. The packetizer receives a data segment and creates one or more data packets sized for the solid-state storage. The ECC generator generates one or more error-correcting codes (“ECC”) for the data packets received from the packetizer. The read data pipeline includes an ECC correction module, a depacketizer, and an alignment module. The ECC correction module reads a data packet from solid-state storage, determines if a data error exists using corresponding ECC and corrects errors. The depacketizer checks and removes one or more packet headers. The alignment module removes unwanted data, and re-formats the data as data segments of an object.

Abstract: Embodiments of the invention generally provide a method and apparatus for correcting errors in a memory device. In one embodiment, the method includes receiving a read command and a read address for the read command and reading data from a first location of the memory device corresponding to the read address. The method also includes reading error correction information corresponding to the read address. If the error correction information indicates an error in the data, the error in the data is corrected to produce corrected data and the corrected data is output from the memory device. The corrected data is also written back to a second location in the memory device corresponding to the read address.

Abstract: A first storing unit stores therein information on a communication status relating to installing positions of a plurality of storage devices forming a disk array. A selecting unit selects a plurality of storage devices for storing data, based on stored information. A second storing unit stores recovery data recovered from a storage device from which a failure is detected from among the storage devices forming the disk array in selected storage devices in a striping manner.

Abstract: A system and method for tracking and restoring computer configuration are disclosed. In one aspect, the system and method monitors for a series of changes in watched one or more computer configuration variables. The changes are registered into a series of saved states. The one or more computer configuration variables may be restored to a desired saved state using the registry of saved states. In one aspect, the system and method monitors the changes by intercepting system calls, determining which system calls affect the one or more computer configuration variables, and logging the system calls and the results of the system calls that affect the one or more computer configuration variables. A recovery script may be dynamically generated to restore to a saved state.

Abstract: A frame error concealment method and apparatus and a decoding method and apparatus using the same. The frame error concealment method includes setting a concealment method to conceal an error based on one or more signal characteristics of an error frame having the error and concealing the error using the set concealment method.

Abstract: Methods and apparatus for adjusting a phase difference between clock signals. A first clock signal at a memory controller is adjusted relative to a clock second signal at a memory device. In one embodiment, data is transferred to the memory device according to the first clock signal, which has a predetermined phase relationship with second clock signal. Data received at the memory device is sampled at the memory device according to the second clock signal. Analysis is done of the data on the memory controller and of the received data on the memory circuit. On the basis of the analysis, an adjustment may be made to the phase relationship.

Abstract: A soft decision value correction method can detect interference occurring in a desired wave and correct a soft decision value where a received power difference between the desired wave and an interference wave is small. A receiver and a program capable of performing the soft decision value correction method are provided. In the receiver an EVM calculator sets a detection distance for a primary modulation symbol of the first subcarrier in the first OFDM symbol as a reference, and calculates an evaluation value ?El,m that is an index of a distance between the primary modulation symbol of the reception signal and the reference. When the evaluation value ?El,m is greater than or equal to a normal threshold, a weighting controller infers that interference occurred, and multiplies a soft decision value Wl,m,n by a weighting factor to calculate a corrected soft decision value Vl,m,n.

Abstract: Embodiments of the present invention provide Forward Error Correcting Code encoders and decoder structures that use DRAM in their memory designs. DRAM is a very attractive memory options in many electronic systems due to the high memory density provided by DRAM. However, the DRAM is typically not included in ASIC or FPGA implementations of encoders and decoders due to complex refresh requirements of DRAM that are required to maintain data stored in DRAM and may interfere with user access to the memory space during refresh cycles. Embodiments of the present invention provide FECC encoder and decoder structures that are implemented using DRAM that do not require complex refresh operations to be performed on the DRAM to ensure data integrity. Accordingly, embodiments of the present invention maximize memory density without the added complexity of introduced by the refresh requirements of DRAM.

Abstract: In a tape recording apparatus having a write head and a read head, a data block is stored by writing to a tape via the write head. The tape moves past the write head in a predetermined direction and writes a first data block responsive to transmitting the first data block from the computer system. The read head then reads the written data block from the tape. For reading, the tape moves past the read head in the same, predetermined direction as the writing, and the reading of the first data block occurs without reversing the tape movement after the writing of the first data block. Portions of the transmitted and read data blocks are compared and a corruption indication is sent responsive to the comparing.

Abstract: When a convolution code is decoded, electric power consumption is certainly suppressed keeping error correction capability. In a Viterbi decoder 100 which decodes received signal, a convolution code, having plural series with a soft decision Viterbi decoding method, an estimation control unit 30 estimates quality of the received signal and outputs control signal M according to the quality to a branch metric calculation data obtaining unit 20. The branch metric calculation data obtaining unit 20 performs logical combination operation between digital multi-value data S1 expressing amplitude of the received signal and the control signal M, and thereby, outputs the digital multi-value data S1 directly to a decoding execution unit 90 if the quality of the received signal is lower than a prescribed level, and outputs the digital multi-value data S1 reduced by series each as branch metric calculation data S2 to the decoding execution unit 90 if the quality of the received signal is no less than the prescribed level.

Abstract: A system having a transmission unit transmitting an output data signal formed from output data and related error detection code and a corresponding receiving unit. The output data signal is pre-emphasized by a pre-emphasis driver in the transmission unit. The receiving unit includes an equalizer equalizing the received output data signal and an error detector analyzing the error detection code to determine whether a bit error is present in the received data. Upon successive data transmission failures either an equalization coefficient in the equalizer or a pre-emphasis coefficient in the pre-emphasis driver are changed.

Abstract: An apparatus according to the present invention is designed to perform formatting processing on an information storage medium. The storage medium has a data storage area including a user data area and a spare area. The user data area is provided to write user data on, while the spare area includes a replacement block to be used as a replacement for a block that has been detected as a defective block. The replacement block stores instruction information that instructs to read data from the defective block when data is read from the replacement block. The apparatus includes a control section for controlling the formatting processing. In performing the formatting processing, the control section updates information stored in the replacement block such that when data is read from the replacement block, the data is not read from the defective block.