Physical Design Processing Patents (Class 716/110)
  • Patent number: 8799839
    Abstract: An extraction tool for, and method of, determining a stage delay associated with an integrated circuit (IC) interconnect. In one embodiment, the extraction tool includes: (1) a driver strength estimator configured to extract dimensions of a driver associated with the interconnect and estimate a driver strength therefrom, (2) a driver delay estimator coupled to the driver strength estimator and configured to estimate a driver delay based on the driver strength, (3) an interconnect delay estimator configured to estimate an interconnect delay based on extracted C and RC parameters associated with the interconnect and (4) a stage delay estimator coupled to the driver delay estimator and the interconnect delay estimator and configured to estimate the stage delay based on the driver delay and the interconnect delay.
    Type: Grant
    Filed: July 24, 2008
    Date of Patent: August 5, 2014
    Assignee: LSI Corporation
    Inventors: Alexander Y. Tetelbaum, Richard A. Laubhan
  • Patent number: 8799845
    Abstract: An adaptive patterning method and system for fabricating panel based package structures is described. Misalignment for individual device units in a panel or reticulated wafer may be adjusted for by measuring the position of each individual device unit and forming a unit-specific pattern over each of the respective device units.
    Type: Grant
    Filed: September 7, 2010
    Date of Patent: August 5, 2014
    Assignee: Deca Technologies Inc.
    Inventors: Christopher M. Scanlan, Timothy L. Olson
  • Patent number: 8799850
    Abstract: Some embodiments provide a system that performs a simulation within an electronic design automation (EDA) application. During operation, the system obtains a design from a user of the EDA application. Next, the system performs the simulation using the design to create a set of current simulation results associated with the design. The system then automatically saves a current design state of the design which is associated with the current simulation results. Finally, the system enables subsequent access to the current design state and one or more previous design states of the design by the user through a graphical user interface (GUI) associated with the EDA application.
    Type: Grant
    Filed: October 29, 2009
    Date of Patent: August 5, 2014
    Assignee: Synopsys, Inc.
    Inventors: Salem L. Ganzhorn, Kristin M. Beggs, Govindaswamy Chithamudali
  • Patent number: 8799842
    Abstract: Systems, methods, and other embodiments associated with analyzing interconnects for global wires of a circuit are described. In one embodiment, for a target wire in a circuit design, a method includes determining an inductance value and a capacitance value for parallel wires to the target wire. The method then calculates a second capacitance value for non-parallel wires to the target wire and calculates an estimated inductance value for the non-parallel wires based on the second capacitance value. A circuit model for the target wire may then be generated using the inductance and capacitance values.
    Type: Grant
    Filed: September 10, 2012
    Date of Patent: August 5, 2014
    Assignee: Oracle International Corporation
    Inventors: Bogdan Tutuianu, George J. Chen
  • Publication number: 20140215419
    Abstract: A system and method for designing integrated circuits and predicting current mismatch in a metal oxide semiconductor (MOS) array. A first subset of cells in the MOS array is selected and current measured for each of these cells. Standard deviation of current for each cell in the first subset of cells is determined with respect to current of a reference cell. Standard deviation of local variation can be determined using the determined standard deviation of current for one or more cells in the first subset. Standard deviations of variation induced by, for example, poly density gradient effects, in the x and/or y direction of the array can then be determined and current mismatch for any cell in the array determined therefrom.
    Type: Application
    Filed: January 28, 2013
    Publication date: July 31, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Amit KUNDU, Jaw-Juinn HORNG, Yung-Chow PENG, Shih-Cheng YANG, Chung-Kai LIN
  • Patent number: 8793636
    Abstract: Mechanisms are provided for performing placement of cells in a design of a semiconductor device. An initial design of the semiconductor device is generated, the initial design comprising a first placement of cells. A preferred direction of placement associated with the cells is determined. The preferred direction is a direction along which spreading of the cells is preferred. A second design of the semiconductor device is generated by modifying the first placement of the cells to generate a second placement of cells, different from the first placement cells, based on the preferred direction of placement associated with the cells.
    Type: Grant
    Filed: April 14, 2011
    Date of Patent: July 29, 2014
    Assignee: International Business Machines Corporation
    Inventors: Charles J. Alpert, Myung-Chul Kim, Zhuo Li, Natarajan Viswanathan, Samuel I. Ward
  • Patent number: 8793632
    Abstract: In one or more embodiments, one or more methods, processes, and/or systems described can determine stress failures in interconnect segments of integrated circuit designs and correct those failure via modifying the interconnect segments of the integrated circuit designs with one or more additions to the interconnect segments of the integrated circuit designs. Potentials can be received from a simulation, and one or more failures of an interconnect segment can be determined via the potentials from the simulation. For example, a failure can be determined via a comparison with a potential from the simulation and a critical potential. An interconnect segment can be modified with a stub such that a comparison with a potential from the simulation and a critical potential to provide a non-failing, modified interconnect segment.
    Type: Grant
    Filed: August 12, 2013
    Date of Patent: July 29, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Ertugrul Demircan, Mehul D. Shroff
  • Patent number: 8793629
    Abstract: A method for designing a system to be implemented on a field programmable gate array (FPGA) includes identifying an adder from an intermediate representation of the system. Components on the target device are designated to support and implement the adder as a partitioned adder having a plurality of sub-adders each registering an intermediate result.
    Type: Grant
    Filed: January 10, 2011
    Date of Patent: July 29, 2014
    Assignee: Altera Corporation
    Inventor: Steven Perry
  • Patent number: 8788995
    Abstract: A system and method are provided for pessimism reduction of a timing database provided for optimization of a circuit design. Pessimism is reduced through generation of a hybrid graph-based static timing analysis (GBA) and path-based static timing analysis (PBA STA) database. PBA is selectively performed on the most critical GBA identified timing violations with the goal of reducing erroneous pessimism in operational timing characteristics passed on to the physical implementation corrective optimizer module to thereby reduce unnecessary fixing and transformations upon the circuit design to correspondingly reduce design time, temporary storage space, needed processing power for timing closure and to result in a finished operable and tangible circuit device with reduced area, power requirements, and decreased cost.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: July 22, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventors: Naresh Kumar, Prashant Sethia, Amit Dhuria, Krishna Belkhale
  • Patent number: 8788988
    Abstract: Techniques and structures relating to consistency management for fabrication data are disclosed. A plurality of data sources may contain different values for a variety of design parameters usable by electronic circuit design tools to physically lay out at least a portion of an integrated circuit (such as minimum spacing rules, etc.). By seeking to detect different parameter values and/or parameter values that fail to meet a confidence threshold, potential errors may be uncovered at an earlier stage of the design process. Error detection may occur in response to a request to a database, or as part of a consistency check. Different file formats for different design tools may be imported into a central database to facilitate system operation, and an application programming interface may be used to acquire or calculate data values and perform checks in some embodiments.
    Type: Grant
    Filed: October 31, 2011
    Date of Patent: July 22, 2014
    Assignee: Apple Inc.
    Inventors: Jeffrey B. Reed, Brian J. Nalle, Michael A. Dukes
  • Publication number: 20140197520
    Abstract: In a particular embodiment, a method includes removing a first portion of an optical planarization layer using a lithographic mask to expose a region of the optical planarization layer. A resistive layer is formed at least partially within the region. The method further includes removing at least a second portion of the optical planarization layer and at least a third portion of the resistive layer to form a resistor.
    Type: Application
    Filed: January 17, 2013
    Publication date: July 17, 2014
    Applicant: QUALCOMM INCORPORATED
    Inventors: Jihong Choi, John J. Zhu, Bin Yang, Giridhar Nallapati, PR Chidambaram
  • Patent number: 8782584
    Abstract: A computer implemented method for reworking a plurality of cells initially placed in a circuit design. An expander allocates cells to tiles. The expander determines a high detailed routing cost tile class, wherein the high detailed routing cost tile class is a class of tiles that has high detailed routing costs. The expander selects a cell within a tile of the high detailed routing cost tile class to form a selected cell in a selected tile. The expander applies multiple techniques to reposition these cells at new locations to improve the detailed routability. The expander can place an expanded bounding box around the selected cell, wherein the bounding box extends to at least one tile adjacent the selected tile, and repositions the selected cell within the bounding box to form a modified design to improve the detailed routability. The expander may also inflate and legalize those cells.
    Type: Grant
    Filed: May 24, 2013
    Date of Patent: July 15, 2014
    Assignee: International Business Machines Corporation
    Inventors: Charles J Alpert, Zhuo D Li, Gi-Joon Nam, Shyam Ramji, Lakshmi N Reddy, Jarrod A Roy, Taraneh E Taghavi, Paul G Villarrubia, Natarajan Viswanathan
  • Patent number: 8782579
    Abstract: A connection verification method is disclosed. A computer verifies a connection between a first node and a second node by starting from the first node in a designed integrated circuit, based on connection information stored in a storage part. The computer detects whether a module connected to the second node is a predetermined module predetermined module having a logic condition therein, based on connection relationship logic information stored in the storage part. The computer conducts a connection verification starting the module to verify a connection between the module and a third node when the module is the predetermined module.
    Type: Grant
    Filed: October 25, 2011
    Date of Patent: July 15, 2014
    Assignees: Fujitsu Limited, Fujitsu Semiconductor Limited
    Inventors: Satoshi Matsubara, Akira Kurokawa
  • Patent number: 8782577
    Abstract: Disclosed are a method, system, and computer program product for providing customizable information in designing electronic circuits with electrical awareness. The method or the system displays a portion of a physical design of an electronic circuit in a first display area. The method or the system receives or identifies a user's or a system's manipulation of the portion of the physical design of the electronic circuit. The method or the system then determines and displays an in situ response to the manipulation in the first display area. The method or the system may further display, in the first display area or in another display area, result(s) relating to the physical data of a component, electrical parasitic(s) associated with the physical data, electrical characteristic(s) associated with the physical data or the electrical characteristic(s), or other element(s) of the physical design that is impacted by the manipulation.
    Type: Grant
    Filed: December 30, 2010
    Date of Patent: July 15, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventors: Ed Fischer, David White, Michael McSherry, Bruce Yanagida, Vance Kenzle
  • Patent number: 8779553
    Abstract: A method of circuit design involving an integrated circuit (IC) having an interposer can include identifying an active resource implemented within the IC within a region of the interposer exposed to an amount of stress that exceeds a normalized amount of stress on the interposer and selectively assigning an element of the circuit design to be implemented within the IC to the active resource according to a stress-aware analysis of the circuit design as implemented within the IC.
    Type: Grant
    Filed: June 16, 2011
    Date of Patent: July 15, 2014
    Assignee: Xilinx, Inc.
    Inventor: Arifur Rahman
  • Patent number: 8776006
    Abstract: Aspects of the invention provide for a method of delay defect testing in integrated circuits. In one embodiment, the method includes: generating at least one test pattern based on a transition fault model type; evaluating a dynamic voltage drop for the at least one pattern during a capture cycle and generating a voltage drop value for the at least one test pattern; performing a static timing analysis, using the voltage drop value for the at least one test pattern; evaluating a plurality of paths in the at least one pattern; and masking each path that fails to meet a timing requirement.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: July 8, 2014
    Assignee: International Business Machines Corporation
    Inventors: Raghu G. Gopalakrishnasetty, Thamaraiselvan Subramani, Balaji Upputuri
  • Patent number: 8775991
    Abstract: A memory module has an array of connections. The array of connections is arranged in rows and columns such that there are first and second outer columns. Connections in the first and second outer columns can be interchanged to optimize double-side module placement on a substrate. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: May 7, 2013
    Date of Patent: July 8, 2014
    Assignee: Intel Corporation
    Inventors: Michael W. Leddige, Kuljit Singh Bains, John Thomas Sprietsma
  • Patent number: 8776000
    Abstract: A method of implementing timing ECO in a circuit includes the steps of performing a static timing analysis on the circuit so as to determine at least one timing violating path of the circuit, decomposing the timing violating path into at least one violating path segment, determining a smooth curve from each timing violating path and determining a plurality of reference points along the smooth curve, computing a fixability parameter of each gate on the violating path segment, extracting at least one gate according to the fixability parameters, and selecting one spare cell and disposing the selected spare cell on the violating path segment.
    Type: Grant
    Filed: November 7, 2012
    Date of Patent: July 8, 2014
    Assignee: National Chiao Tung University
    Inventors: Hua-Yu Chang, Hui-Ru Jiang, Yao-Wen Chang
  • Patent number: 8775988
    Abstract: A method for performing a parallel static timing analysis in which multiple processes independently update a timing graph without requiring communication through a central coordinator module. Local processing queues are used to reduce locking overhead without causing excessive load imbalance. A parallel analysis is conducted on a circuit design represented by a timing graph formed by a plurality of interconnected nodes, the method including: using a computer for creating a shared work queue of ready to process independent nodes; assigning the independent nodes from the work queue to at least two parallel computation processes, simultaneously performing node analysis computations thereof; and modifying the circuit design by updating values of the processed independent nodes obtained from the node analysis, the at least two parallel computation processes independently updating the shared work queue to process a new plurality of independent nodes.
    Type: Grant
    Filed: June 1, 2011
    Date of Patent: July 8, 2014
    Assignee: International Business Machines Corporation
    Inventors: Mark A. Lavin, David J. Hathaway, Kerim Kalafala, Jeffrey S. Piaget, Chandramouli Visweswariah
  • Patent number: 8775984
    Abstract: Phase-coherent differential structures contain a phase-coherent transformer having two pairs of phase-coherent coupled differential inductors.
    Type: Grant
    Filed: December 28, 2010
    Date of Patent: July 8, 2014
    Assignee: The Regents of the University of California
    Inventors: Mau-Chung Frank Chang, Daquan Huang
  • Publication number: 20140185981
    Abstract: A method of forming an integrated photonic semiconductor structure having a photonic device and adjacent CMOS devices may include depositing a first silicon nitride layer over the adjacent CMOS devices and depositing an oxide layer over the first silicon nitride layer, wherein the oxide layer conformally covers the first silicon nitride layer and the underlying adjacent CMOS devices to form a substantially planarized surface over the adjacent CMOS devices. A second silicon nitride layer is then deposited over the oxide layer and a region corresponding to forming the photonic device. A germanium layer is deposited over the oxide layer and the region corresponding to forming the photonic device. The germanium layer deposited over the adjacent CMOS devices is etched to form a germanium active layer within the photonic region, whereby the oxide layer and the second silicon nitride layer protect the adjacent CMOS devices during the etching of the germanium.
    Type: Application
    Filed: January 2, 2013
    Publication date: July 3, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Solomon Assefa, Marwan H. Khater, Edward W. Kiewra, Steven M. Shank
  • Patent number: 8769466
    Abstract: The disclosed method includes: identifying a first reference component from among first components defined in a first constraint condition that is a reference designated from among constraint conditions regarding a position relationship between plural components on a printed circuit board; identifying a second reference component from among second components defined in a second constraint condition that is to be compared with the first constraint condition and included in the constraint conditions; and identifying a fourth component that is a component other than the second reference component among the second components and has a correspondence with a third component, based on position relationships with the third component and an attribute of the third component, wherein the third component is a component other than the first reference component among the first components.
    Type: Grant
    Filed: March 23, 2012
    Date of Patent: July 1, 2014
    Assignee: Fujitsu Limited
    Inventor: Yuji Baba
  • Patent number: 8769455
    Abstract: Various embodiments use connectivity information or model(s), design attribute(s), and system intelligence layer(s) to make lower blocks at lower levels aware of changes made in other blocks at same or different levels to implement the design at different levels synchronously. Budgeting is performed for the design to distribute budgets to respective blocks in the design. The various budgets may be borrowed from one or more blocks and lent to a block in order for this block to meet closure requirements such that a total number of iterations of the reassembly process, which integrates lower level blocks into top level design, may be reduced or completely eliminated. The design attribute(s) or the connectivity model(s) or information is updated upon the identification of changes to provide the latest information or data for properly closing a design.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: July 1, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventors: Sushobhit Singh, Amit Kumar, Oleg Levitsky
  • Patent number: 8769459
    Abstract: The present invention provides a high-end fault-tolerant computer system and an implementation method. The system includes N single junction prototype verification systems and M crossbar-switch interconnection router chipsets. Each crossbar-switch interconnection router chipset is used to achieve the interconnection among the N single junction prototype verification systems. Switching is not performed among all crossbar-switch interconnection router chipsets, and both M and N are positive integers greater than or equal to 2. The single junction includes: a computer board, which is 4-path tightly-coupled computer board, and a junction controller for controlling 2 paths of CPUs on the computer board. The present invention can effectively realize the global memories sharing, balance the system transmission bandwidth and delay, and solve the problem of the integration reliability of multi-path CPU system.
    Type: Grant
    Filed: March 6, 2012
    Date of Patent: July 1, 2014
    Assignee: Inspur (Beijing) Electronic Information Industry Co., Ltd.
    Inventors: Edong Wang, Leijun Hu, Rengang Li
  • Patent number: 8769457
    Abstract: After a global placement phase of physical design of an integrated circuit, a data processing system iteratively refines local placement of a plurality of modules comprising the integrated circuit within a die area based on density of the plurality of modules and separately refines local wirelength for the plurality of modules in individual subareas among a plurality of subareas of the die area. The data processing system thereafter performs detailed placement of modules in the plurality of subareas.
    Type: Grant
    Filed: June 30, 2012
    Date of Patent: July 1, 2014
    Assignee: International Business Machines Corporation
    Inventors: Charles J. Alpert, Myung-Chul Kim, Gi-Joon Nam, Shyam Ramji, Natarajan Viswanathan
  • Patent number: 8769458
    Abstract: A prototype verification system and method are provided for a high-end fault-tolerant computer. The system includes multiple single junction prototype verification systems and an interconnection router chipset. The single junction prototype verification systems are interconnected through the interconnection router chipset. Each single junction prototype verification system includes a computer board which is a four-path tightly-coupled computer board, and a chip verification board including two junction controller chipsets. Each junction controller chipset includes two field-programmable gate array (FGPA) chips which bear a logic of one junction controller together, and an interconnection board including two FGPA chips. Each FPGA chip provides a high speed interconnection port used to achieve protocol interconnection between two paths of the computer board and one of the junction controller chipsets.
    Type: Grant
    Filed: March 2, 2012
    Date of Patent: July 1, 2014
    Assignee: Inspur (Beijing) Electronic Information Industry Co., Ltd.
    Inventors: Endong Wang, Leijun Hu, Rengang Li
  • Patent number: 8769456
    Abstract: Various processes or modules described herein enable the schematic design tools to obtain physical data of a physical design and to perform one or more simulations in the schematic domain with such physical data such that the schematic design tools are made electrically aware of the physical data. Various types of data in the physical domain may be transferred to the schematic domain for the performance of one or more schematic simulations with the transferred data. The schematic designs are thus made electrically aware of such data from the physical domain and may incorporate any layout induced effects early in the schematic design stage or even at the time a schematic instance of a physical module is to be created in the schematic domain.
    Type: Grant
    Filed: October 26, 2011
    Date of Patent: July 1, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventors: Prakash Krishnan, Jeremiah Cessna, Akshat Shah, Keith Dennison
  • Publication number: 20140175550
    Abstract: Device structures, design structures, and fabrication methods for fin-type field-effect transistor integrated circuit technologies. First and second fins, which constitute electrodes of the device structure, are each comprised of a first semiconductor material. The second fin is formed adjacent to the first fin to define a gap separating the first and second fins. Positioned in the gap is a layer comprised of a second semiconductor material.
    Type: Application
    Filed: February 27, 2014
    Publication date: June 26, 2014
    Applicant: International Business Machines Corporation
    Inventors: Robert J. Gauthier, JR., Jeffrey B. Johnson, Junjun Li
  • Patent number: 8762924
    Abstract: Roughly described, a method for approximating stress-induced mobility enhancement in a channel region in an integrated circuit layout, including approximating the stress at each of a plurality of sample points in the channel, converting the stress approximation at each of the sample points to a respective mobility enhancement value, and averaging the mobility enhancement values at all the sample points. The method enables integrated circuit stress analysis that takes into account stresses contributed by multiple stress generation mechanisms, stresses having vector components other than along the length of the channel, and stress contributions (including mitigations) due to the presence of other structures in the neighborhood of the channel region under study, other than the nearest STI interfaces. The method also enables stress analysis of large layout regions and even full-chip layouts, without incurring the computation costs of a full TCAD simulation.
    Type: Grant
    Filed: July 27, 2009
    Date of Patent: June 24, 2014
    Assignee: Synopsys, Inc.
    Inventors: Victor Moroz, Dipankar Pramanik
  • Patent number: 8762927
    Abstract: Designing operation efficiency is improved by automatically transmitting and receiving circuit-related information and layout-related information required for designing each printed board between printed boards, for designing a plurality of printed boards at the same time. In an electric information processing method in a CAD system, the printed boards are designed at the same time by transmitting and receiving the circuit design information relating to the printed boards and the layout design information relating to the printed boards between the circuits and layouts relating to the printed boards.
    Type: Grant
    Filed: October 10, 2007
    Date of Patent: June 24, 2014
    Assignee: Zuken Inc.
    Inventor: Satoshi Nakamura
  • Patent number: 8762902
    Abstract: A system and method for detecting an invalid winding path in a layout design file includes generating a first reticle pattern file using a first path generation program, generating a second reticle pattern file using a second path generation program, comparing the first and second reticle patterns files to detect the invalid winding path. The invalid winding path includes one or more overlapping polygons.
    Type: Grant
    Filed: December 29, 2009
    Date of Patent: June 24, 2014
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Kuei Mei Yu
  • Patent number: 8762905
    Abstract: Methods and systems for determining a numerical delay model based on one or more discretized delay models are described. A discretized delay model is a delay model in which the delay behavior is represented using a set of discrete data points of delay behavior. A numerical delay model is a delay model that can be used by a numerical solver to optimize a cost function. In general, computing delay using a numerical delay model is significantly faster than computing delay using discretized delay models. This performance improvement is important when optimizing a design for various metrics like timing, area and leakage power, because repeated delay computations are required in circuit optimization approaches.
    Type: Grant
    Filed: April 18, 2012
    Date of Patent: June 24, 2014
    Assignee: Synopsys, Inc.
    Inventors: Mahesh A. Iyer, Amir H. Mottaez
  • Patent number: 8762900
    Abstract: A method of an integrated circuit (IC) design includes receiving an IC design layout. The IC design layout includes an IC feature with a first outer boundary and a first target points assigned to the first outer boundary. The method also includes generating a second outer boundary for the IC feature and moving all the first target points to the second outer boundary to form a modified IC design layout.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: June 24, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jaw-Jung Shin, Shy-Jay Lin, Hua-Tai Lin, Burn Jeng Lin
  • Patent number: 8762911
    Abstract: A method of designing a layout, a design system and a computer program product for a multi-finger complementary metal oxide semiconductor (CMOS) inverter including a multi-finger N-type field effect transistor (NFET) and a multi-finger P-type field effect transistor (PFET) is disclosed. The design of the layout disposes a metallization wire connecting multiple drains of each type of MOS transistor. Analysis of an electric current in each segment of the metallization wire and of a total resistance of in all segments of the metallization wire provides an optimal location where the metallization wires for NFET drains and PFET drains are connected. The optimal wire connection location provides maximum drain current for the CMOS inverter along with a low wire capacitance between the wire and the gates of NFETs and PFETs.
    Type: Grant
    Filed: May 7, 2013
    Date of Patent: June 24, 2014
    Assignee: International Business Machines Corporation
    Inventor: Ning Lu
  • Patent number: 8762910
    Abstract: A wiring design method and apparatus are provided. The wiring design method includes dividing a wiring region represented by wiring region data to generate a plurality of first division regions based on a first wiring rule and generating, when a second wiring rule different from the first wiring rule may be set in the first division region, second division regions with the second wiring rule in the first division region.
    Type: Grant
    Filed: October 15, 2009
    Date of Patent: June 24, 2014
    Assignee: Fujitsu Limited
    Inventor: Ikuo Ohtsuka
  • Patent number: 8762921
    Abstract: Apparatus for providing semiconductor device with an analysis module to receive device information, a G-function processor producing an ordered relationship representation corresponding to an optimization parameter specification, and a power cell optimizer to produce an optimization parameter from the ordered relationship representation. A method for designing a semiconductor device includes receiving an optimization target specification; receiving an optimization parameter specification corresponding to an optimization parameter; receiving the target parameter; receiving a G-function corresponding to an ordered relationship representation; optimizing the optimization parameter specification as a function of the predetermined G-function; and producing at least one optimized geometric layout parameter (GLP) by the optimizing, wherein the at least one GLP corresponds to an optimized power cell.
    Type: Grant
    Filed: December 3, 2010
    Date of Patent: June 24, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Juan Cordovez, James Victory
  • Publication number: 20140169076
    Abstract: A static random access memory (SRAM) having two or more SRAM memory cells connected with a write bit line (WBL) and a write bit line complement (WBLC) is disclosed. The SRAM may include a write driver logic coupled to the WBL and the WBLC. The write driver logic is adapted to drive a selected bit line of the WBL and the WBLC to a voltage uplevel below a first supply voltage and shut off the drive to the selected bit line when the selected bit line reaches the uplevel. The write driver logic is further adapted to drive an unselected bit line of the WBL and the WBLC to a downlevel, in conjunction with the driving of the selected bit line to the uplevel, where the downlevel is a second supply voltage lower than the first supply voltage.
    Type: Application
    Filed: December 18, 2012
    Publication date: June 19, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Derick G. Behrends, Todd A. Christensen, Travis R. Hebig, Michael Launsbach
  • Patent number: 8756538
    Abstract: A method for implementing a hardware design that includes using a computer for receiving structured data that includes a representation of a basic hardware structure and a complex hardware structure that includes the basic hardware structure, parsing the structured data and generating, based on a result of the parsing, commands of a hardware design environment.
    Type: Grant
    Filed: February 19, 2013
    Date of Patent: June 17, 2014
    Assignee: International Business Machines Corporation
    Inventors: Hans-Werner Anderson, Uwe Brandt, Markus Buehler, Katherine Eve, Thomas Kalla, Jens Noack, Monika Strohmer
  • Patent number: 8756554
    Abstract: A method comprises tracing a first and second terminal of a junction through a circuit layout to associated power supplies to determine their respective defined bias values. The method further comprises comparing the defined bias values of each terminal in order to determine, based on the comparison, whether the junction is forward biased.
    Type: Grant
    Filed: May 15, 2012
    Date of Patent: June 17, 2014
    Assignee: International Business Machines Corporation
    Inventors: Douglas W. Kemerer, Edward W. Seibert, Lijiang L. Wang
  • Patent number: 8756541
    Abstract: Systems and methods for relative ordering circuit synthesis are provided herein. One aspect provides for generating at least one circuit design via at least one processor accessible by a computing device; wherein generating at least one circuit design comprises: generating at least one relative order structure based on at least one circuit design layout, the at least one relative order structure comprising at least one placement constraint associated with at least one circuit element; placing the at least one circuit element associated with the at least one placement constraint within a circuit design according to the at least one placement constraint; and placing circuit elements not associated with the at least one placement constraint within the circuit design. Other embodiments and aspects are also described herein.
    Type: Grant
    Filed: March 27, 2012
    Date of Patent: June 17, 2014
    Assignee: International Business Machines Corporation
    Inventors: Minsik Cho, Ruchir Puri, Haoxing Ren, Xiaoping Tang, Hua Xiang, Matthew Mantell Ziegler
  • Patent number: 8756549
    Abstract: Disclosed are embodiments of an integrated circuit chip designed for reliability at low ambient temperatures. The chip substrate can be divided into zones, including at least one temperature-sensitive zone (TSZ) that contains one or more temperature-sensitive circuits. Temperature sensor(s) can be positioned in the semiconductor substrate adjacent to the TSZ. Thermal radiator(s) can be embedded in a metal wiring layer and aligned above the TSZ. The temperature sensor(s) can be operatively connected to the thermal radiator(s) and can trigger operation of the thermal radiator(s) when the temperature in the TSZ is below a predetermined threshold temperature. Additionally, an on-chip power control system can be operatively connected to the thermal radiator(s) so that operation of the thermal radiator(s) is only triggered when a circuit within the TSZ is about to be powered up. Also disclosed are associated embodiments of a system and method for designing such an integrated circuit chip.
    Type: Grant
    Filed: January 5, 2011
    Date of Patent: June 17, 2014
    Assignee: International Business Machines Corporation
    Inventors: Richard S. Graf, Keishi Okamoto, Faraydon Pakbaz, Jack R. Smith, Sebastian T. Ventrone
  • Patent number: 8756545
    Abstract: An apparatus calculates a delay time of nets within a circuit included in design data by a processing unit. The processing unit performs a process that includes selecting a first calculation to calculate the delay time of a net when the net satisfies a first condition, when the first calculation is not selected by the selecting, selecting the first or second calculation to calculate the delay time of the net, depending on whether the net satisfies a second condition, and calculating the delay time of the net by the first or second calculation selected by the selecting.
    Type: Grant
    Filed: July 2, 2012
    Date of Patent: June 17, 2014
    Assignee: Fujitsu Limited
    Inventor: Hiroyuki Sugiyama
  • Patent number: 8751999
    Abstract: In one embodiment, creating a layout for a Printed Circuit Board (PCB) by creating n boundary lines at n locations, respectively, on the PCB and placing n sets of electronic components on the n boundary lines, respectively; and iteratively adjusting and evaluating the layout of the PCB until a set of layout requirements for the PCB has been satisfied.
    Type: Grant
    Filed: July 5, 2011
    Date of Patent: June 10, 2014
    Assignee: Fujitsu Limited
    Inventor: Toshiyuki Shibuya
  • Patent number: 8751976
    Abstract: The present disclosure provides one embodiment of an integrated circuit (IC) method. The method includes building a pattern bank including a pattern having an area of interest. The method further includes recognizing that the pattern of the pattern bank corresponds to a pattern of an IC design layout. The method further includes identifying an area of interest of the pattern of the IC design layout that corresponds to the area of interest of the pattern of the pattern bank. The method further includes performing pattern recognition dissection on the area of interest of the pattern of the IC design layout to dissect the area of interest of the pattern of the IC design layout into a plurality of segments. The method further includes after performing pattern recognition dissection, producing a modified IC design layout.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: June 10, 2014
    Inventors: Cheng-Lung Tsai, Jui-Hsuan Feng, Sheng-Wen Lin, Wen-Li Cheng, Wen-Chun Huang, Ru-Gun Liu
  • Patent number: 8751974
    Abstract: The invention provides systems and methods for layout decomposition to produce exposure layouts that can be used to perform double patterning lithography (DPL). Preferred embodiment methods of the invention are executed by a computer and provide alternate methods for layout decomposition for double patterning lithography (DPL) using integer linear programming (ILP) formulations. Embodiments of the invention meet a key optimization goals, which is to reduce the total cost of layout decomposition, considering the abovementioned aspects that contribute to cost of prior conventional DPL techniques. Embodiments of the invention provide integer linear programming (ILP), phase conflict detection (PCD) and node election bipartization (NBD) formulations for the optimization of DPL layout decomposition, with a process-aware cost function that avoids small jogging line-ends, and maximizes overlap at dividing points of polygons. The cost function can also make preferential splits at landing pads, junctions and long runs.
    Type: Grant
    Filed: February 13, 2013
    Date of Patent: June 10, 2014
    Assignee: The Regents of the University of California
    Inventors: Andrew B. Kahng, Hailong Yao
  • Patent number: 8751998
    Abstract: Disclosed is a method of simulating partial reconfiguration of a programmable logic device (PLD). A wrapper module is incorporated into a logic description that may be implemented in a PLD. The wrapper module represents a first logic design. In response to receiving a parameter, the wrapper module changes to represent a second logic design. According to various embodiments, the logic description is a simulatable source file. The simulatable source file is a source file that is used by a simulation program to simulate partial reconfiguration of the logic design. The wrapper module of the simulatable source file receives a run-time parameter. In various embodiments, the logic description is a synthesizable source file. The synthesizable source file is a source file that is used by a synthesis tool to compile the source file into hardware. The wrapper module of the synthesizable source receives a compile-time parameter.
    Type: Grant
    Filed: February 8, 2012
    Date of Patent: June 10, 2014
    Assignee: Altera Corporation
    Inventors: David W. Mendel, Marwan A. Khalaf, Renxin Xia
  • Patent number: 8751987
    Abstract: A method of resistor matching in analog integrated circuit layout is disclosed. Shapes of mismatching resistor blocks are analyzed to obtain geometrical information for deforming the mismatching resistor blocks. The mismatching resistor blocks are deformed into centrosymmetrical blocks according to the obtained geometrical information, each mismatching resistor block being decomposed to a plurality of unit-resistors. The unit-resistors are placed into matching resistor blocks to return a resulting layout with improved matching quality by reducing centroid offset between a centroid of the unit-resistors and a centroid of the matching resistor block.
    Type: Grant
    Filed: July 12, 2012
    Date of Patent: June 10, 2014
    Assignee: Oryx Holdings Pty Ltd.
    Inventors: Tsung-Yi Ho, Sheng-Jhih Jiang, Chan-Liang Wu
  • Patent number: 8751986
    Abstract: Methods and apparatuses are disclosed that automatically generate relative placement rules. Constructs at the register transfer language-level result in relative placement rules specified at the register transfer language-level.
    Type: Grant
    Filed: August 5, 2011
    Date of Patent: June 10, 2014
    Assignee: Synopsys, Inc.
    Inventors: Anand Arunachalam, Mustafa Kamal, Xinwei Zheng, Mohammad Khan, Xiaoyan Yang, Dongxiang Wu
  • Patent number: 8745562
    Abstract: A design method of on-board wiring for a designed circuit includes determining a severity as a crosstalk prevention index for a pair of wires based on a generated noise level of a damaging side wire and a permissible noise level of a damaged side wire. The pair of wires is then assigned a severity class (SC) based on the severity determined. The SC is a pre-defined value range(s) for severity classification. Based on a preset SC specific permissible value list, one or more by-design permissible values belonging to the SC is generated for a design element of the pair of wires. A layout of the pair of wires on a board is constructed based on the by-design permissible value.
    Type: Grant
    Filed: December 5, 2012
    Date of Patent: June 3, 2014
    Assignee: DENSO CORPORATION
    Inventors: Masashi Inagaki, Kouji Ichikawa, Makoto Tanaka, Hideki Kashiwagi
  • Patent number: 8739100
    Abstract: A technique for implementing an clock tree distribution network having a clock buffer and a plurality of LC tanks that each take into consideration local capacitance distributions and conductor resistances. An AC-based sizing formulation is applied to the buffer and to the LC tanks so as to reduce the total buffer area. The technique is iterative and can be fully automated while also reducing clock distribution power consumption.
    Type: Grant
    Filed: June 23, 2012
    Date of Patent: May 27, 2014
    Assignee: The Regents of the University of California
    Inventor: Matthew Guthaus