Abstract: Disclosed is a light emitting device having a plurality of light emitting cells and a package having the same mounted thereon. The light emitting device includes a plurality of light emitting cells which are formed on a substrate and each of which has an N-type semiconductor layer and a P-type semiconductor layer located on a portion of the N-type semiconductor layer. The plurality of light emitting cells are bonded to a submount substrate. Accordingly, heat generated from the light emitting cells can be easily dissipated, so that a thermal load on the light emitting device can be reduced. Meanwhile, since the plurality of light emitting cells are electrically connected using connection electrodes or electrode layers formed on the submount substrate, it is possible to provide light emitting cell arrays connected to each other in series.

Abstract: Disclosed herein is an article comprising a substrate; an interlayer comprising aluminum nitride, gallium nitride, boron nitride, indium nitride or a solid solution of aluminum nitride, gallium nitride, boron nitride and/or indium nitride; the interlayer being directly disposed upon the substrate and in contact with the substrate; where the interlayer comprises a columnar film and/or nanorods and/or nanotubes; and a group-III nitride layer disposed upon the interlayer; where the group-III nitride layer completely covers a surface of the interlayer that is opposed to a surface in contact with the substrate; the group-III nitride layer being free from cracks.

Abstract: The invention provides an apparatus and method for generating quantum-correlated and/or polarization-entangled photon pairs with unequal wavelengths. The photon pairs generated collinearly with respect to the pump light via a nonlinear process in a nonlinear optical medium are collected into a single mode fiber and split using a dichroic device. The wavelengths of photons constituting a pair are selected such that, first, their efficient propagation in the same single mode optical fiber, and second, their efficient splitting with high switching ratio, is possible. A detected rate ˜105-106 pairs/s and >98% quantum interference visibility of polarization entanglement is observed. This source, given its performance, robustness and minimum alignment requirements is ideal for quantum communication schemes, in particular for entanglement-based quantum cryptography.

Abstract: A semiconductor structure including nanotubes forming an electrical connection between electrodes is disclosed. The semiconductor structure may include an open volume defined by a lower surface of an electrically insulative material and sidewalls of at least a portion of each of a dielectric material and opposing electrodes. The nanotubes may extend between the opposing electrodes, forming a physical and electrical connection therebetween. The nanotubes may be encapsulated within the open volume in the semiconductor structure. A semiconductor structure including nanotubes forming an electrical connection between source and drain regions is also disclosed. The semiconductor structure may include at least one semiconducting carbon nanotube electrically connected to a source and a drain, a dielectric material disposed over the at least one semiconducting carbon nanotube and a gate dielectric overlying a portion of the dielectric material. Methods of forming the semiconductor structures are also disclosed.

Abstract: An electronic device using quantum dots, which comprises a ferromagnetic micro magnet and performs individual ESR control on each multi-quantum bit in a power saving way. The electronic device comprising the ferromagnetic micro magnet (10) disposed in the vicinity of the quantum dots (8, 9) of a plurality of aligned semiconductor quantum dots, wherein a strong magnetic field is applied so as to induce electron spin resonance (ESR), and the layout of the ferromagnetic micro magnet (10) is changed, thereby controlling the resonance frequency of the quantum dots (8, 9). Under the condition where the resonance frequency of each quantum dot (8, 9) is controlled, swapping of the electron spins in the quantum dots (8, 9) is performed, thereby creating a quantum bit (QUBIT) required for quantum calculation.

Abstract: A method of generating a photoluminescence map for an indium gallium nitride (InGaN) well can include presenting data on a pixel by pixel basis. The data can be generated as a function of emission wavelength, line width of emission, polarization of emission, and intensity of emission. The data can also be generated as a function of excitation polarization and polarization angle orientation with respect to film crystalline axes of the InGaN well. The data can also be generated as a function of multiple wavelengths of light to generate the photoluminescence map. The photoluminescence maps can be correlated to device internal quantum efficiency as measured in test devices. The resulting correlation maps can serve as line monitors of indium rich InGaN wafers used for green LEDs.

Abstract: Nanowire-based opto-electronic devices including nanowire lasers, photodetectors and semiconductor optical amplifiers are disclosed. The devices include nanowires grown from single crystal and/or non-single surfaces. The semiconductor optical amplifiers include nanowire arrays that act as ballast lasers to amplify a signal carried by a signal waveguide. Embodiments of the nanowire lasers and photodetectors include horizontal and vertical nanowires that can provide different polarizations.

Abstract: A method for fabricating AlxGa1-xN-cladding-free nonpolar III-nitride based laser diodes or light emitting diodes. Due to the absence of polarization fields in the nonpolar crystal planes, these nonpolar devices have thick quantum wells that function as an optical waveguide to effectively confine the optical mode to the active region and eliminate the need for Al-containing waveguide cladding layers.

Abstract: A plurality of core-shell semiconductor nanowires each being fixed to a support includes II-VI materials for both the cores and the shells. Each nanowire terminates in a free end and a metal alloy nanoparticle is fixed to each nanowire at its free end.

Abstract: A method of etching active quantum nanostructures provides the step of laterally etching of an intermediate active quantum nanostructure layer interposed between cladding layers. The lateral etching can be carried out on at least one side of the intermediate active quantum nanostructure layer selectively, with respect to the cladding layers to define at least one lateral recess or spacing in the intermediate active quantum nanostructure layer and respective lateral protrusions of cladding layers protruding with respect to the intermediate active quantum nanostructure layer. This method can be applied to create devices including active quantum nanostructures such as, for example, three-dimensional photonic crystals, a photonic crystal double-slab and a photonic crystal laser.

Abstract: Provided are a high-quality non-polar/semi-polar semiconductor device with reduced defect density and improved internal quantum efficiency and light extraction efficiency, and a manufacturing method thereof. The manufacturing method is a method for manufacturing a semiconductor device, in which a template layer and a semiconductor device structure are formed on a sapphire substrate having a crystal plane for growing a non-polar or semi-polar nitride semiconductor layer. The sapphire substrate is etched to form uneven patterns, and the template layer including a nitride semiconductor layer and a GaN layer is formed on the sapphire substrate in which the uneven patterns are formed.

Abstract: A photonic structure includes a plurality of annealed, substantially smooth-surfaced ellipsoids arranged in a matrix. Additionally, a method of producing a photonic structure is provided. The method includes providing a semiconductor material, providing an etch mask comprising a two-dimensional hole array, and disposing the etch mask on at least one surface of the semiconductor material. The semiconductor material is then etched through the hole array of the etch mask to produce holes in the semiconductor material and thereafter applying a passivation layer to surfaces of the holes. Additionally, the method includes repeating the etching and passivation-layer application to produce a photonic crystal structure that contains ellipsoids within the semiconductor material and annealing the photonic crystal structure to smooth the surfaces of the ellipsoids.

Abstract: Methods for preparing one or more conductive nanostructures are provided. In accordance with one embodiment, a method for preparing one or more conductive nanostructures may include providing a composite of nanoparticles and block copolymer including one or more first microdomains and one or more second microdomains, where conductive nanoparticles are selectively distributed in the one or more first microdomains, removing the first microdomains while leaving the conductive nanoparticles in the composite, forming one or more conductive nanostructures on the conductive nanoparticles, and removing the second microdomains.

Abstract: Disclosed are core/shell type semiconductor nanoparticles exhibiting a sufficient emission intensity without causing a blink phenomenon (blinking). The core/shell-type semiconductor nanoparticles have an average particle size of from 2 to 50 nm and comprise an intermediate layer between a core portion and a shell portion, wherein band gap widths of bulk crystals which have the same compositions as those of the core portion, the intermediate portion and the shell portion, respectively, are in the order of: core portion<shell portion<intermediate layer.

Abstract: Provided are a photodiode array and its manufacturing method, which maintain the crystalline quality of an absorption layer formed on a group III-V semiconductor substrate to obtain excellent characteristics, and which improve the crystallinity at the surface of a window layer; an epitaxial wafer used for manufacturing the photodiode array; and a method for manufacturing the epitaxial wafer. A method for manufacturing a photodiode array 1 having a plurality of absorption regions 21, includes the steps of: growing an absorption layer 7 on an n-type InP substrate 3; growing an InP window layer on the absorption layer 7; and diffusing a p-type impurity in regions, in the window layer 11, corresponding to the plurality of absorption regions 21. The window layer 11 is grown by MOVPE using only metal-organic sources, at a growth temperature equal to or lower than that of the absorption layer 7.

Abstract: A field emitter array structure is provided. The field emitter array structure includes a plurality of vertical un-gated transistor structures formed on a semiconductor substrate. The semiconductor substrate includes a plurality of vertical pillar structures to define said un-gated transistor structures. A plurality of emitter structures are formed on said vertical un-gated transistor structures. Each of said emitter structures is positioned in a ballasting fashion on one of said vertical un-gated transistor structures so as to allow said vertical ungated transistor structure to effectively provide high dynamic resistance with large saturation currents.

Abstract: A quantum well transistor has a germanium quantum well channel region. A silicon-containing etch stop layer provides easy placement of a gate dielectric close to the channel. A group III-V barrier layer adds strain to the channel. Graded silicon germanium layers above and below the channel region improve performance. Multiple gate dielectric materials allow use of a high-k value gate dielectric.

Abstract: A nitride semiconductor light emitting device comprises a first nitride semiconductor layer, an active layer of a single or multiple quantum well structure formed on the first nitride semiconductor layer and including an InGaN well layer and a multilayer barrier layer, and a second nitride semiconductor layer formed on the active layer. A fabrication method of a nitride semiconductor light emitting device comprises: forming a buffer layer on a substrate, forming a GaN layer on the buffer layer, forming a first electrode layer on the GaN layer, forming an InxGa1?xN layer on the first electrode layer, forming on the first InxGa1?xN layer an active layer including an InGaN well layer and a multilayer barrier layer for emitting light, forming a p-GaN layer on the active layer, and forming a second electrode layer on the p-GaN layer.

Abstract: Disclosed herein is a nano device, including: a carbon layer including one-layered graphene having a honeycombed planar structure in which carbon atoms are connected with each other and two or more-layered monocrystalline graphite; and one or more vertically-grown nanostructures formed on the carbon layer. This nano device can be used to manufacture an integrated circuit in which various devices including a graphene electronic device and a photonic device are connected with each other, and is a high-purity and high-quality nano device having a small amount of impurities because a metal catalyst is not used.

Abstract: A method for forming non-polar (Al,B,In,Ga)N quantum well and heterostructure materials and devices. Non-polar (11 20) a-plane GaN layers are grown on an r-plane (1 102) sapphire substrate using MOCVD. These non-polar (11 20) a-plane GaN layers comprise templates for producing non-polar (Al,B,In,Ga)N quantum well and heterostructure materials and devices.

Abstract: An optical device capable of emitting polarized light includes a light emitting means, two multi-layer optical films disposed above and below the light emitting means and two metal layers. The two metal layers cover the two multi-layer optical layers from the upper and lower sides respectively. Each of the two multi-layer optical films includes at least two films made from materials of different refractive indexes that are stacked in a staggered manner. The optical film formed by the multi-layer optical films and metal layers provides greater reflectance to S-polarized light (TE) and higher absorption to P-polarized light. Light generated by the light emitting means emits diagonally to the optical films and is reflected several times thereof to form S-polarized light (TE) to emit sideward.

Abstract: An electrical device includes a charge carrier transport layer formed using a ternary semiconducting compound having a stoichiometry of 1:1:1 and an element combination selected from the set of I-II-V, I-III-IV, II-II-IV, and I-I-VI; or having a stoichiometry of 3:1:2 and an element combination selected from the set of I-III-V; or having a stoichiometry of 2:1:1 and an element combination selected from the set of I-II-IV. In some embodiments, the charge carrier transport layer is used as the radiation absorption layer for a photovoltaic cell, or a light emitting layer of a light emitting device. Other devices, such as laser diode, a photodetection device, an optical modulator, a transparent electrode and a window layer, can also be formed using the ternary semiconducting compound as the charge carrier transport.

Abstract: A gain medium and an interband cascade laser, having the gain medium are presented. The gain medium can have one or both of the following features: (1) the thicknesses of the one or more hole quantum wells in the hole injector region are reduced commensurate with the thickness of the active hole quantum well in the active quantum well region, so as to place the valence band maximum in the hole injector region at least about 100 meV lower than the valence band maximum in the active hole quantum well; and (2) the thickness of the last well of the electron injector region is between 85 and 110% of the thickness of the first active electron quantum well in the active gain region of the next stage of the medium. A laser incorporating a gain medium in accordance with the present invention can emit in the mid-IR range from about 2.5 to 8 ?m at high temperatures with room-temperature continuous wave operation to wavelengths of at least 4.

Abstract: A CMOS device includes a PMOS transistor with a first quantum well structure and an NMOS device with a second quantum well structure. The PMOS and NMOS transistors are formed on a substrate.

Abstract: Electro-optical components are disclosed having intersubband transitions by quantum confinement between two Group III nitride elements, typically by means of GaN/AlN. Related devices or systems are also disclosed including such components, as well as to a method for manufacturing such a component. Such a component includes at least one active area that includes at least two so-called outer barrier layers surrounding one or more N-doped quantum well structures, and said quantum well structure(s) are each surrounded by two barrier areas that are unintentionally doped at a thickness of at least five monoatomic layers.

Abstract: The invention relates to a process for producing a p-n junction in a nanostructure, in which the nanostructure has one or more nanoconstituents made of a semiconductor material with a single type of doping having one conductivity type, characterized in that it includes a step consisting in forming a dielectric element (3, 32, . . . , 3n) embedding the nanostructure over a height h, the dielectric element generating a surface potential capable of inverting the conductivity type over a defined width W of the nanoconstituents(s) thus embedded over the height h.

Abstract: In the production of optical devices or the like utilizing an intersubband transition of a coupled quantum well, a quantum well structure having strong coupling is provided. In addition, a coupled well structure of excellent productivity capable of avoiding thinning of coupling barrier layer for strengthening the coupling is provided. In the semiconductor coupled well structure of the present invention, a coupled quantum well structure disposed on the semiconductor single crystal substrate includes a coupling barrier layer 1a disposed between two or more quantum well layers 2a and 2b, wherein the coupling barrier layer 1a has an energy barrier that is smaller than an excitation level (E4 and E3) and is larger than a ground level (E2 and E1).

Abstract: A semiconductor light emitting element includes a substrate 11 having a defect concentrated region 11a which has a crystal defect density higher than in the other region. On the substrate 11, a semiconductor layer 12 is formed. On the defect concentrated region 11a, a first electrode 13 is formed. On the semiconductor layer 12, a second electrode 14 is formed.

Abstract: Certain embodiments provide a semiconductor light emitting device including: a first metal layer; a stack film including a p-type nitride semiconductor layer, an active layer, and an n-type nitride semiconductor layer; an n-electrode; a second metal layer; and a protection film protecting an outer circumferential region of the upper face of the n-type nitride semiconductor layer, side faces of the stack film, a region of an upper face of the second metal layer other than a region in contact with the p-type nitride semiconductor layer, and a region of an upper face of the first metal layer other than a region in contact with the second metal layer. Concavities and convexities are formed in a region of the upper face of the n-type nitride semiconductor layer, the region being outside the region in which the n-electrode is provided and being outside the regions covered with the protection film.

Abstract: A single crystalline silicon carbide layer can be grown on a single crystalline sapphire substrate. Subsequently, a graphene layer can be formed by conversion of a surface layer of the single crystalline silicon layer during an anneal at an elevated temperature in an ultrahigh vacuum environment. Alternately, a graphene layer can be deposited on an exposed surface of the single crystalline silicon carbide layer. A graphene layer can also be formed directly on a surface of a sapphire substrate or directly on a surface of a silicon carbide substrate. Still alternately, a graphene layer can be formed on a silicon carbide layer on a semiconductor substrate. The commercial availability of sapphire substrates and semiconductor substrates with a diameter of six inches or more allows formation of a graphene layer on a commercially scalable substrate for low cost manufacturing of devices employing a graphene layer.

Abstract: A non-degenerate polarization-entangled photon pair generation device (1) that efficiently and easily generates non-degenerate polarization-entangled photon pairs includes: a quantum-entangled photon pair generator (2) including a single crystal in which periodically poled structures (3a, 3b) having different periods are formed; and a light radiating unit (4) for entering light into the quantum-entangled photon pair generator (2) such that the light passes through the periodically poled structure (3a) and then through the periodically poled structure (3b).

Abstract: Provided is a method for fabricating a light emitting device. The method for fabricating the light emitting device includes forming a buffer layer including a compound semiconductor in which a rare-earth element is doped on a substrate, forming a light emitting structure including a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer, which are successively stacked on the buffer layer, forming a first electrode layer on the light emitting structure, removing the substrate, and forming a second electrode layer under the light emitting structure.

Abstract: A method for forming optical devices includes providing a gallium nitride substrate having a crystalline surface region and a backside region. The backside is subjected to a laser scribing process to form scribe regions. Metal contacts overly the scribe regions.

Abstract: A three-dimensional polycrystalline semiconductor material provides a major ingredient forming individual crystalline grains having a nominal maximum grain diameter less than or equal to 50 nm, and a minor ingredient forming boundaries between the individual crystalline grains.

Abstract: A semiconductor graphene is used for a channel layer, and a metal graphene is used for electrode layers for a source, a drain, and a gate which serve as interconnections as well. An oxide is used for a gate insulating layer. The channel layer and the electrode layers are located on the same plane.

Abstract: An optoelectronic device is disclosed which includes a quantum dot layer including plurality of quantum dots which do not have capping layers. This optoelectronic device may be a quantum dot light-emitting device, which includes (1) a substrate which is transparent or translucent, (2) an anode electrical conducting layer which is transparent or translucent, and is located adjacent to the substrate, (3) a planarizing/hole injection layer which is located adjacent to the anode electrical conducting layer, (4) a quantum dot layer including the plurality of quantum dots which do not have capping layers, and (5) a cathode electrical conducting layer which is located adjacent to the quantum dot layer.

Abstract: A light emitting diode (LED) for minimizing crystal defects in an active region and enhancing recombination efficiency of electrons and holes in the active region includes non-polar GaN-based semiconductor layers grown on a non-polar substrate. The semiconductor layers include a non-polar N-type semiconductor layer, a non-polar P-type semiconductor layer, and non-polar active region layers positioned between the N-type semiconductor layer and the P-type semiconductor layer. The non-polar active region layers include a well layer and a barrier layer with a superlattice structure.

Abstract: A memory device includes a first electrode, a second electrode spaced apart from the first electrode and a nanotube or nanowire network disposed between the first electrode and the second electrode, having a stacked structure of a P-type network and an N-type network, and having a diode characteristic. Since the nanotube or nanowire network has the stacked structure of the P-type network and the N-type network, and has the diode characteristic, it is possible to enhance a degree of integration of the memory device and simplify the fabrication processes without separately requiring a selection device.

Abstract: A yellow Light Emitting Diode (LED) with a peak emission wavelength in the range 560-580 nm is disclosed. The LED is grown on one or more III-nitride-based semipolar planes and an active layer of the LED is composed of indium (In) containing single or multi-quantum well structures. The LED quantum wells have a thickness in the range 2-7 nm. A multi-color LED or white LED comprised of at least one semipolar yellow LED is also disclosed.

Abstract: A group III nitride semiconductor optical device includes: a substrate comprising a group III nitride semiconductor; a first group-III nitride semiconductor region on a primary surface of the substrate; a second group-III nitride semiconductor region on the primary surface of the substrate; and an active layer between the first group-III nitride semiconductor region and the second group-III nitride semiconductor region. The primary surface of the substrate tilts at a tilt angle in the range of 63 degrees to smaller than 80 degrees toward the m-axis of the group III nitride semiconductor from a plane perpendicular to a reference axis extending along the c-axis of the group III nitride semiconductor. The first group-III nitride semiconductor region, the active layer, and the second group-III nitride semiconductor region are arranged in the direction of the normal axis to the primary surface of the substrate. The active layer is configured to produce light having a wavelength in the range of 580 nm to 800 nm.

Abstract: This invention concerns a quantum device, suitable for quantum computing, based on dopant atoms located in a solid semiconductor or insulator substrate. In further aspects the device is scaled up. The invention also concerns methods of reading out from the devices, initializing them, using them to perform logic operations and making them.

Abstract: A microwave circuit includes at least one inductive portion and at least one capacitive portion and having a resonance frequency, the microwave circuit including a material which acts as a dielectric for the capacitive portion, characterized in that the material acting as a dielectric includes an active region that is an electrically pumped semiconductor heterostructure having at least two energy levels whose energy separation is close to the resonance frequency of the microwave circuit.

Abstract: In one aspect, the present invention provides a method of processing a substrate, e.g., a semiconductor substrate, by irradiating a surface of the substrate (or at least a portion of the surface) with a first set of polarized short laser pulses while exposing the surface to a fluid to generate a plurality of structures on the surface, e.g., within a top layer of the surface. Subsequently, the structured surface can be irradiated with another set of polarized short laser pulses having a different polarization than that of the initial set while exposing the structured surface to a fluid, e.g., the same fluid initially utilized to form the structured surface or a different fluid. In many embodiments, the second set of polarized laser pulses cause the surface structures formed by the first set to break up into smaller-sized structures, e.g., nano-sized features such as nano-sized rods.

Abstract: A method for fabricating a semiconductor nanowire that has first and second regions is provided. A catalyst particle is put on a substrate. A first source gas is introduced, thereby growing the first region from the catalyst particle via a vapor-liquid-solid phase growth. A protective coating is formed on a sidewall of the first region, and a second source gas is introduced to grow the second region extending from the first region via the liquid-solid-phase growth.

Abstract: Sensor are generally provided that include a layer of silicon oxide on a portion of a n+ layer to form an uneven surface where the layer of silicon oxide defines a thicker region than an exposed portion of the n+ layer. First and second metal contacts can be on the layer of silicon oxide, with first and second nanowires extending respectively from a first base on the first metal contact and a second base on the second metal contact. The first nanowire and the second nanowire are connected together at an apex to form a v-shaped nanocantilever, wherein the apex is positioned over the exposed n+ layer, and wherein the nanowires comprise indium and nitrogen. Methods of fabricating such sensors, along with methods of their use, are also generally provided.

Abstract: The present invention relates to a GaN series light-emitting diode structure, which includes a substrate; at least one GaN series layer formed over the substrate; subsequently an interface blocking structure composed of an n-type GaN series superlattice structure and a GaN series light-emitting layer, and a GaN series light-emitting layer are formed over the GaN series layer; and a p-type GaN series layer formed over the GaN series light-emitting layer. In the present invention, the radiative recombination efficiency is improved by introducing an interface blocking structure before the light-emitting layer under the epitaxial conditions of low temperature and pure nitrogen atmosphere.

Abstract: Provided is an infrared light detector 100 wherein a light coupling mechanism 110 is configured by a metal thin film or metal thin plate in which a plurality of windows apart from each other are formed. Each of the windows is formed by multangular shapes in which a part of the internal angles are obtuse angles. The plurality of windows are periodically arrayed in postures having translational symmetry in at least two directions. The array cycle p of the plurality of windows are set according to a wavelength A? of the infrared light of a substrate including a first electronic layer 110 so as to fall within a range with reference to a value at which a perpendicular oscillating electric field component in a first electronic region 10 indicates a peak value.

Abstract: A nitride semiconductor light emitting device, and a method of manufacturing the same are disclosed. The nitride semiconductor light emitting device includes a substrate, an n-type nitride semiconductor layer disposed on the substrate and including a plurality of V-shaped pits in a top surface thereof, an active layer disposed on the n-type nitride semiconductor layer and including depressions conforming to the shape of the plurality of V-shaped pits, and a p-type nitride semiconductor layer disposed on the active layer and including a plurality of protrusions on a top surface thereof. Since the plurality of V-shaped pits are formed in the top surface of the n-type nitride semiconductor layer, the protrusions can be formed on the p-type nitride semiconductor layer as an in-situ process. Accordingly, the resistance to ESD, and light extraction efficiency are enhanced.

Abstract: The present disclosure generally relates to techniques for controlled quantum dot growth as well as a quantum dot structures. In some examples, a method is described that includes one or more of providing a substrate, forming a defect on the substrate, depositing a layer on the substrate and forming quantum dots along the defect.

Abstract: A nanowire light emitting diode (LED) and method of emitting light employ a plasmonic mode. The nanowire LED includes a nanowire having a semiconductor junction, a shell layer coaxially surrounding the nanowire, and an insulating layer, which is plasmonically thin, isolating the shell layer from the nanowire. The shell layer supports a surface plasmon that couples to the semiconductor junction by an evanescent field. Light is generated in a vicinity of the semiconductor junction and the surface plasmon is coupled to the semiconductor junction during light generation. The coupling enhances one or both of an efficiency of light emission and a light emission rate of the LED. A method of making the nanowire LED includes forming the nanowire, providing the insulating layer on the surface of the nanowire, and forming the shell layer on the insulating layer in the vicinity of the semiconductor junction.