Quantum Well Patents (Class 257/14)
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Patent number: 8567960Abstract: Emissive quantum photonic imagers comprised of a spatial array of digitally addressable multicolor pixels. Each pixel is a vertical stack of multiple semiconductor laser diodes, each of which can generate laser light of a different color. Within each multicolor pixel, the light generated from the stack of diodes is emitted perpendicular to the plane of the imager device via a plurality of vertical waveguides that are coupled to the optical confinement regions of each of the multiple laser diodes comprising the imager device. Each of the laser diodes comprising a single pixel is individually addressable, enabling each pixel to simultaneously emit any combination of the colors associated with the laser diodes at any required on/off duty cycle for each color. Each individual multicolor pixel can simultaneously emit the required colors and brightness values by controlling the on/off duty cycles of their respective laser diodes.Type: GrantFiled: September 16, 2009Date of Patent: October 29, 2013Assignee: Ostendo Technologies, Inc.Inventors: Hussein S. El-Ghoroury, Robert G. W. Brown, Dale A. McNeill, Huibert DenBoer, Andrew J. Lanzone
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Patent number: 8558215Abstract: A light emitting device may include a first conductive semiconductor layer, an active layer adjacent to the first conductive semiconductor layer and a second conductive semiconductor layer adjacent to the active layer. The active layer may include a first quantum well layer, a second quantum well layer and a barrier layer between the first quantum well layer and the second quantum well layer. The first quantum well layer may include a first plurality of sub-barrier layers and a first plurality of sub-quantum well layers, and the second quantum well layer may include a second plurality of sub-barrier layers and a second plurality of sub-quantum well layers. A bandgap of the first quantum well layer may be different than a bandgap of the second quantum well layer.Type: GrantFiled: September 16, 2010Date of Patent: October 15, 2013Assignee: LG Innotek Co., Ltd.Inventor: Hyo Kun Son
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Patent number: 8558257Abstract: Implementations and techniques for coupled asymmetric quantum confinement structures are generally disclosed.Type: GrantFiled: November 24, 2009Date of Patent: October 15, 2013Assignee: University of Seoul Industry Cooperation FoundationInventor: Doyeol Ahn
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Publication number: 20130263918Abstract: Photovoltaic nanocomposite and solar cell device including the photovoltaic nanocomposite, where the photovoltaic nanocomposite includes a film of solution processed semiconductor materials having an n-type material selected from n-type quantum dots and n-type nanocrystals, and a p-type material selected from p-type quantum dots and p-type nanocrystals, and where the n-type material has a conduction band level at least equal, compared to vacuum level, to that of the p-type material, the p-type material has a valence band at the most equal, compared to vacuum level, to that of the n-type material. at least a portion of the n-type material and at least a portion of the p-type material are present in a bulk nano-heterojunction binary nanocomposite layer having a blend of the n-type material and the p-type material.Type: ApplicationFiled: April 9, 2012Publication date: October 10, 2013Applicant: FUNDACIÓ INSTITUT DE CIÈNCIES FOTÒNIQUESInventors: GERASIMOS KONSTANTATOS, ARUP KUMAR RATH, MARIA BERNECHEA NAVARRO, LUIS MARTINEZ MONTBLANCH
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Patent number: 8551868Abstract: A method of fabricating quantum confinements is provided. The method includes depositing, using a deposition apparatus, a material layer on a substrate, where the depositing includes irradiating the layer, before a cycle, during a cycle, and/or after a cycle of the deposition to alter nucleation of quantum confinements in the material layer to control a size and/or a shape of the quantum confinements. The quantum confinements can include quantum wells, nanowires, or quantum dots. The irradiation can be in-situ or ex-situ with respect to the deposition apparatus. The irradiation can include irradiation by photons, electrons, or ions. The deposition is can include atomic layer deposition, chemical vapor deposition, MOCVD, molecular beam epitaxy, evaporation, sputtering, or pulsed-laser deposition.Type: GrantFiled: March 24, 2011Date of Patent: October 8, 2013Assignees: The Board of Trustees of the Leland Stanford Junior Universit, Honda Patents & Technologies North America, LLCInventors: Timothy P. Holme, Andrei Iancu, Hee Joon Jung, Michael C Langston, Munekazu Motoyama, Friedrich B. Prinz, Takane Usui, Hitoshi Iwadate, Neil Dasgupta, Cheng-Chieh Chao
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Patent number: 8546805Abstract: Systems and methods are disclosed for performing laser annealing in a manner that reduces or minimizes wafer surface temperature variations during the laser annealing process. The systems and methods include annealing the wafer surface with first and second laser beams that represent preheat and anneal laser beams having respective first and second intensities. The preheat laser beam brings the wafer surface temperate close to the annealing temperature and the anneal laser beam brings the wafer surface temperature up to the annealing temperature. The anneal laser beam can have a different wavelength, or the same wavelength but different orientation relative to the wafer surface. Reflectivity maps of the wafer surface at the preheat and anneal wavelengths are measured and used to select first and second intensities that ensure good anneal temperature uniformity as a function of wafer position.Type: GrantFiled: January 27, 2012Date of Patent: October 1, 2013Assignee: Ultratech, Inc.Inventors: Xiaohua Shen, Yun Wang, Xiaoru Wang
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Publication number: 20130248820Abstract: A gallium nitride substrate includes a plurality of physical level differences in a surface thereof. All the physical level differences existing in the surface have a dimension of not more than 4 ?m. A relationship of (H?L)/H×100?80 is satisfied in all the physical level differences, where H represents a higher value of cathodoluminescence emission intensities of a wavelength corresponding to a bandgap of the gallium nitride substrate, and L represents a lower value of the cathodoluminescence emission intensities, the cathodoluminescence emission intensities being measured in an upper step and a lower step of the physical level difference.Type: ApplicationFiled: March 11, 2013Publication date: September 26, 2013Applicant: Hitachi Cable, Ltd.Inventor: Shunsuke Yamamoto
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Patent number: 8541869Abstract: A III-nitride edge-emitting laser diode is formed on a surface of a III-nitride substrate having a semipolar orientation, wherein the III-nitride substrate is cleaved by creating a cleavage line along a direction substantially perpendicular to a nonpolar orientation of the III-nitride substrate, and then applying force along the cleavage line to create one or more cleaved facets of the III-nitride substrate, wherein the cleaved facets have an m-plane or a-plane orientation.Type: GrantFiled: February 12, 2008Date of Patent: September 24, 2013Assignee: The Regents of the University of CaliforniaInventors: Shuji Nakamura, James S. Speck, Steven P. DenBaars, Anurag Tyagi
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Patent number: 8541769Abstract: A single crystalline silicon carbide layer can be grown on a single crystalline sapphire substrate. Subsequently, a graphene layer can be formed by conversion of a surface layer of the single crystalline silicon layer during an anneal at an elevated temperature in an ultrahigh vacuum environment. Alternately, a graphene layer can be deposited on an exposed surface of the single crystalline silicon carbide layer. A graphene layer can also be formed directly on a surface of a sapphire substrate or directly on a surface of a silicon carbide substrate. Still alternately, a graphene layer can be formed on a silicon carbide layer on a semiconductor substrate. The commercial availability of sapphire substrates and semiconductor substrates with a diameter of six inches or more allows formation of a graphene layer on a commercially scalable substrate for low cost manufacturing of devices employing a graphene layer.Type: GrantFiled: November 9, 2010Date of Patent: September 24, 2013Assignee: International Business Machines CorporationInventors: Jack O. Chu, Christos D. Dimitrakopoulos, Marcus O. Freitag, Alfred Grill, Timothy J. McArdle, Robert L. Wisnieff
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Patent number: 8541770Abstract: Select devices including an open volume that functions as a high bandgap material having a low dielectric constant are disclosed. The open volume may provide a more nonlinear, asymmetric I-V curve and enhanced rectifying behavior in the select devices. The select devices may comprise, for example, a metal-insulator-insulator-metal (MIIM) diode. Various methods may be used to form select devices and memory systems including such select devices. Memory devices and electronic systems include such select devices.Type: GrantFiled: August 16, 2011Date of Patent: September 24, 2013Assignee: Micron Technology, Inc.Inventors: Bhaskar Srinivasan, Gurtej S. Sandhu
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Patent number: 8541252Abstract: The use of an abbreviated GaN growth mode on nano-patterned AGOG sapphire substrates, which utilizes a process of using 15 nm low temperature GaN buffer and bypassing etch-back and recovery processes during epitaxy, enables the growth of high-quality GaN template on nano-patterned AGOG sapphire. The GaN template grown on nano-patterned AGOG sapphire by employing abbreviated growth mode has two orders of magnitude lower threading dislocation density than that of conventional GaN template grown on planar sapphire. The use of abbreviated growth mode also leads to significant reduction in cost of the epitaxy. The growths and characteristics of InGaN quantum wells (QWs) light emitting diodes (LEDs) on both templates were compared. The InGaN QWs LEDs grown on the nano-patterned AGOG sapphire demonstrated at least a 24% enhancement of output power enhancement over that of LEDs grown on conventional GaN templates.Type: GrantFiled: December 17, 2010Date of Patent: September 24, 2013Assignee: Lehigh UniversityInventors: Nelson Tansu, Helen M. Chan, Richard P. Vinci, Yik-Khoon Ee, Jeffrey Biser
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Publication number: 20130234111Abstract: A method for forming optical devices. The method includes providing a gallium nitride substrate member having a crystalline surface region and a backside region. The method also includes subjecting the backside region to a laser scribing process to form a plurality of scribe regions on the backside region and forming a metallization material overlying the backside region including the plurality of scribe regions. The method removes at least one optical device using at least one of the scribe regions.Type: ApplicationFiled: November 9, 2010Publication date: September 12, 2013Applicant: Soraa, Inc.Inventors: Nicholas J. Pfister, James W. Raring, Mathew Schmidt
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Publication number: 20130234112Abstract: A semiconductor optical modulator includes a first n-type semiconductor region, a first p-type semiconductor region, an i-type semiconductor region, a second p-type semiconductor region, and a second n-type semiconductor region that constitute a stacked layer structure. The stacked layer structure includes a first cladding layer, a second cladding layer, and a core layer disposed between the first and second cladding layer. The first n-type semiconductor region and the first p-type semiconductor region form a first p-n junction disposed in an intermediate region between the first and second cladding layer. The second p-type semiconductor region and the second n-type semiconductor region form a second p-n junction disposed in the intermediate region or the second cladding layer. The intermediate region, the first n-type semiconductor region, and the second n-type semiconductor region include the core layer, the first cladding layer, and part or all of the second cladding layer, respectively.Type: ApplicationFiled: February 27, 2013Publication date: September 12, 2013Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventor: Naoya KONO
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Patent number: 8530257Abstract: Methods for improving the temperature performance of AlInGaP based light emitters. Nitrogen is added to the quantum wells in small quantities. Nitrogen is added in a range of about 0.5 percent to 2 percent. The addition of nitrogen increases the conduction band offset and increases the separation of the indirect conduction band. To keep the emission wavelength in a particular range, the concentration of In in the quantum wells may be decreased or the concentration of Al in the quantum wells may be increased. The net result is an increase in the conduction band offset and an increase in the separation of the indirect conduction band.Type: GrantFiled: August 27, 2012Date of Patent: September 10, 2013Assignee: Finisar CorporationInventor: Ralph Herbert Johnson
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Publication number: 20130228751Abstract: A method of forming nanowire devices. The method includes forming a stressor layer circumferentially surrounding a semiconductor nanowire. The method is performed such that, due to the stressor layer, the nanowire is subjected to at least one of radial and longitudinal strain to enhance carrier mobility in the nanowire. Radial and longitudinal strain components can be used separately or together and can each be made tensile or compressive, allowing formulation of desired strain characteristics for enhanced conductivity in the nanowire of a given device.Type: ApplicationFiled: November 2, 2011Publication date: September 5, 2013Inventors: Bernd W Gotsmann, Siegfried F. Karg, Heike E. Riel
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Patent number: 8525151Abstract: Embodiments of an apparatus and methods of providing a quantum well device for improved parallel conduction are generally described herein. Other embodiments may be described and claimed.Type: GrantFiled: July 10, 2012Date of Patent: September 3, 2013Assignee: Intel CorporationInventors: Ravi Pillarisetty, Mantu Hudait, Been-Yih Jin, Benjamin Chu-Kung, Robert Chau
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Patent number: 8525149Abstract: A photon source comprising: a quantum dot; electrical contacts configured to apply an electric field across said quantum dot: and an electrical source coupled to said contacts, said electrical source being configured to apply a potential such that carriers are supplied to said quantum dot to form a bi-exciton or higher order exciton, wherein said photon source further comprises a barrier configured to increase the time which a carrier takes to tunnel to and from said quantum dot to be greater than the radiative lifetime of an exciton in the quantum dot, the quantum dot being suitable for emission of entangled photons during decay of a bi-exciton or higher order exciton.Type: GrantFiled: October 13, 2010Date of Patent: September 3, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Richard Mark Stevenson, Andrew James Shields
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Patent number: 8519379Abstract: An embodiment relates to a device comprising a substrate, a nanowire and a doped epitaxial layer surrounding the nanowire, wherein the nanowire is configured to be both a channel to transmit wavelengths up to a selective wavelength and an active element to detect the wavelengths up to the selective wavelength transmitted through the nanowire. Another embodiment relates to a device comprising a substrate, a nanowire and one or more photogates surrounding the nanowire, wherein the nanowire is configured to be both a channel to transmit wavelengths up to a selective wavelength and an active element to detect the wavelengths up to the selective wavelength transmitted through the nanowire, and wherein the one or more photogates comprise an epitaxial layer.Type: GrantFiled: December 8, 2009Date of Patent: August 27, 2013Assignee: Zena Technologies, Inc.Inventors: Young-June Yu, Munib Wober
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Patent number: 8513696Abstract: A lateral thermal dissipation LED and a fabrication method thereof are provided. The lateral thermal dissipation LED utilizes a patterned metal layer and a lateral heat spreading layer to transfer heat out of the LED. The thermal dissipation efficiency of the LED is increased, and the lighting emitting efficiency is accordingly improved.Type: GrantFiled: March 4, 2010Date of Patent: August 20, 2013Assignee: Advanced Optoelectronic Technology, Inc.Inventors: Po Min Tu, Shih Cheng Huang, Ying Chao Yeh, Wen Yu Lin, Peng Yi Wu, Shih Hsiung Chan
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Patent number: 8513643Abstract: An optical semiconductor device such as a light emitting diode is formed on a transparent substrate having formed thereon a template layer, such as AlN, which is transparent to the wavelength of emission of the optical device. A mixed alloy defect redirection region is provided over the template layer such that the composition of the defect redirection region approaches or matches the composition of the regions contiguous thereto. For example, the Al content of the defect redirection region may be tailored to provide a stepped or gradual Aluminum content from template to active layer. Strain-induced cracking and defect density are reduced or eliminated.Type: GrantFiled: April 28, 2011Date of Patent: August 20, 2013Assignee: Palo Alto Research Center IncorporatedInventors: Christopher L. Chua, Zhihong Yang, Noble M. Johnson
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Patent number: 8513641Abstract: Disclosed herein is a nanowire including silicon rich oxide and a method for producing the same. The nanowire exhibits excellent electrically conducting properties and optical characteristics, and therefore is effectively used in a variety of applications including, for example, solar cells, sensors, photodetectors, light emitting diodes, laser diodes, EL devices, PL devices, CL devices, FETs, CTFs, surface plasmon waveguides, MOS capacitors and the like.Type: GrantFiled: January 8, 2009Date of Patent: August 20, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Eun Kyung Lee, Byoung Lyong Choi, Gyeong Su Park, Jai Yong Han
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Patent number: 8513634Abstract: A data storage and a semiconductor memory device including the same are provided, the data storage including a lower electrode, a first discharge prevention layer stacked on the lower electrode, a phase-transition layer on the first discharge prevention layer, a second discharge prevention layer stacked on the phase-transition layer, and an upper electrode stacked on the second discharge prevention layer. The phase transition layer includes oxygen and exhibits two different resistance characteristics depending on whether an insulating property thereof changed. The first and second discharge prevention layers block discharge of the oxygen from the phase transition layer.Type: GrantFiled: June 15, 2009Date of Patent: August 20, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-hyun Lee, Sung-ho Park, Myoung-jae Lee, Young-soo Park
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Patent number: 8513645Abstract: A source gas flows through a flow channel 23 of a metal-organic vapor phase epitaxy reactor 21. The source gas is fed in a direction across a main surface 25a of a susceptor 25. GaN substrates 27a to 27c are placed on the susceptor main surface 25a. An off-angle monotonically varies on a line segment extending from one point on the edges of the main surfaces of the gallium nitride substrates 27a to 27c to another point on the edges. The orientations of the GaN substrates 27a to 27c are represented by the orientations of the orientation flats. By placing the plurality of gallium nitride substrates 27a to 27c on the susceptors 25 of the metal-organic vapor phase epitaxy reactor 21 in these orientations, the influence of the off-angle distribution can be reduced by using the influence originated from the flow of the source gas.Type: GrantFiled: February 20, 2008Date of Patent: August 20, 2013Assignee: Sumitomo Electric Industries, Ltd.Inventors: Yusuke Yoshizumi, Masaki Ueno, Takao Nakamura
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Patent number: 8507894Abstract: This invention concerns an electronic device for the control and readout of the electron or hole spin of a single dopant in silicon. The device comprises a silicon substrate in which there are one or more ohmic contact regions. An insulating region on top of the substrate. First and second barrier gates spaced apart to isolate a small region of charges to form an island of a Single Electron Transistor (SET). A third gate over-lying both the first and second barrier gates, but insulated from them, the third gate being able to generate a gate-induced charge layer (GICL) in the beneath it. A fourth gate in close proximity to a single dopant atom, the dopant atom being encapsulated in the substrate outside the region of the GICL but close enough to allow spin-dependent charge tunnelling between the dopant atom and the SET island under the control of gate potentials, mainly the fourth gate.Type: GrantFiled: February 11, 2009Date of Patent: August 13, 2013Assignee: Qucor Pty LimitedInventors: Andrea Morello, Andrew Dzurak, Hans-Gregor Huebl, Robert Graham Clark, Laurens Henry Willems Van Beveren, Lloyd Christopher Leonard Hollenberg, David Normal Jamieson, Christopher Escott
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Patent number: 8502204Abstract: An optoelectronic module includes a layer structure having a plurality of semiconductor layers including a substrate layer, a first layer arrangement and a second layer arrangement, wherein 1) the first layer arrangement has a light-emitting layer arranged on the substrate layer, 2) the second layer arrangement contains at least one circuit that controls an operating state of the light-emitting layer, and 3) the second layer arrangement is arranged on the substrate layer and/or surrounded by the substrate layer.Type: GrantFiled: May 13, 2009Date of Patent: August 6, 2013Assignee: OSRAM Opto Semiconductors GmbHInventors: Dieter Eissler, Siegfried Herrmann
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Patent number: 8502195Abstract: Systems, methods and devices for the efficient photocurrent generation in single- or multi-walled carbon nanotubes, which includes (SWNTs)/poly [3-hexylthiophene-2,5-diyl] (P3HT) hybrid photovoltaics, and exhibit the following features: photocurrent measurement at individual SWNT/P3HT heterojunctions indicate that both semiconducting (s-) and metallic (m-) SWNTs function as excellent hole acceptors; electrical transport and gate voltage dependent photocurrent indicate that P3HT p-dopes both s-SWNT and m-SWNT, and exciton dissociation is driven by a built-in voltage at the heterojunction. Some embodiments include a mm2 scale SWNT/P3HT bilayer hybrid photovoltaics using horizontally aligned SWNT arrays, which exhibit greater than 90% effective external quantum efficiency, among other things, which advantageously provide carbon nanomaterial based low cost and high efficiency hybrid photovoltaics.Type: GrantFiled: July 11, 2011Date of Patent: August 6, 2013Assignee: The Regents of the University of MichiganInventors: Nanditha Dissanayake, Zhaohui Zhong
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Patent number: 8502244Abstract: Solid state lighting (“SSL”) devices with improved contacts and associated methods of manufacturing are disclosed herein. In one embodiment, an SSL device includes a first semiconductor material, a second semiconductor material spaced apart from the first semiconductor material, and an active region between the first and second semiconductor materials. The SSL device also includes a first contact on the first semiconductor material and a second contact on the second semiconductor material. The second contact is opposite the first contact. The SSL device further includes an insulative material between the first contact and the first semiconductor material, the insulative material being generally aligned with the second contact.Type: GrantFiled: August 31, 2010Date of Patent: August 6, 2013Assignee: Micron Technology, Inc.Inventor: Martin F. Schubert
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Patent number: 8502197Abstract: A device including a locally modified buried first layer. A second layer is arranged on top of the first layer. The first layer includes at least one modified section and at least one unmodified section. The modified material of the locally modified buried first layer changes or induces mechanical strain in a portion of the second layer which is arranged above the at least one modified section. At least one nanostructure is placed on top of the second layer in an area, which is located above the at least one unmodified section of the first layer or adjacent thereto, said at least one nanostructure being formed by a strain-sensitive third material deposited on the locally strained second layer.Type: GrantFiled: December 11, 2012Date of Patent: August 6, 2013Assignee: Technische Universitat BerlinInventors: André Strittmatter, Andrei Schliwa, Tim David Germann, Udo W. Pohl, Vladimir Gaysler, Jan-Hindrik Schulze
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Patent number: 8502194Abstract: A light-emitting device and the method for making the same is disclosed. The light-emitting device is a semiconductor device, comprising a growth substrate, an n-type semiconductor layer, a quantum well active layer and a p-type semiconductor layer. It combines the holographic and the quantum well interdiffusion (QWI) to form a photonic crystal light-emitting device having a dielectric constant of two-dimensional periodic variation or a material composition of two-dimensional periodic variation in the quantum well active layer. The photonic crystal light-emitting devices can enhance the internal efficiency and light extraction efficiency.Type: GrantFiled: June 28, 2011Date of Patent: August 6, 2013Assignee: Epistar CorporationInventors: Chiu-Lin Yao, Ta-Cheng Hsu
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Patent number: 8502245Abstract: Provided is a semiconductor light emitting device. The semiconductor light emitting device comprises a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer. The active layer comprises a first active layer, a second active layer, an electron barrier layer on the first conductive type semiconductor layer. The first active layer and the second active layer comprise a quantum well layer and a quantum barrier layer. The electron barrier layer is formed between the first active layer and the second active layer. The second conductive type semiconductor layer is formed on the active layer.Type: GrantFiled: January 25, 2012Date of Patent: August 6, 2013Assignee: LG Innotek Co., Ltd.Inventors: Tae Yun Kim, Hyo Kun Son
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Patent number: 8492779Abstract: Disclosed a nitride semiconductor LED including: a substrate; a GaN-based buffer layer formed on the substrate; AlyGa1-yN/GaN short period superlattice (SPS) layers formed on the GaN-based buffer layer in a sandwich structure of upper and lower parts having an undoped GaN layer or an indium-doped GaN layer interposed therebetween (Here, 0?y?1); a first electrode layer of an n-GaN layer formed on the upper AlyGa1-yN/GaN SPS layer; an active layer formed on the first electrode layer; and a second electrode layer of a p-GaN layer formed on the active layer.Type: GrantFiled: October 1, 2009Date of Patent: July 23, 2013Assignee: LG Innotek Co., Ltd.Inventor: Suk Hun Lee
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Patent number: 8492787Abstract: This application discloses alight-emitting diode device, comprising an epitaxial structure having a light-emitting layer, a first-type conductivity layer, and a second-type conductivity layer wherein the thicknesses of the first-type conductivity confining layer is not equal to the second-type conductivity confining layer and the light-emitting layer is not overlapped with the portion of the epitaxial structure corresponding to the peak zone of the wave intensity distribution curve along the direction of the epitaxy growth.Type: GrantFiled: June 17, 2009Date of Patent: July 23, 2013Assignee: Epistar CorporationInventors: Ta-Cheng Hsu, Meng-Lun Tsai
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Patent number: 8492746Abstract: A light emitting diode (LED) die includes a wavelength conversion layer having a base material, and a plurality of particles embedded in the base material including wavelength conversion particles, and reflective particles. A method for fabricating light emitting diode (LED) dice includes the steps of mixing the wavelength conversion particles in the base material to a first weight percentage, mixing the reflective particles in the base material to a second weight percentage, curing the base material to form a wavelength conversion layer having a selected thickness, and attaching the wavelength conversion layer to a die.Type: GrantFiled: May 4, 2012Date of Patent: July 23, 2013Assignee: SemiLEDS Optoelectronics Co., Ltd.Inventor: Jui-Kang Yen
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Patent number: 8481991Abstract: An epitaxial structure for a III-Nitride based optical device, comprising an active layer with anisotropic strain on an underlying layer, where a lattice constant and strain in the underlying layer are partially or fully relaxed in at least one direction due to a presence of misfit dislocations, so that the anisotropic strain in the active layer is modulated by the underlying layer.Type: GrantFiled: August 23, 2010Date of Patent: July 9, 2013Assignee: The Regents of the University of CaliforniaInventors: Hiroaki Ohta, Feng Wu, Anurag Tyagi, Arpan Chakraborty, James S. Speck, Steven P. DenBaars, Shuji Nakamura, Erin C. Young
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Patent number: 8471240Abstract: An optoelectronic component including a semiconductor layer structure, the semiconductor layer structure including a superlattice composed of stacked layers of III-V compound semiconductors of a first and at least one second type. Adjacent layers of different types in the superlattice differ in composition with respect to at least one element, at least two layers of the same type having a different content of the at least one element, the content of the at least one element is graded within a layer of the superlattice, and the layers of the superlattice contain dopants in predefined concentrations, with the superlattice comprising layers that are doped with different dopants. In this way, the electrical, optical and epitaxial properties of the superlattice can be adapted in the best possible manner to given requirements, particularly epitaxial constraints.Type: GrantFiled: January 19, 2011Date of Patent: June 25, 2013Assignee: Osram Opto Semiconductors GmbHInventors: Christoph Eichler, Alfred Lell, Andreas Miler, Marc Schillgalies
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Patent number: 8471268Abstract: There is provided a light emitting device of a simpler structure, capable of ensuring a broad light emitting area and a high light emitting efficiency, while manufactured in a simplified and economically efficient process. The light emitting device including: a semiconductor layer; an active layer formed on the semiconductor layer, the active layer comprising at least one of a quantum well structure, a quantum dot and a quantum line; an insulating layer formed on the active layer; and a metal layer formed on the insulating layer.Type: GrantFiled: September 2, 2011Date of Patent: June 25, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Won Ha Moon, Chang Hwan Choi, Dong Woohn Kim, Hyun Jun Kim
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Publication number: 20130153860Abstract: A method of forming a hybrid nanostructure on graphene, the method including providing a graphene layer on a substrate; forming a metal layer on the graphene layer; and chemically depositing a nanomaterial on the graphene layer on which the metal layer is formed to form the hybrid nanostructure.Type: ApplicationFiled: December 11, 2012Publication date: June 20, 2013Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventor: SAMSUNG ELECTRONICS CO., LTD.
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Patent number: 8466449Abstract: There is provided a nitride semiconductor device including: an n-type nitride semiconductor layer; a p-type nitride semiconductor layer; and an active layer formed between the n-type and p-type nitride semiconductor layers, the active layer including a plurality of quantum well layers and at least one quantum barrier layer deposited alternately with each other, wherein the active layer includes a first quantum well layer, a second quantum well layer formed adjacent to the first quantum well layer toward the p-type nitride semiconductor layer and having a quantum level higher than a quantum level of the first quantum well layer, and a tunneling quantum barrier layer formed between the first and second quantum well layers and having a thickness enabling a carrier to be tunneled therethrough.Type: GrantFiled: April 11, 2011Date of Patent: June 18, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Soo Min Lee, Hee Seok Park, Jae Woong Han, Seong Suk Lee, Cheol Soo Sone
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Publication number: 20130146843Abstract: Vapor-liquid-solid growth of nanowires is tailored to achieve complex one-dimensional material geometries using phase diagrams determined for nanoscale materials. Segmented one-dimensional nanowires having constant composition display locally variable electronic band structures that are determined by the diameter of the nanowires. The unique electrical and optical properties of the segmented nanowires are exploited to form electronic and optoelectronic devices. Using gold-germanium as a model system, in situ transmission electron microscopy establishes, for nanometer-sized Au—Ge alloy drops at the tips of Ge nanowires (NWs), the parts of the phase diagram that determine their temperature-dependent equilibrium composition. The nanoscale phase diagram is then used to determine the exchange of material between the NW and the drop. The phase diagram for the nanoscale drop deviates significantly from that of the bulk alloy.Type: ApplicationFiled: February 1, 2013Publication date: June 13, 2013Applicant: Brookhaven Science Associates, LLCInventor: Brookhaven Science Associates, LLC
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Patent number: 8461029Abstract: A method for fabricating quantum wells by using indium gallium nitride (InGaN) semiconductor material includes fabricating a potential well on a layered group III-V nitride structure at a first predetermined temperature in a reactor chamber by injecting into the reactor chamber an In precursor gas and a Ga precursor gas. The method further includes, subsequent to the fabrication of the potential well, terminating the Ga precursor gas, maintaining a flow of the In precursor gas, and increasing the temperature in the reactor chamber to a second predetermined temperature while adjusting the In precursor gas flow rate from a first to a second flow rate. In addition, the method includes annealing and stabilizing the potential well at the second predetermined temperature while maintaining the second flow rate. The method also includes fabricating a potential barrier above the potential well at the second predetermined temperature while resuming the Ga precursor gas.Type: GrantFiled: August 3, 2012Date of Patent: June 11, 2013Assignee: Lattice Power (JIANGXI) CorporationInventors: Fengyi Jiang, Li Wang, Chunlan Mo, Wenqing Fang
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Patent number: 8461569Abstract: A semiconductor device includes a quantum dot and a plurality of layers, wherein said plurality of layers includes: a first layer; a stressor layer; and a patterned layer wherein said stressor layer overlies said first layer and said patterned layer overlies said stressor layer; wherein said stressor layer has a substantially different lattice constant to said first layer and said patterned layer and has a pit provided in said layer; said quantum dot lying above said patterned layer aligned with said pit.Type: GrantFiled: May 10, 2011Date of Patent: June 11, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Joanna Krystyna Skiba-Szymanska, Andrew James Shields
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Patent number: 8461862Abstract: One embodiment of the invention includes a quantum processor system. The quantum processor system includes a first resonator having a first characteristic frequency and a second resonator having a second characteristic frequency greater than the first characteristic frequency. A qubit cell is coupled to each of the first resonator and the second resonator. The qubit cell has a frequency tunable over a range of frequencies including the first characteristic frequency and the second characteristic frequency. A classical control mechanism is configured to tune the frequency of the qubit cell as to transfer quantum information between the first resonator and the second resonator.Type: GrantFiled: November 30, 2011Date of Patent: June 11, 2013Assignee: Northrop Grumman Systems CorporationInventors: Aaron A. Pesetski, James E. Baumgardner
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Patent number: 8461674Abstract: A thermal plate for a substrate support assembly in a semiconductor plasma processing apparatus, comprises multiple independently controllable planar thermal zones arranged in a scalable multiplexing layout, and electronics to independently control and power the planar heater zones. Each planar thermal zone uses at least one Peltier device as a thermoelectric element. A substrate support assembly in which the thermal plate is incorporated includes an electrostatic clamping electrode layer and a temperature controlled base plate. Methods for manufacturing the thermal plate include bonding together ceramic or polymer sheets having planar thermal zones, positive, negative and common lines and vias.Type: GrantFiled: September 21, 2011Date of Patent: June 11, 2013Assignee: Lam Research CorporationInventors: Keith William Gaff, Keith Comendant, Anthony Ricci
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Publication number: 20130140524Abstract: A noble metal nanoparticle can be grown on a semiconductor substrate by contacting a predetermined region of the substrate with a solution including noble metal ions. The predetermined region of the semiconductor substrate can be exposed by applying a polymeric layer over the substrate selectively removing a portion of the polymeric layer. The nanoparticles can be prepared in a predetermined pattern. The nanoparticle can be formed with a barrier separating it from another nanoparticle on the substrate; for example, nanoparticle can be located in a pit etched in the substrate. The size and location of the nanoparticle can be stable at elevated temperatures.Type: ApplicationFiled: January 17, 2013Publication date: June 6, 2013Applicant: MASSACHUSETTS INSTITUTE OF TECHNOLOGYInventor: MASSACHUSETTS INSTITUTE OF TECHNOLOGY
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Publication number: 20130140523Abstract: An apparatus includes a substrate, a sequence of crystalline semiconductor layers on a planar surface of the substrate, and first and second sets of electrodes over the sequence. The sequence has a 2D quantum well therein. The first set of electrodes border opposite sides of a lateral region of the sequence and are controllable to vary a width of a non-depleted portion of the quantum well along the top surface. The second set of electrodes border channels between the lateral region and first and second adjacent lateral areas of the sequence and are controllable to vary widths of non-depleted segments of the quantum well in the channels. The electrodes are such that straight lines connecting the lateral areas via the channels either pass between one of the electrodes and the substrate or are misaligned to an effective [1 10] lattice direction of the sequence.Type: ApplicationFiled: January 12, 2012Publication date: June 6, 2013Inventor: Robert L. Willett
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Patent number: 8455856Abstract: Various embodiments provide materials and methods for integrating exemplary heterostructure field-effect transistor (HFET) driver circuit or thyristor driver circuit with LED structures to reduce or eliminate resistance and/or inductance associated with their conventional connections.Type: GrantFiled: April 1, 2011Date of Patent: June 4, 2013Assignee: STC.UNMInventor: Stephen D. Hersee
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Patent number: 8450720Abstract: A method of fabricating a frontside-illuminated inverted quantum well infrared photodetector may include providing a quantum well wafer having a bulk substrate layer and a quantum material layer, wherein the quantum material layer includes a plurality of alternating quantum well layers and barrier layers epitaxially grown on the bulk substrate layer. The method further includes applying at least one frontside common electrical contact to a frontside of the quantum well wafer, bonding a transparent substrate to the frontside of the quantum well wafer, thinning the bulk substrate layer of the quantum well wafer, and etching the quantum material layer to form quantum well facets that define at least one pyramidal quantum well stack. A backside electrical contact may be applied to the pyramidal quantum well stack. In one embodiment, a plurality of quantum well stacks is bonded to a read-out integrated circuit of a focal plane array.Type: GrantFiled: September 6, 2012Date of Patent: May 28, 2013Assignee: L-3 Communications Cincinnati Electronics CorporationInventors: David Forrai, Darrel Endres, Robert Jones, Michael James Garter
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Patent number: 8450719Abstract: A nitride-based light emitting device capable of achieving an enhancement in light emission efficiency and an enhancement in reliability is disclosed. The nitride-based light emitting device includes a light emitting layer including a quantum well layer and a quantum barrier layer, and a stress accommodating layer arranged on at least one surface of the quantum well layer of the light emitting layer.Type: GrantFiled: May 26, 2011Date of Patent: May 28, 2013Assignees: LG Innotek, Co. Ltd., LG Electronics, Inc.Inventor: Yong Tae Moon
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Patent number: 8445890Abstract: Solid state lighting devices grown on semi-polar facets and associated methods of manufacturing are disclosed herein. In one embodiment, a solid state light device includes a light emitting diode with an N-type gallium nitride (“GaN”) material, a P-type GaN material spaced apart from the N-type GaN material, and an indium gallium nitride (“InGaN”)/GaN multi quantum well (“MQW”) active region directly between the N-type GaN material and the P-type GaN material. At least one of the N-type GaN, InGaN/GaN MQW, and P-type GaN materials is grown a semi-polar sidewall.Type: GrantFiled: March 9, 2010Date of Patent: May 21, 2013Assignee: Micron Technology, Inc.Inventors: Lifang Xu, Zaiyuan Ren
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Publication number: 20130112940Abstract: Semiconductor structures having a nanocrystalline core and corresponding nanocrystalline shell are described. In an example, a semiconductor structure includes an anisotropic nanocrystalline core composed of a first semiconductor material and having an aspect ratio between, but not including, 1.0 and 2.0. The semiconductor structure also includes a nanocrystalline shell composed of a second, different, semiconductor material at least partially surrounding the anisotropic nanocrystalline core.Type: ApplicationFiled: May 31, 2012Publication date: May 9, 2013Inventors: Juanita Kurtin, Matthew J. Carillo, Steven Hughes