Abstract: Materials, methods, structures and device including the same can provide a semiconductor device such as an LED using an active region corresponding to a non-polar face or surface of III-V semiconductor crystalline material. In some embodiments, an active diode region contains more non-polar III-V material oriented to a non-polar plane than III-V material oriented to a polar plane. In other embodiments, a bottom region contains more non-polar m-plane or a-plane surface area GaN than polar c-plane surface area GaN facing an active region.

Abstract: A semiconductor device according to the present invention includes a substrate; a nitride semiconductor layer formed above the substrate and having a laminated structure including at least three layers; a heterojunction bipolar transistor formed in a region of the nitride semiconductor layer; and a field-effect transistor formed in a region of the nitride semiconductor layer, the region being different from the region in which the heterojunction bipolar transistor is formed.

Abstract: A Group III nitride semiconductor substrate is formed of a Group III nitride single crystal, and has a diameter of not less than 25.4 mm and a thickness of not less than 150 ?m. The substrate satisfies that a ratio of ??/? is not more than 0.1, where ? is a thermal expansion coefficient calculated from a temperature change in outside dimension of the substrate, and ?? is a difference (???L) between the thermal expansion coefficient ? and a thermal expansion coefficient ?L calculated from a temperature change in lattice constant of the substrate.

Abstract: Gallium nitride material-based semiconductor structures are provided. In some embodiments, the structures include a composite substrate over which a gallium nitride material region is formed. The gallium nitride material structures may include additional features, such as strain-absorbing layers and/or transition layers, which also promote favorable stress conditions. The reduction in stresses may reduce defect formation and cracking in the gallium nitride material region, as well as reducing warpage of the overall structure. The gallium nitride material-based semiconductor structures may be used in a variety of applications such as transistors (e.g. FETs) Schottky diodes, light emitting diodes, laser diodes, SAW devices, and sensors, amongst others devices.

Abstract: An apparatus includes a field-effect transistor (FET). The FET includes a region of first semiconductor and a layer of second semiconductor that is located on the region of the first semiconductor. The layer and region form a semiconductor heterostructure. The FET also includes source and drain electrodes that are located on one of the region and the layer and a gate electrode located to control a conductivity of a channel portion of the semiconductor heterostructure. The channel portion is located between the source and drain electrodes. The gate electrode is located vertically over the channel portion and portions of the source and drain electrodes.

Abstract: Impurity concentration of a second semiconductor region is set such that when a predetermined reverse bias is applied to a heterojunction diode configured by a first semiconductor region and the second semiconductor region, a breakdown voltage at least in a heterojunction region other than outer peripheral ends of the heterojunction diode is a breakdown voltage of a semiconductor device.

Abstract: A reconfigurable electric circuit includes first and second crystalline material layers positioned adjacent to each other and forming a first interface, and a first ferroelectric layer positioned adjacent to the first crystalline material layer and having ferroelectric domains applying an electric field to regions of the first interface to induce a quasi two-dimensional electron gas in the regions, wherein at least one of the regions forms a gate and at least one of the regions forms a channel.

Abstract: A semiconductor device includes: a first group-III nitride semiconductor layer formed on a substrate; a second group-III nitride semiconductor layer made of a single layer or two or more layers, formed on the first group-III nitride semiconductor layer, and acting as a barrier layer; a source electrode, a drain electrode, and a gate electrode formed on the second group-III nitride semiconductor layer, the gate electrode controlling a current flowing between the source and drain electrodes; and a heat radiation film with high thermal conductivity which covers, as a surface passivation film, the entire surface other than a bonding pad.

Abstract: Ge/Si and other nonsilicon film heterostructures are formed by hydrogen-induced exfoliation of the Ge film which is wafer bonded to a cheaper substrate, such as Si. A thin, single-crystal layer of Ge is transferred to Si substrate. The bond at the interface of the Ge/Si heterostructures is covalent to ensure good thermal contact, mechanical strength, and to enable the formation of an ohmic contact between the Si substrate and Ge layers. To accomplish this type of bond, hydrophobic wafer bonding is used, because as the invention demonstrates the hydrogen-surface-terminating species that facilitate van der Waals bonding evolves at temperatures above 600° C. into covalent bonding in hydrophobically bound Ge/Si layer transferred systems.

Abstract: An SiGe layer is grown on a silicon substrate. The SiGe layer or the silicon substrate and SiGe layer are porosified by anodizing the SiGe layer to form a strain inducing porous layer or a porous silicon layer and strain inducing porous layer. An SiGe layer and strained silicon layer are formed on the resultant structure. The SiGe layer in the stacking growth step only needs to be on the uppermost surface of the porous layer. For this reason, an SiGe layer with a low defect density and high concentration can be formed. Since the SiGe layer on the strain inducing porous layer can achieve a low defect density without lattice mismatching. Hence, a high-quality semiconductor substrate having a high strained silicon layer can be obtained.

Abstract: A high electron mobility device and method of making is provided whereby a two-dimensional electron gas is formed at a hetero-junction or hetero-interface between different polytypes of a semiconductor material. The different crystal forms or polytypes of the semiconductor material having different electronic bandgaps are used to provide the bandgap necessary to form the two-dimensional electron gas.

Abstract: An enhancement mode III-nitride heterojunction device that includes a region between the gate and the drain electrode thereof that is at the same potential as the source electrode thereof when the device is operating.

Abstract: Embodiments of the invention are provided for a thin film stack containing a plurality of epitaxial stacks disposed on a substrate and a method for forming such a thin film stack. In one embodiment, the epitaxial stack contains a first sacrificial layer disposed over the substrate, a first epitaxial film disposed over the first sacrificial layer, a second sacrificial layer disposed over the first epitaxial film, and a second epitaxial film disposed over the second sacrificial layer. The thin film stack may further contain additional epitaxial films disposed over sacrificial layers. Generally, the epitaxial films contain gallium arsenide alloys and the sacrificial layers contain aluminum arsenide alloys. Methods provide the removal of the epitaxial films from the substrate by etching away the sacrificial layers during an epitaxial lift off (ELO) process. The epitaxial films are useful as photovoltaic cells, laser diodes, or other devices or materials.

Abstract: Planar Schottky diodes for which the semiconductor material includes a heterojunction which induces a 2DEG in at least one of the semiconductor layers. A metal anode contact is on top of the upper semiconductor layer and forms a Schottky contact with that layer. A metal cathode contact is connected to the 2DEG, forming an ohmic contact with the layer containing the 2DEG.

Abstract: A P-N junction device and method of forming the same are disclosed. The P-N junction device may include a P-N diode, a PiN diode or a thyristor. The P-N junction device may have a monocrystalline or polycrystalline raised anode. In one embodiment, the P-N junction device results in a raised polycrystalline silicon germanium (SiGe) anode. In another embodiment, the P-N junction device includes a first terminal (anode) including a conductor layer positioned above an upper surface of a substrate and a remaining structure positioned in the substrate, the first terminal positioned over an opening in an isolation region; and a second terminal (cathode contact) positioned over the opening in the isolation region adjacent the first terminal. This latter embodiment reduces parasitic resistance and capacitance, and decreases the required size of a cathode implant area since the cathode contact is within the same STI opening as the anode.

Abstract: A semiconductor sensor determines physical and/or chemical properties of a medium, in particular a pH sensor. The semiconductor sensor has an electronic component with a sensitive surface, said component being constructed for its part on the basis of semiconductors with a large band gap (wide-gap semiconductor). The sensitive surface is provided at least in regions with a functional layer sequence which has an ion-sensitive surface. The functional layer sequence has at least one layer which is impermeable at least for the medium and/or the materials or ions to be determined.

Abstract: The semiconductor device, which provides reduced electric current leakage and parasitic resistance to achieve stable current gain, is provided. A first polycrystalline semiconductor layer is grown on a p-type polycrystalline silicon film exposed in a lower surface of a visor section composed of a multiple-layered film containing a p-type polycrystalline silicon film and a silicon nitride film, while growing the first semiconductor layer on a n-type collector layer, and then the first polycrystalline semiconductor layer is selectively removed.

Abstract: There is provided a method of producing a thin GaN film-joined substrate, including the steps of: joining on a GaN bulk crystalline body a substrate different in type or chemical composition from GaN; and dividing the GaN bulk crystalline body at a plane having a distance of at least 0.1 ?m and at most 100 ?m from an interface thereof with the substrate different in type, to provide a thin film of GaN on the substrate different in type, wherein the GaN bulk crystalline body had a surface joined to the substrate different in type, that has a maximum surface roughness Rmax of at most 20 ?m. Thus a GaN-based semiconductor device including a thin GaN film-joined substrate including a substrate different in type and a thin film of GaN joined firmly on the substrate different in type, and at least one GaN-based semiconductor layer deposited on the thin film of GaN, can be fabricated at low cost.

Abstract: An enhancement mode High Electron Mobility Transistor (HEMT) comprising a p-type nitride layer between the gate and a channel of the HEMT, for reducing an electron population under the gate. The HEMT may also comprise an Aluminum Nitride (AlN) layer between an AlGaN layer and buffer layer of the HEMT to reduce an on resistance of a channel.

Abstract: A semiconductor device is formed on a semiconductor substrate, which is comprised of: a base substrate; and a multilayer being formed on the base substrate and having a surface serving for an interface with the semiconductor device, the multilayer including alternating layers of a first compound semiconductor and a second compound semiconductor materially distinguishable from the first compound semiconductor, one selected from the group consisting of the first compound semiconductor and the second compound semiconductor being doped with one selected from the group consisting of carbon and transition elements.

Abstract: An aspect of the present invention inheres in a semiconductor wafer includes a support substrate, a first nitride semiconductor layer, at least an upper surface of which has become monocrystalline, the first semiconductor layer being provided on the support substrate, and a second nitride semiconductor layer containing nitrogen and gallium, the second nitride semiconductor layer being provided on the upper surface of the first nitride semiconductor layer.

Abstract: A semiconductor device exhibiting interband tunneling with a first layer with a first conduction band edge with an energy above a first valence band edge, with the difference a first band-gap. A second layer with second conduction band edge with an energy above a second valence band edge, with the difference a second band-gap, and the second layer formed permitting electron carrier tunneling transport. The second layer is between the first and a third layer, with the difference between the third valence band edge and the third conduction band edge a third band-gap. A Fermi level is nearer the first conduction band edge than the first valence band edge. The second valence band edge is beneath the first conduction band edge. The second conduction band edge is above the third valence band edge. The Fermi level is nearer the third valence band edge than to the third conduction band edge.

Abstract: The invention relates to a structure usable in electronic, optical or optoelectronic engineering which comprises a substantially crystalline layer made of an alloy consisting of at least one element of the column II of the periodic elements system and/or at least one element of the column IV of the periodic elements system and of N2 (said alloy being noted N-IV-N2), wherein said structure also comprises an InN layer. A method for producing an indium nitride layer, a substrate forming plate and the use thereof for indium nitride growth are also disclosed.

Abstract: A semiconductor electronic device comprises a substrate; a buffer layer formed on said substrate, having two or more layers of composite layers in which a first semiconductor layer comprising nitride based compound semiconductor having smaller lattice constant and greater coefficient of thermal expansion than the substrate and a second semiconductor layer comprising nitride based compound semiconductor having smaller lattice constant and greater coefficient of thermal expansion than the first semiconductor layer are alternately laminated; a semiconductor operating layer comprising nitride based compound semiconductor formed on said buffer layer; a dislocation reducing layer comprising nitride based compound semiconductor, formed in a location between a location directly under said buffer layer and inner area of said semiconductor operating layer, and comprising a lower layer area and an upper layer area each having an uneven boundary surface, wherein threading dislocation extending from the lower layer area t

Abstract: A semiconductor heterostructure (10) includes a crystalline substrate of a first semiconductor material and a mask (11) disposed over a surface of the crystalline substrate. The mask (11) has openings (12) including a plurality of elongated opening sections (13, 14) with a width (w) less than or equal to 900 nm. At least one first section (13) of the elongated opening sections is directed non-parallel relative to at least one second section (14) of the elongated opening sections. The semiconductor heterostructure (10) further includes an overgrowth crystalline layer of a second semiconductor material, filling the openings (12) and covering the mask. A method for manufacturing of such a semiconductor heterostructure is also presented.

Abstract: A method of forming a nitride semiconductor through ion implantation and an electronic device including the same are disclosed. In the method, an ion implantation region composed of a line/space pattern is formed on a substrate at an ion implantation dose of more than 1E17 ions/cm2 to 5E18 ions/cm2 or less and an ion implantation energy of 30˜50 keV, and a metal nitride thin film is grown on the substrate by epitaxial lateral overgrowth, thereby decreasing lattice defects in the metal nitride thin film. Thus, the electronic device has improved efficiency.

Abstract: It is desired for semiconductor devices to reduce leakage currents. In a semiconductor device having a stacked structure including a GaAs layer and an InGaP layer, p-type impurity is doped to the GaAs layer. Consequently, the conduction band of the GaAs is raised to higher than the Fermi level. As a result, electron accumulation is suppressed and the gate leakage current can be reduced.

Abstract: A GaN layer functions as an electron transit layer and is formed to exhibit, at least at a portion thereof, A/B ratio of 0.2 or less obtained by a photoluminescence measurement, where “A” is the light-emission intensity in the 500-600 nm band, and “B” is the light-emission intensity at the GaN band-edge.

Abstract: The present invention directed to photonic devices which emit or absorb light with a short wavelength formed using molybdenum oxide grown on substrates which consist of materials selected from element semiconductors, III-V or II-IV compound semiconductors, IV compound semiconductors, organic semiconductors, metal crystal and their derivatives or glasses. New inexpensive photonic devices which emit light with a wavelength from blue to deep ultraviolet rays are realized.

Abstract: It is an object of the present invention to form an organic transistor including an organic semiconductor having high crystallinity without loosing an interface between an organic semiconductor of a channel where carriers are spread out and a gate insulating layer and deteriorating a yield. A semiconductor device according to the present invention has a stacked structure of organic semiconductor layers, and at least the upper organic semiconductor layer is in a polycrystalline or a single crystalline state and the lower organic semiconductor layer is made of a material serving as a channel. Carrier mobility can be increased owing to the upper organic semiconductor layer having high crystallinity; thus, insufficient contact due to the upper organic semiconductor layer can be compensated by the lower organic semiconductor layer.

Abstract: A photodiode in which a pn junction is formed between the doped region (DG) formed in the surface of a crystalline semiconductor substrate and a semiconductor layer (HS) deposited above said doped region. An additional doping (GD) is provided in the edge region of the doped zone, by means of which additional doping the pn junction is shifted deeper into the substrate (SU). With the greater distance of the pn junction from defects at phase boundaries that is achieved in this way, the dark current within the photodiode is reduced.

Abstract: A transistor includes: a first semiconductor layer and a second semiconductor layer with a first region and a second region, which are sequentially formed above a substrate; a first p-type semiconductor layer formed on a region of the second semiconductor layer other than the first and second regions; and a second p-type semiconductor layer formed on the first p-type semiconductor layer. The first p-type semiconductor layer is separated from a drain electrode by interposing therebetween a first groove having a bottom composed of the first region, and from a source electrode by interposing therebetween a second groove having a bottom composed of the second region.

Abstract: A method for fabricating substantially relaxed SiGe alloy layers with a reduced planar defect density is disclosed The method of the present invention includes forming a strained Ge-containing layer on a surface of a Si-containing substrate; implanting ions at or below the Ge-containing layer/Si-containing substrate interface and heating to form a substantially relaxed SiGe alloy layer that has a reduced planar defect density. A substantially relaxed SiGe-on-insulator substrate material having a SiGe layer with a reduced planar defect density as well as heterostructures containing the same are also provided.

Abstract: The present invention provides a superior method for the removal of nitride semiconductor thin films, thick films, heterostructures, and bulk material from initial substrates and/or templates. The method utilizes specially patterned mask layers between the initial substrates/templates and the nitride semiconductors to decrease adhesion between the nitride semiconductor and underlying material. Thermal stresses generated upon cooling the nitride semiconductor from its deposition temperature trigger spontaneous separation of the nitride semiconductor from the initial substrate or template at the mask layer. The invention remedies deficiencies in the prior art by providing a simple, reproducible, and effective means of removing initial substrates and templates from a variety of nitride semiconductor layers and structures.

Abstract: The present invention provides novel silicon-germanium hydride compounds, methods for their synthesis, methods for their deposition, and semiconductor structures made using the novel compounds.

Abstract: An efficient method of fabricating a high-quality heteroepitaxial microstructure having a smooth surface. The method includes detaching a layer from a base structure to provide a carrier substrate having a detached surface, and then forming a heteroepitaxial microstructure on the detached surface of the carrier substrate by depositing an epitaxial layer on the detached surface of a carrier substrate. Also included is a heteroepitaxial microstructure fabricated from such method.

Abstract: Embodiments of the invention generally relate to epitaxial lift off (ELO) thin films and devices and methods used to form such films and devices. In one embodiment, a method for forming a thin film material during an epitaxial lift off process is provided which includes forming an epitaxial material over a sacrificial layer on a substrate, adhering a non-uniform support handle onto the epitaxial material, and removing the sacrificial layer during an etching process. The etching process further includes peeling the epitaxial material from the substrate while forming an etch crevice therebetween and bending the support handle to form compression in the epitaxial material during the etching process. In one example, the non-uniform support handle contains a wax film having a varying thickness.

Abstract: Methods for electrodepositing germanium on various semiconductor substrates such as Si, Ge, SiGe, and GaAs are provided. The electrodeposited germanium can be formed as a blanket or patterned film, and may be crystallized by solid phase epitaxy to the orientation of the underlying semiconductor substrate by subsequent annealing. These plated germanium layers may be used as the channel regions of high-mobility channel field effect transistors (FETs) in complementary metal oxide semiconductor (CMOS) circuits.

Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.

Abstract: A method for photoelectrochemical (PEC) etching of a p-type semiconductor layer simply and efficiently, by providing a driving force for holes to move towards a surface of a p-type cap layer to be etched, wherein the p-type cap layer is on a heterostructure and the heterostructure provides the driving force from an internal bias generated internally in the heterostructure; generating electron-hole pairs in a separate area of the heterostructure than the surface to be etched; and using an etchant solution to etch the surface of the p-type layer.

Abstract: This semiconductor photodetector consists of a diode with at least two heterojunctions comprising two external layers, a first layer with a given kind or type of doping and a second layer with a kind or type of doping opposite to that of the first layer, the bandgap width of these two layers being determined as a function of the energy and hence the wavelength or wavelength band that they are each intended to detect, these two layers being separated from each other by an intermediate layer having the same kind or type of doping as one of said first and second layers, said diode being subjected to a bias voltage of adjustable value between the two external layers. The bandgap width of the intermediate layer is greater than that of the layer that has the same type of doping as layer.

Abstract: A semiconductor device includes: a semiconductor base; a hetero semiconductor region which is in contact with the semiconductor base and which has a band gap different from that of the semiconductor base; a first electrode connected to the hetero semiconductor region; and a second electrode forming an ohmic contact to the semiconductor base. The hetero semiconductor region includes a laminated hetero semiconductor region formed by laminating a plurality of semiconductor layers in which crystal alignment is discontinuous at a boundary between at least two layers.

Abstract: A process for fabricating a multilayer structure is provided as well as the structure itself. In accordance with one embodiment, the process includes growing a growth layer on a silicon substrate by epitaxial growth, forming at least one pattern from the growth layer, depositing an oxide layer on the silicon substrate, transferring a silicon active layer onto the oxide layer, forming a cavity in the silicon active layer oxide layer above the pattern, and growing a III-V material in the cavity.

Abstract: A semiconductor light-emitting device includes: a substrate; a first conductivity type layer formed on the substrate and including a plurality of group III-V nitride semiconductor layers of a first conductivity type; an active layer formed on the first conductivity type layer; and a second conductivity type layer formed on the active layer and including a group III-V nitride semiconductor layer of a second conductivity type. The first conductivity type layer includes an intermediate layer made of AlxGa1?x?yInyN (wherein 0.001?x<0.1, 0<y<1 and x+y<1).

Abstract: A nitride-based compound semiconductor substrate mainly used for an epitaxial growth of a nitride semiconductor and a method for fabricating the same are disclosed. The nitride-based compound semiconductor substrate has a composition of AlxGa1-xN (0<x<1), a principal plane of C face, an area of 2 cm2 or more, and a thickness of 200 ?m or more. The substrate having this structure is fabricated by a HVPE (hydride vapor phase epitaxy) method by using an organic Al compound such as TMA (trimethyl aluminum) or TEA (trimethyl aluminum) as an Al source, A stable crystal growth can be obtained without damaging a reacting furnace, and a large-sized AlGaN crystal substrate with an excellent crystallinity can be obtained.

Abstract: A method of forming a virtually defect free lattice mismatched nanoheteroepitaxial layer is disclosed. The method includes forming an interface layer on a portion of a substrate. A plurality of seed pads are then formed by self-directed touchdown by exposing the interface layer to a material comprising a semiconductor material. The plurality of seed pads, having an average width of about 1 nm to 10 nm, are interspersed within the interface layer and contact the substrate. An epitaxial layer is then formed by lateral growth of the seed pads over the interface layer.

Abstract: A method for making a free-standing, single crystal, aluminum gallium nitride (AlGaN) wafer includes forming a single crystal AlGaN layer directly on a single crystal LiAlO2 substrate using an aluminum halide reactant gas, a gallium halide reactant gas, and removing the single crystal LiAlO2 substrate from the single crystal AlGaN layer to make the free-standing, single crystal AlGaN wafer. Forming the single crystal AlGaN layer may comprise depositing AlGaN by vapor phase epitaxy (VPE) using aluminum and gallium halide reactant gases and a nitrogen-containing reactant gas. The growth of the AlGaN layer using VPE provides commercially acceptable rapid growth rates. In addition, the AlGaN layer can be devoid of carbon throughout. Because the AlGaN layer produced is high quality single crystal, it may have a defect density of less than about 107cm?2.

Abstract: InP epitaxial material is directly bonded onto a Silicon-On-Insulator (SOI) wafer having Vertical Outgassing Channels (VOCs) between the bonding surface and the insulator (buried oxide, or BOX) layer. H2O and other molecules near the bonding surface migrate to the closest VOC and are quenched in the buried oxide (BOX) layer quickly by combining with bridging oxygen ions and forming pairs of stable nonbridging hydroxyl groups (Si—OH). Various sizes and spacings of channels are envisioned for various devices.

Abstract: One-dimensional nanostructures having uniform diameters of less than approximately 200 nm. These inventive nanostructures, which we refer to as “nanowires”, include single-crystalline homostructures as well as heterostructures of at least two single-crystalline materials having different chemical compositions. Because single-crystalline materials are used to form the heterostructure, the resultant heterostructure will be single-crystalline as well. The nanowire heterostructures are generally based on a semiconducting wire wherein the doping and composition are controlled in either the longitudinal or radial directions, or in both directions, to yield a wire that comprises different materials. Examples of resulting nanowire heterostructures include a longitudinal heterostructure nanowire (LOHN) and a coaxial heterostructure nanowire (COHN).

Abstract: Semiconductor-on-diamond (SOD) substrates and methods for making such substrates are provided. In one aspect, a method of making an SOD substrate may include depositing a base layer onto a lattice-orienting silicon (Si) substrate such that the base layer lattice is substantially oriented by the Si substrate, depositing a semiconductor layer onto the base layer such that the semiconductor layer lattice is substantially oriented with respect to the base layer lattice, and disposing a layer of diamond onto the semiconductor layer. The base layer may include numerous materials, including, without limitation, aluminum phosphide (Alp), boron arsenide (BAs), gallium nitride (GaN), indium nitride (InN), and combinations thereof. Additionally, the method may further include removing the lattice-orienting Si substrate and the base layer from the semiconductor layer. In one aspect, the Si substrate may be of a single crystal orientation.