Multiple Layers Patents (Class 257/635)
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Patent number: 6936533Abstract: A method of fabricating a semiconductor device having a low dielectric constant is disclosed. According to the method, a silicon oxycarbide layer is formed, treated with plasma, and patterned. The silicon oxycarbide layer is formed by a coating method or a CVD method such as a PECVD method. Treating the silicon oxycarbide layer with plasma is performed by supplying at least one gas selected from a group of He, H2, N2O, NH3, N2, O2 and Ar. It is desirable that plasma be applied at the silicon oxycarbide layer in a PECVD device by an in situ method after forming the silicon oxycarbide layer. In a case in which a capping layer is further stacked and patterned, it is desirable to treat with H2-plasma. Even in a case in which an interlayer insulation is formed of the silicon oxycarbide layer and a coating layer of an organic polymer group for a dual damascene process, it is desirable to perform the plasma treatment before forming the coating layer.Type: GrantFiled: November 27, 2001Date of Patent: August 30, 2005Assignee: Samsung Electronics, Co., Ltd.Inventors: Jae-Hak Kim, Hong-Jae Shin, Soo-Geun Lee, Kyoung-Woo Lee
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Patent number: 6921937Abstract: The present invention provides a flash memory integrated circuit and a method of fabricating the same. A tunnel dielectric in an erasable programmable read only memory (EPROM) device is nitrided with a hydrogen-bearing compound, particularly ammonia. Hydrogen is thus incorporated into the tunnel dielectric, along with nitrogen. The gate stack is etched and completed, including protective sidewall spacers and dielectric cap, and the stack lined with a barrier to hydroxyl and hydrogen species. Though the liner advantageously reduces impurity diffusion through to the tunnel dielectric and substrate interface, it also reduces hydrogen diffusion in any subsequent hydrogen anneal. Hydrogen is provided to the tunnel dielectric, however, in the prior exposure to ammonia.Type: GrantFiled: March 3, 2003Date of Patent: July 26, 2005Assignee: Micron Technology, Inc.Inventor: Ronald A. Weimer
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Patent number: 6919617Abstract: There is disclosed a semiconductor device comprising a first metal wiring buried in a first wiring groove formed, via a first barrier metal, in a first insulating layer formed on a semiconductor substrate, a second insulating layer formed on the first metal wiring, a via plug formed of a metal buried, via a second barrier metal, in a via hole formed in the second insulating layer, a third insulating layer formed on the second insulating layer in which the via plug is buried, and a second metal wiring buried in a second wiring groove formed in the third insulating layer via a third barrier metal having a layer thickness of layer quality different from that of the second barrier metal.Type: GrantFiled: June 17, 2003Date of Patent: July 19, 2005Assignee: Kabushiki Kaisha ToshibaInventors: Masaki Yamada, Hideki Shibata
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Patent number: 6917110Abstract: A semiconductor device capable of inhibiting a conductive plug from increase of resistance or disconnection resulting from moisture discharged from a first insulator film while reducing the capacitance between adjacent first interconnection layers is obtained. This semiconductor device comprises a plurality of first interconnection layers formed on a semiconductor substrate at a prescribed interval, a first insulator film, formed to fill up the clearance between the plurality of first interconnection layers, having an opening reaching the first interconnection layers and a conductive plug charged in the opening of the first insulator film and formed to be in contact with the first interconnection layers. An impurity is selectively introduced into a first region of the first insulator film in the vicinity of contact surfaces between the first interconnection layers and the conductive plug, thereby selectively modifying the first region of the first insulator film.Type: GrantFiled: December 5, 2002Date of Patent: July 12, 2005Assignee: Sanyo Electric Co., Ltd.Inventors: Naoteru Matsubara, Hideki Mizuhara, Takashi Goto
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Patent number: 6913814Abstract: A lamination process and structure of a high layout density substrate is disclosed. The lamination process comprises the following steps. First of all, a plurality of laminating layers are individually formed, wherein each laminating layer has a first dielectric layer, a plurality of first vias and a patterned conducting layer. Next, a bottom layer having a second dielectric layer and a plurality of second vias is formed. Then, the laminating layers and the bottom layer are stacked. Finally, the laminating layers and the bottom layer are laminated simultaneously to form a multiplayer substrate at one time.Type: GrantFiled: November 19, 2003Date of Patent: July 5, 2005Assignee: Via Technologies, Inc.Inventors: Kwun Yao Ho, Moriss Kung
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Patent number: 6906350Abstract: The present invention provides a unit cell of a metal-semiconductor field-effect transistor (MESFET). The unit cell of the MESFET includes a delta doped silicon carbide MESFET having a source, a drain and a gate. The gate is situated between the source and the drain and extends into a doped channel layer of a first conductivity type. Regions of silicon carbide adjacent to the source and the drain extend between the source and the gate and the drain and the gate, respectively. The regions of silicon carbide have carrier concentrations that are greater than a carrier concentration of the doped channel layer and are spaced apart from the gate.Type: GrantFiled: October 24, 2001Date of Patent: June 14, 2005Assignee: Cree, Inc.Inventor: Saptharishi Sriram
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High permeability thin films and patterned thin films to reduce noise in high speed interconnections
Patent number: 6906402Abstract: This invention provides a structure and method for improved transmission line operation on integrated circuits. One method of the invention includes forming transmission lines in an integrated circuit. The method includes forming a first layer of electrically conductive material on a substrate. A first layer of insulating material is formed on the first layer of the electrically conductive material. A pair of high permeability metal lines are formed on the first layer of insulating material. The pair of high permeability metal lines include permalloy and/or Ni45Fe55 films. A transmission line is formed on the first layer of insulating material and between and parallel with the pair of high permeability metal lines. A second layer of insulating material is formed on the transmission line and the pair of high permeability metal lines. And, the method includes forming a second layer of electrically conductive material on the second layer of insulating material.Type: GrantFiled: February 20, 2003Date of Patent: June 14, 2005Assignee: Micron Technology Inc.Inventors: Leonard Forbes, Kie Y. Ahn, Salman Akram -
High permeability thin films and patterned thin films to reduce noise in high speed interconnections
Patent number: 6903444Abstract: This invention provides a structure and method for improved transmission line operation on integrated circuits. One method of the invention includes forming transmission lines in an integrated circuit. The method includes forming a first layer of electrically conductive material on a substrate. A first layer of insulating material is formed on the first layer of the electrically conductive material. A pair of high permeability metal lines are formed on the first layer of insulating material. The pair of high permeability metal lines include permalloy and/or Ni45Fe55 films. A transmission line is formed on the first layer of insulating material and between and parallel with the pair of high permeability metal lines. A second layer of insulating material is formed on the transmission line and the pair of high permeability metal lines. And, the method includes forming a second layer of electrically conductive material on the second layer of insulating material.Type: GrantFiled: February 20, 2003Date of Patent: June 7, 2005Assignee: Micron Technology Inc.Inventors: Leonard Forbes, Kie Y. Ahn, Salman Akram -
Patent number: 6888224Abstract: Low-k dielectric materials have desirable insulating characteristics for use in insulating sub micron conductors in semiconductor devices. However, certain physical and material characteristics of the low-k dielectric materials make them difficult to work with. More particularly, the soft, porous, leakage-prone characteristics of low-k materials makes it difficult to accommodate electrical contacts for electrical probing to conductors covered by such materials. The present invention provides methods and structures for facilitating the electrical probing of semiconductor device conductors insulated by overlying low-k layers of dielectric material.Type: GrantFiled: June 30, 2003Date of Patent: May 3, 2005Assignee: International Business Machines CorporationInventors: Terence Lawrence Kane, Michael P. Tenney
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Patent number: 6867453Abstract: A method of forming a memory device, where a first insulator layer and a charge trapping layer may be formed on a substrate, and at least one of the first insulator layer and charge trapping layer may be patterned to form patterned areas. A second insulation layer and a conductive layer may be formed on the patterned areas, and one or more of the conductive layer, second insulator layer, charge trapping layer and first insulator layer may be patterned to form a string selection line, ground selection line, a plurality of word lines between the string selection and ground selection lines on the substrate, a low voltage gate electrode, and a plurality of insulators of varying thickness. The formed memory device may be a NAND-type non-volatile memory device having a SONOS gate structure, for example.Type: GrantFiled: March 7, 2003Date of Patent: March 15, 2005Assignee: Samsung Electronics Co., Ltd.Inventors: Yoo-cheol Shin, Jeong-Hyuk Choi, Sung-Hoi Hur
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Patent number: 6864181Abstract: A planarized conductive material is formed over a substrate including narrow and wide features. The conductive material is formed through a succession of deposition processes. A first deposition process forms a first layer of the conductive material that fills the narrow features and at least partially fills the wide features. A second deposition process forms a second layer of the conductive material within cavities in the first layer. A flexible material can reduce a thickness of the first layer above the substrate while delivering a solution to the cavities to form the second layer therein. The flexible material can be a porous membrane attached to a pressurizable reservoir filled with the solution. The flexible material can also be a poromeric material wetted with the solution.Type: GrantFiled: March 27, 2003Date of Patent: March 8, 2005Assignee: Lam Research CorporationInventors: Fred C. Redeker, John Boyd
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Patent number: 6858937Abstract: A semiconductor device and a method of making it are described. During the formation of the semiconductor device, a hard mask is formed of an etch-resistant material. The mask prevents etchant from etching an area within a dielectric material near a conductive plug. The mask may be formed of a nitride. Conductive material is then deposited withinan etched via and is contacted with the conductive plug.Type: GrantFiled: March 2, 2000Date of Patent: February 22, 2005Assignee: Micron Technology, Inc.Inventor: Chih-Chen Cho
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Patent number: 6853054Abstract: A high frequency semiconductor device including wiring layers which are formed above a semiconductor substrate and in which transmission lines are formed by combining with a ground plate having a potential fixed at the ground potential, at least one crossing portion in which the wiring layers mutually cross, with insulating interlayers provided therebetween, and at least one separation electrode being selectively provided on one of the insulating interlayers, the at least one separation electrode having a potential fixed at the ground potential. Accordingly, in the high frequency semiconductor device, electrical interference between two crossing wiring layer is prevented and transmission loss is suppressed.Type: GrantFiled: February 21, 2002Date of Patent: February 8, 2005Assignee: Fujitsu Quantum Devices LimitedInventors: Osamu Baba, Yutaka Mimino
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Patent number: 6849924Abstract: A multilayer switching assembly for switching high frequency signals has MEMS structures on a ceramic substrate having a top surface, a bottom surface and a plurality of insulating layers. The insulating layers are separated by a first conductor and a second conductor. The first conductor is connected to a ground potential. The second conductor is separated from the first conductor by one of the insulating layers. The second conductor presents a specific impedance (50 ohms) with respect to the first conductor to high frequency signals traveling on the second conductor. 64 MEMS structures are mounted on the top surface. Each MEMS has an input, an output, and a control. The input connected to the second conductor. The output is connected to a coplanar waveguide placed on the top surface. The control is connected to the bottom surface. The input to each MEMS is electrically shielded from the output and from the control by a third conductor connected to the first (grounded) conductor.Type: GrantFiled: May 9, 2002Date of Patent: February 1, 2005Assignee: Raytheon CompanyInventors: Robert C. Allison, Jar J. Lee
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Patent number: 6849925Abstract: A semiconductor device having a composite dielectric layer, including a semiconductor substrate, alternating sub-layers including a first dielectric material and a second dielectric material on the semiconductor substrate, the sub-layers forming a composite dielectric layer having at least two sub-layers of at least one of the first dielectric material and the second dielectric material, in which one of the first dielectric material and the second dielectric material is a high-K dielectric material and an other of the first dielectric material and the second dielectric material is a standard-K dielectric material comprising aluminum oxide; and the composite dielectric layer includes a reaction product of the high-K dielectric material and the standard-K dielectric material. In one embodiment, the composite dielectric layer includes a substantially uniform layer of the reaction product of the first dielectric material and the second dielectric material.Type: GrantFiled: September 5, 2003Date of Patent: February 1, 2005Assignee: Advanced Micro Devices, Inc.Inventors: Arvind Halliyal, Joong S. Jeon, Minh Van Ngo, Robert B. Ogle
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Patent number: 6849923Abstract: Disclosed is a semiconductor device, comprising a first wiring structure formed on a semiconductor substrate and including a first plug and a first wiring formed on the first plug, and a second wiring structure formed on the semiconductor substrate belonging to the wiring layer equal to the first wiring structure and including a second plug and a second wiring formed on the second plug, wherein the upper surface of the first wiring is positioned higher than the upper surface of the second wiring, and the lower surface of the first wiring is positioned flush with or lower than the upper surface of the second wiring. The present invention also provides a method of manufacturing the particular semiconductor device.Type: GrantFiled: March 4, 2002Date of Patent: February 1, 2005Assignee: Kabushiki Kaisha ToshibaInventors: Shoji Seta, Makoto Sekine, Naofumi Nakamura
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Patent number: 6844612Abstract: A fluorine-doped silica glass (FSG) dielectric layer includes a number of sublayers. Each sublayer is doped with fluorine in such a way that the doping concentration of fluorine in the sublayer decreases as one moves from an interior region of the sublayer towards one or both of the interfaces between the sublayer and adjacent sublayers. This structure reduces the generation of HF when the layer is exposed to moisture and thereby improves the stability and adhesion properties of the layer. The principles of this invention can also be applied to dielectric layers doped with such other dopants as boron, phosphorus or carbon.Type: GrantFiled: April 29, 2003Date of Patent: January 18, 2005Assignee: Novellus Systems, Inc.Inventors: Jason Tian, Wenxian Zhu, M. Ziaul Karim, Cong Do
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Patent number: 6841850Abstract: A semiconductor device of this invention includes a silicon nitride film formed on a semiconductor substrate and having a density of 2.2 g/cm3 or less, and a silicon oxide film formed on the silicon nitride film in an ambient atmosphere containing TEOS and O3.Type: GrantFiled: September 6, 2002Date of Patent: January 11, 2005Assignee: Kabushiki Kaisha ToshibaInventors: Susumu Hiyama, Akihito Yamamoto, Hiroshi Akahori, Shigehiko Saida
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Patent number: 6838750Abstract: An electrical circuit having one or more dielectric layers formed of latex; and one or more layers of electrically conductive material, such as copper, patterned to form multiple electrical interconnects, with each such layer placed on top of one of said dielectric layers. The dielectric and conductive layers can be used to connect multiple chips in a multichip module. The latex layers can be formed to have a top surface that contains peaks and valleys, and the conductive layers can be formed of a first metal that substantially fills such valleys, so as to increase the adherence of the metal to the latex surface. The layers of conductive metal can contain particles of a second metal between said peaks and valleys of the latex layer that were used as a catalytic seed particles to promote the deposition of the metal layer onto the top surface of the latex.Type: GrantFiled: July 12, 2001Date of Patent: January 4, 2005Assignee: Custom One Design, Inc.Inventors: Peter R. Nuytkens, Ilya E. Popeko, Joseph M. Kulinets
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Publication number: 20040258932Abstract: The present invention provides a technique to reduce a stress of thick spin-on dielectric layer by forming a sandwich dielectric structure, wherein a first dielectric layer is formed on a substrate by spin coating, a liquid phase deposited (LPD) silica layer is formed the first dielectric layer, and a second dielectric layer is formed on the LPD silica layer by spin coating. The LPD silica layer can be further subjected to a nitrogen plasma treatment to enhance its thermal stability and anti-water penetration ability.Type: ApplicationFiled: July 19, 2004Publication date: December 23, 2004Applicant: National Science CouncilInventors: Ching-Fa Yeh, Yueh-Chuan Lee, Chih-Chuan Hsu, Kwo-Hau Wu, Shuo-Cheng Wang
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Patent number: 6833604Abstract: An electronic structure having a first conductive layer provided by a dual damascene fabrication process; an etch-stop layer provided by the fabrication process, and electrically coupled with the first conductive layer, the etch-stop layer having a preselected dielectric constant and a predetermined geometry; and a second conductive layer, electrically coupled with the etch-stop layer. The structure can be, for example, a metal-insulator-metal capacitor, an antifuse, and the like.Type: GrantFiled: October 3, 2001Date of Patent: December 21, 2004Assignee: Broadcom CorporationInventor: Liming Tsau
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Patent number: 6831366Abstract: A low-k dielectric metal conductor interconnect structure having no micro-trenches present therein and a method of forming such a structure are provided. Specifically, the above structure is achieved by providing an interconnect structure which includes at least a multilayer of dielectric materials which are applied sequentially in a single spin apply tool and then cured in a single step and a plurality of patterned metal conductors within the multilayer of spun-on dielectrics. The control over the conductor resistance is obtained using a buried etch stop layer having a second atomic composition located between the line and via dielectric layers of porous low-k dielectrics having a first atomic composition. The inventive interconnect structure also includes a hard mask which assists in forming the interconnect structure of the dual damascene-type.Type: GrantFiled: March 25, 2003Date of Patent: December 14, 2004Assignee: International Business Machines CorporationInventors: Stephen McConnell Gates, Jeffrey Curtis Hedrick, Satyanarayana V. Nitta, Sampath Purushothaman, Cristy Sensenich Tyberg
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Publication number: 20040245606Abstract: An interconnect structure for microelectronic devices includes a plurality of patterned, spaced apart, substantially co-planar, conductive lines, a first portion of the plurality of conductive lines having a first intralayer dielectric of a first dielectric constant therebetween, and a second portion of the plurality of conductive lines having a second intralayer dielectric of a second dielectric constant therebetween. By providing in-plane selectability of dielectric constant, in-plane decoupling capacitance, as between power supply nodes, can be increased, while in-plane parasitic capacitance between signal lines can be reduced.Type: ApplicationFiled: July 13, 2004Publication date: December 9, 2004Inventors: Chien Chiang, David B. Fraser
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Patent number: 6822333Abstract: According to one embodiment (500), a method of depositing an insulating layer to fill constrained spaces on an integrated circuit is disclosed. Gate structures are formed that include sidewall structures (502 and 504). An insulating layer may then be deposited over the gate structures (506). An insulating layer may be deposited by high density plasma CVD to create a silicon dioxide layer with relatively high levels of phosphorous. An insulating layer formed in this manner may fill constrained spaces and may not include a following reflow step. This may allow for a smaller thermal budget and may reduce process complexity and/or cycle time. In the event the insulating layer is substantially phosphosilicate glass (PSG), the formation of a “cap” layer of undoped silicon oxide may be avoided. Without a cap layer, contact holes may be etched through an insulating layer with a single etch step. This may also reduce process complexity and/or cycle time.Type: GrantFiled: September 12, 2001Date of Patent: November 23, 2004Assignee: Cypress Semiconductor CorporationInventor: Jengyi Yu
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Publication number: 20040227214Abstract: A method, apparatus and system are provided for relieving stress in the via structures of semiconductor structures whenever a linewidth below a via is larger than a ground-rule, including providing a via at least as large as the groundrule, providing a landing pad above the via, providing a via bar in place of a via, slotting the metal linewidth below the via, or providing an oversize via with a sidewall spacer.Type: ApplicationFiled: May 16, 2003Publication date: November 18, 2004Inventors: Mark Hoinkis, Matthias Hierlemann, Gerald Friese, Andy Cowley, Dennis J. Warner, Erdem Kaltalioglu
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Patent number: 6815367Abstract: A process of eliminating resist footing on a hardmask when preparing a semiconductor wafer stack, comprising: a) depositing a layer of hardmask material on a substrate; b) subjecting the hardmask to oxygen under conditions sufficient to produce an oxide cap layer and provide a hardmask/oxide cap layer with a substrate reflectivity below 0.8%; c) forming a layer of SiO2 on the hardmask/oxide cap layer; d) forming a layer of photoresist on the layer of SiO2; e) patterning and developing the layer of photoresist by exposing photoresist; and f) etching exposed portions of the layer of hardmask/oxide cap layer/SiO2 layer to obtain a semiconductor wafer stack with no standing waves and free from resist footing.Type: GrantFiled: April 3, 2002Date of Patent: November 9, 2004Assignee: Infineon Technologies AGInventor: Xiaochun Linda Chen
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Patent number: 6815805Abstract: The present invention provides a flash memory integrated circuit and a method of fabricating the same. A tunnel dielectric in an erasable programmable read only memory (EPROM) device is nitrided with a hydrogen-bearing compound, particularly ammonia. Hydrogen is thus incorporated into the tunnel dielectric, along with nitrogen. The gate stack is etched and completed, including protective sidewall spacers and dielectric cap, and the stack lined with a barrier to hydroxyl and hydrogen species. Though the liner advantageously reduces impurity diffusion through to the tunnel dielectric and substrate interface, it also reduces hydrogen diffusion in any subsequent hydrogen anneal. Hydrogen is provided to the tunnel dielectric, however, in the prior exposure to ammonia.Type: GrantFiled: January 15, 2004Date of Patent: November 9, 2004Assignee: Micron Technology, Inc.Inventor: Ronald A. Weimer
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Patent number: 6812572Abstract: An etch-stop layer is selectively provided between layers of a multiple-layered circuit in a selective manner so as to allow for outgassing of impurities during subsequent fabrication processes. The etch-stop layer is formed over an underlying stud so as to serve as an alignment target during formation of an overlying stud formed in an upper layer. In this manner multiple-layered circuits, for example memory devices, can be fabricated in relatively dense configurations.Type: GrantFiled: May 21, 2003Date of Patent: November 2, 2004Assignee: Samsung Electronics Co., Ltd.Inventors: Won-Suk Yang, Sang-Ho Song, Hong-Sik Jeong, Ki-Nam Kim
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Patent number: 6806576Abstract: An exemplary implementation of the invention is a process for forming passivation protection on a semiconductor assembly by the steps of: forming a layer of oxide over patterned metal lines having sidewalls; forming a first passivation layer of silicon nitride over the layer of oxide such that the first passivation layer of silicon nitride resides along the sidewalls of metal lines and pinches off a gap between the metal lines; performing a facet etch to remove material from the edges of the first passivation layer of silicon nitride and re-deposits some of removed material across a pinch-off junction; forming a second passivation layer of silicon nitride on the first passivation layer of silicon nitride.Type: GrantFiled: April 9, 2003Date of Patent: October 19, 2004Assignee: Micron Technology, Inc.Inventors: Philip J. Ireland, James E. Green
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Patent number: 6798065Abstract: Method and apparatus for plasma etching both metal and inorganic dielectric layers in a single chamber during deep sub-micron semiconductor fabrication. Fluorine based chemistries, or a mixture of fluorine and chlorine based chemistries, are used to etch the inorganic dielectric layer. A switch is then made to chlorine based chemistries, within the same etching chamber, which are utilized to etch the metal layer. Overetching may also be performed with chlorine based chemistries to clear any residuals.Type: GrantFiled: September 19, 2001Date of Patent: September 28, 2004Assignee: Newport Fab, LLCInventors: Shao-Wen Hsia, Michael J. Berg, Maureen R. Brongo
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Publication number: 20040183162Abstract: A semiconductor device has a semiconductor substrate, and a multi-layered wiring arrangement provided thereon. The multi-layered wring arrangement includes at least one insulating layer structure having a metal wiring pattern formed therein. The insulating layer structure includes a first SiOCH layer, a second SiOCH layer formed on the first SiOCH layer, and a silicon dioxide (SiO2) layer formed on the second SiOCH layer. The second SiOCH layer features a carbon (C) density lower than that of the first SiOCH layer, a hydrogen (H) density lower than that of the first SiOCH layer, and an oxygen (O) density higher than that of the first SiOCH layer.Type: ApplicationFiled: January 29, 2004Publication date: September 23, 2004Applicant: NEC Electronics CorporationInventors: Koichi Ohto, Tatsuya Usami, Noboru Morita, Sadayuki Ohnishi, Koji Arita, Ryohei Kitao, Yoichi Sasaki
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Patent number: 6794733Abstract: In integrated circuit that yields the advantages of contemporary processing technologies and yet is irreparably damaged by ionizing radiation. An integrated circuit is designed and fabricated with contemporary processing technologies in well-known fashion, except that certain devices, called “safeguard” devices, are added to the integrated circuit. The safeguard devices are fabricated so that they, and not the other devices on the integrated circuit, are susceptible to ionizing radiation. Furthermore, the safeguard devices are coupled to the utile devices on the integrated circuit in such a manner than when the integrated circuit is bombarded with ionizing radiation the safeguard devices short and destroy the functionality of the utile devices, and, therefore, the functionality of the integrated circuit.Type: GrantFiled: June 9, 2000Date of Patent: September 21, 2004Assignee: BAE SystemsInventors: Frederick T. Brady, Murty S. Polavarapu
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Patent number: 6794681Abstract: There are provided a substrate of a semiconductor device and a fabrication method thereof which allow to suppress impurity from turning around from a glass or quartz substrate in fabrication steps of a TFT. An insulating film is deposited so as to surround the glass substrate by means of reduced pressure thermal CVD. It allows to suppress the impurity from infiltrating from the glass substrate to an active region of the TFT in the later process.Type: GrantFiled: September 14, 2001Date of Patent: September 21, 2004Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Setsuo Nakajima, Shunpei Yamazaki, Hisashi Ohtani, Satoshi Teramoto, Toshiji Hamatani
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Patent number: 6791164Abstract: A stereolithographically fabricated package that surrounds at least a portion of a semiconductor die so as to substantially hermetically seal the same. The package may be fabricated from thermoplastic glass, other types of glass, ceramics, or metals. Stereolithographic processes are used to fabricate at least a portion of the substantially hermetic package around the semiconductor dice of assemblies including carrier substrates or leads or around bare or minimally packaged semiconductor dice, including on dice that have yet to be singulated from a wafer. As at least a portion of the substantially hermetic package is stereolithographically fabricated, that portion may include a series of superimposed, contiguous, mutually adhered layers of a suitable hermetic material. The layers can be fabricated by consolidated selected regions of a layer of unconsolidated particulate or powdered material, or by defining an object layer from a sheet of material.Type: GrantFiled: January 9, 2002Date of Patent: September 14, 2004Assignee: Micron Technology, Inc.Inventor: Warren M. Farnworth
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Patent number: 6787886Abstract: A semiconductor device includes a semiconductor substrate which has a major surface and a MOS transistor which has a gate and first and second diffusion regions and which is formed on the major surface. The semiconductor device also includes a laminated structure of a SOG layer, wherein the laminated structure is composed of a base layer and a surface layer formed on the base layer and is formed over the MOS transistor and wherein the surface layer is denser than the base layer.Type: GrantFiled: February 4, 2000Date of Patent: September 7, 2004Assignee: Oki Electric Industry Co., Ltd.Inventors: Kazuhiko Asakawa, Wataru Shimizu
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Patent number: 6784485Abstract: A semiconductor device containing a diffusion barrier layer is provided. The semiconductor device includes at least a semiconductor substrate containing conductive metal elements; and, a diffusion barrier layer applied to at least a portion of the substrate in contact with the conductive metal elements, the diffusion barrier layer having an upper surface and a lower surface and a central portion, and being formed from silicon, carbon, nitrogen and hydrogen with the nitrogen being non-uniformly distributed throughout the diffusion barrier layer. Thus, the nitrogen is more concentrated near the lower and upper surfaces of the diffusion barrier layer as compared to the central portion of the diffusion barrier layer. Methods for making the semiconductor devices are also provided.Type: GrantFiled: February 11, 2000Date of Patent: August 31, 2004Assignee: International Business Machines CorporationInventors: Stephan Alan Cohen, Timothy Joseph Dalton, John Anthony Fitzsimmons, Stephen McConnell Gates, Lynne M. Gignac, Paul Charles Jamison, Kang-Wook Lee, Sampath Purushothaman, Darryl D. Restaino, Eva Simonyi, Horatio Seymour Wildman
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Patent number: 6784547Abstract: A pre-formed integrated circuit chip is encapsulated into an electronic package, by forming an interconnect assembly separately from the pre-formed integrated circuit chip. If the interconnect assembly tests good it is bonded to the prepared integrated circuit chip. The interconnect assembly is flip bonded to the chip. The interconnect assembly and chip are passivated or potted into an integral structure to provide the electronic package. At least one test pad is defined in an interconnect layer, which test pad can be accessed and electrically connected on opposing sides of the test pad. The chip is underfilled with an insulating material to remove all voids between the chip and the interconnect assembly. The integrated circuit chip is then thinned. The test pad is accessed to test the chip. A plurality of interconnect assemblies and chips are bonded together to form a corresponding plurality of electronic packages.Type: GrantFiled: November 21, 2002Date of Patent: August 31, 2004Assignee: Irvine Sensors CorporationInventors: Angel Antonio Pepe, James Satsuo Yamaguchi
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Patent number: 6781235Abstract: An interconnect structure, which can have three-levels, is formed by a metallization method in an electrical circuit. The method comprises providing a substrate assembly and depositing thereon a first dielectric layer thereover. A second dielectric layer is then deposited over the first dielectric layer. The second dielectric layer is patterned and anisotropically etched to form contact corridors. The second dielectric layer is again patterned and etched to form trenches, some of which are immediately above the contact corridors. An electrically conductive material is deposited to fill the contact corridors and trenches, and to leave a portion of the electrically conductive material above the second dielectric layer and directly above both the contact corridors and the trenches. The deposition forms a unitary three-level interconnect having a contiguous trench below a contact corridor below a metal line, where the metal line is above the second dielectric layer.Type: GrantFiled: May 5, 2000Date of Patent: August 24, 2004Assignee: Micron Technology, Inc.Inventor: John H. Givens
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Patent number: 6774461Abstract: The present invention provides a technique to reduce a stress of thick spin-on dielectric layer by forming a sandwich dielectric structure, wherein a first dielectric layer is formed on a substrate by spin coating, a liquid phase deposited (LPD) silica layer is formed the first dielectric layer, and a second dielectric layer is formed on the LPD silica layer by spin coating. The LPD silica layer can be further subjected to a nitrogen plasma treatment to enhance its thermal stability and anti-water penetration ability.Type: GrantFiled: February 15, 2002Date of Patent: August 10, 2004Assignee: National Science CouncilInventors: Ching-Fa Yeh, Yueh-Chuan Lee, Chih-Chuan Hsu, Kwo-Hau Wu, Shuo-Cheng Wang
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Publication number: 20040150067Abstract: A semiconductor structure and methods for fabricating are disclosed. In an implementation, a method of fabricating a semiconductor structure includes forming a first semiconductor material substrate with a first dielectric area having a first thickness and a second dielectric area having a second thickness, bonding the first substrate to a second semiconductor substrate, and thinning at least one of the first and second substrates. The invention also pertains to a semiconductor structure. The structure includes a semiconductor substrate having a surface layer of semiconductor material, a first dielectric layer of a first dielectric material buried under the surface layer, and a second dielectric layer buried under the surface layer. In an embodiment, the thickness of the first dielectric layer is different than the thickness of the second dielectric layer.Type: ApplicationFiled: November 12, 2003Publication date: August 5, 2004Inventors: Bruno Ghyselen, Oliver Rayssac, Cecile Aulnette, Carlos Mazure
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Publication number: 20040135234Abstract: A semiconductor device includes a substrate, MOS transistors in the substrate, and a dielectric layer on the MOS transistors. Contact holes are formed through the dielectric layer to provide electrical connection to the MOS transistors. An etch-stop layer is between the MOS transistors and the dielectric layer. The etch-stop layer includes a first layer of material having a first residual stress level and covers some of the MOS transistors, and a second layer of material having a second residual stress level and covers all of the MOS transistors. The respective thickness of the first and second layers of material, and the first and second residual stress levels associated therewith are selected to obtain variations in operating parameters of the MOS transistors.Type: ApplicationFiled: November 4, 2003Publication date: July 15, 2004Applicant: STMicroelectronics SAInventors: Pierre Morin, Jorge Luis Regolini
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Patent number: 6759333Abstract: A semiconductor device comprises a first conductor formed inside or on the top surface of a semiconductor substrate; an insulating film formed on the top surface of said semiconductor substrate or on the top surface of said first conductor; contact holes penetrating said insulating layer to reach said first conductor; a second conductor filled inside said contact holes and electrically connected to said first conductor; and an interconnection extending across contact regions on a top surface region of said insulating layer where said contact holes are formed respectively, and having opposite sides at least one of which is in contact with said second conductor inside said contact regions.Type: GrantFiled: September 10, 2002Date of Patent: July 6, 2004Assignee: Kabushiki Kaisha ToshibaInventor: Mutsumi Okajima
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Publication number: 20040124499Abstract: Semiconductor device structures and methods of making such structures that include one or more etched openings (e.g., capacitor containers and/or contact apertures) therein with increased height-to-width ratios are provided. The structures of the present invention are formed by successive layer deposition wherein conventional patterning techniques may be utilized in a stepwise fashion as the height of the structure is increased. Further provided is a self-aligning interconnection structure which may be used to substantially vertically align openings formed in successively deposited, vertically placed structural layers of a semiconductor device. The interconnection structure utilizes a cap-and-funnel model that self-aligns to the center plane of an opening in a first structural layer and also substantially prevents subsequently deposited material from entering the opening.Type: ApplicationFiled: December 26, 2002Publication date: July 1, 2004Inventor: Lingyi A. Zheng
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Patent number: 6753568Abstract: A memory device includes a memory node (1) to which charge is written through a tunnel barrier configuration (2) from a control electrode (9). The stored charge effects the conductivity of a source/drain path (4) and data is read by monitoring the conductivity of the path. The charge barrier configuration comprises a multiple tunnel barrier configuration, which may comprise alternating layers (16) of polysilicon of 3 nm thickness and layers (15) of Si3N4 of 1 nm thickness, overlying polycrystalline layer of silicon (1) which forms the memory node. Alternative barrier configurations (2) are described, including a Schottky barrier configuration, and conductive nanometer scale conductive islands (30, 36, 44), which act as the memory node, distributed in an electrically insulating matrix.Type: GrantFiled: July 28, 1999Date of Patent: June 22, 2004Assignee: Hitachi, LTD.Inventors: Kazuo Nakazato, Kiyoo Itoh, Hiroshi Mizuta, Toshihiko Sato, Toshikazu Shimada, Haroon Ahmed
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Patent number: 6747338Abstract: A method of manufacturing MEMS structures and devices that allows the fabrication of dielectric structures with improved etch selectivity and good electrical leakage characteristics. The dielectric structure includes a composite stack of silicon nitride sub-layers with a silicon-rich nitride sub-layer and a stoichiometric silicon nitride sub-layer at opposite ends of the stack. Alternatively, the dielectric structure includes a single silicon nitride layer providing a graded change in silicon content through the dielectric layer, from silicon-rich nitride to stoichiometric silicon nitride.Type: GrantFiled: November 27, 2002Date of Patent: June 8, 2004Assignee: Analog Devices, Inc.Inventors: Thomas K. Nunan, David E. Grosjean, Denis M. O'Kane, James S. Sellars
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Publication number: 20040104485Abstract: The semiconductor device comprises an interconnection layer 14 formed on a substrate 10, a cap insulation film 22 formed on the upper surface of the interconnection layer 14, and a sidewall insulation film which is formed on the side walls of the interconnection layer 14 and the cap insulation film 22 and which includes a larger layer number of insulation films 24, 26 28 covering the side wall of the interconnection layer 14 at the side wall of the cap insulation film 22 than a layer number of insulation films 24, 26 at the side wall of the cap insulation film 22. Accordingly, the sidewall insulation film can be thickened at the side wall of the interconnection layer 14, whereby a parasitic capacitance between the interconnection layer 14 and the electrodes 32 adjacent to the interconnection layer 14 through the sidewall insulation film can be low.Type: ApplicationFiled: November 12, 2003Publication date: June 3, 2004Applicant: FUJITSU LIMITEDInventor: Yuji Yokoyama
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Patent number: 6744116Abstract: A method for forming an integrated circuit is provided. A semiconductor film is formed onto a first substrate. A metal film is formed onto a second substrate. The second substrate is bonded with the metal film onto the thin film of the first substrate. A first layer of transistors is formed onto the film. The second substrate is removed at a temperature within a low temperature range. The semiconductor film is bonded with the first layer of transistors onto a second layer of transistors of a third substrate.Type: GrantFiled: October 8, 1999Date of Patent: June 1, 2004Assignee: Intel CorporationInventor: Brian S. Doyle
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Patent number: 6734036Abstract: The invention is a semiconductor device and method of fabricating the device. The device includes a semiconductor substrate with an active region, and a low dielectric constant insulating layer formed over the substrate. An additional insulating layer is formed over the low dielectric constant layer by a low temperature deposition, such as ion beam assistance deposition. A metal layer can then be formed over the additional layer using lift-off techniques. The metal layer can be patterned to form a bond pad which may be displaced from the area over the active region. Wire bonds can be made on the bond pad using ultrasonic energy.Type: GrantFiled: May 28, 2002Date of Patent: May 11, 2004Assignee: Agere Systems Inc.Inventors: Utpal Kumar Chakrabarti, Bora M Onat, Kevin Cyrus Robinson, Biswanath Roy, Ping Wu
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Patent number: 6731004Abstract: An electronic device and method of making same wherein the device includes a substrate (e.g., a printed wiring board or semiconductor chip) having a circuit thereon, a first non-photosensitive layer (e.g., polyimide resin) positioned on the substrate and over the substrate's circuit, a second, photosensitive layer (e.g., epoxy resin) positioned on the first layer, and an electrically conductive layer positioned on the first, non-photosensitive layer and electrically coupled to the circuit through a hole in the first layer.Type: GrantFiled: December 11, 2000Date of Patent: May 4, 2004Assignee: International Business Machines CorporationInventor: Kazuto Saitoh
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Patent number: 6723641Abstract: After forming a phosphor-doped amorphous silicon film and before forming a bottom silicon oxide film, a heat treatment is performed while exhausting a gas from the vicinity of the silicon substrate. The heat treatment is performed at a temperature equal to or higher than that for forming the bottom silicon oxide film and at a pressure equal to or lower than that for forming the bottom silicon oxide film. Alternatively, after forming the phosphor-doped amorphous silicon film and before forming the bottom silicon oxide film, a TEOS oxide film and a phosphor-doped amorphous silicon film deposited on the back surface of the silicon substrate are removed. Further alternatively, these films deposited on the back surface of the silicon substrate are covered with a film which prevents gas desorption under the film formation condition for the bottom silicon oxide film.Type: GrantFiled: June 4, 2002Date of Patent: April 20, 2004Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Kojiro Yuzuriha