Abstract: A semiconductor module includes a module package including a first substrate having a first semiconductor device and a second substrate having a second semiconductor device. A first outer conductor extends from the module package and is connected to the first substrate and a second outer conductor extends from the module package and is connected to the second substrate. A method for producing the semiconductor module includes attaching first outer conductors of a leadframe to a first substrate, where the first substrate includes a first semiconductor device that is attached to the first substrate either before or after attaching the first outer conductors. A second substrate is provided including a signal processing circuit and the second substrate is fastening to second outer conductors of the leadframe.

Abstract: There is disclosed a mounting technique for mounting a semiconductor chip of the leadless or so-called flip chip type to a header. The header has an insert made of glass or other suitable non-conductive material within the header hollow. Mounted into the glass insert are a series of conductive metal pins which are placed in areas so that when a chip is mounted in the header, the chip makes contact with these conductive pins and allows one to make outside connections. Also positioned in the header are a series of nonconductive guide pins. These pins are placed in suitable positions in the header to enable one to contact the outside surfaces of the chip when the chip is placed in the header. In this manner, the chip is constrained from movement from side to side or from rotation. However, due to the positioning of the nonconductive pins within the header, it is possible to move the chip up and down while mounting.

Abstract: Improved techniques to produce integrated circuit products are disclosed. The improved techniques permit smaller and less costly production of integrated circuit products. One aspect of the invention concerns covering test contacts (e.g., test pins) provided with the integrated circuit products using printed ink. Once covered with the ink, the test contacts are no longer electrically exposed. Hence, the integrated circuit products are not susceptible to accidental access or electrostatic discharge. Moreover, the integrated circuit products can be efficiently produced in a small form factor without any need for additional packaging or labels to electrically isolate the test contacts.

Abstract: Techniques are here disclosed for a solar cell pre-processing method and system for annealing and gettering a solar cell semiconductor wafer having an undesirably high dispersion of transition metals, impurities and other defects. The process forms a surface contaminant layer on the solar cell semiconductor (e.g., silicon) wafer. A surface of the semiconductor wafer receives and holds impurities, as does the surface contaminant layer. The lower-quality semiconductor wafer includes dispersed defects that in an annealing process getter from the semiconductor bulk to form impurity cluster toward the surface contaminant layer. The impurity clusters form within the surface contaminant layer while increasing the purity level in wafer regions from which the dispersed defects gettered. Cooling follows annealing for retaining the impurity clusters and, thereby, maintaining the increased purity level of the semiconductor wafer in regions from which the impurities gettered.

Abstract: The present invention generally provides apparatus and method for forming a clean and damage free surface on a semiconductor substrate. One embodiment of the present invention provides a system that contains a cleaning chamber that is adapted to expose a surface of substrate to a plasma cleaning process prior to forming an epitaxial layer thereon. In one embodiment, a method is employed to reduce the contamination of a substrate processed in the cleaning chamber by depositing a gettering material on the inner surfaces of the cleaning chamber prior to performing a cleaning process on a substrate. In one embodiment, oxidation and etching steps are repeatedly performed on a substrate in the cleaning chamber to expose or create a clean surface on a substrate that can then have an epitaxial placed thereon. In one embodiment, a low energy plasma is used during the cleaning step.

Abstract: This invention relates to materials and processes for thin film deposition on solid substrates. Silica/alumina nanolaminates were deposited on heated substrates by the reaction of an aluminum-containing compound with a silanol. The nanolaminates have very uniform thickness and excellent step coverage in holes with aspect ratios over 40:1. The films are transparent and good electrical insulators. This invention also relates to materials and processes for producing improved porous dielectric materials used in the insulation of electrical conductors in microelectronic devices, particularly through materials and processes for producing semi-porous dielectric materials wherein surface porosity is significantly reduced or removed while internal porosity is preserved to maintain a desired low-k value for the overall dielectric material.

Abstract: A method for fabricating an image sensor includes forming an insulation layer over a substrate in a logic circuit region and a pixel region, forming a photoresist over the insulation layer, patterning the photoresist to form a photoresist pattern where the insulation layer in the pixel region is exposed and the insulation layer in the logic circuit region is not exposed, wherein a thickness of the photoresist pattern is gradually decreased in an interfacial region between the pixel region and the logic circuit region in a direction of the logic circuit region to the pixel region, and performing an etch back process over the insulation layer and the photoresist pattern in conditions that an etch rate of the photoresist pattern are substantially the same as that of the insulation layer.

Abstract: A flat-top convex-bottom lower lens is formed by first applying a positive tone photoresist over a silicon oxide layer and an optional metallic barrier layer thereupon in a back-end-of-line (BEOL) metallization structure. The positive tone photoresist is exposed under defocused illumination conditions and/or employing a half-tone mask so that a cross-sectional profile of the positive tone photoresist after exposure contains a continuous and smooth concave profile, which is transferred into the underlying silicon oxide layer to form a concave cavity therein. After removing the photoresist, the cavity is filled with a high refractive index material such as silicon nitride, and planarized to form a flat-top convex-bottom lower lens. Various aluminum metal structures, a color filter, and a convex-top flat-bottom upper lens are thereafter formed so that the upper lens and the lower lens constitute a composite lens system.

Abstract: In a method for manufacturing a micromechanical component, a cavity is produced in the substrate from an opening at the rear of a monocrystalline semiconductor substrate. The etching process used for this purpose and the monocrystalline semiconductor substrate used are controlled in such a way that a largely rectangular cavity is formed.

Abstract: An insulation structure for high temperature conditions and a manufacturing method thereof. In the insulation structure, a substrate has a conductive pattern formed on at least one surface thereof for electrical connection of a device. A metal oxide layer pattern is formed on a predetermined portion of the conductive pattern by anodization, the metal oxide layer pattern made of one selected from a group consisting of Al, Ti and Mg.

Abstract: A solid-state light emitting display and a fabrication method thereof are proposed. The light emitting display includes a metallic board formed with conductive circuits, and a plurality of luminous microcrystals disposed on a surface of the metallic board and electrically connected to the conductive circuits. The metallic board provides the features of lightness and thinness, and flexibility, and the luminous microcrystals are in the form of light emitting components, so as to improve the luminous efficiency of display and attain the effect of environmental protection and energy saving, thereby providing display technology with performance satisfactory for various display requirements.

Abstract: A method for manufacturing a MEMS sensor and a thin film thereof includes steps of etching a top surface of a single-crystal silicon wafer in combination of a deposition process, an isotropic DRIE process, a wet etching process and a back etching process in order to form a pressure-sensitive single-crystal silicon film, a cantilever beam, a mass block, a front chamber, a back chamber and trenches connecting the front and the back chambers. The single-crystal silicon film is prevented from etching so that the thickness thereof can be well controlled. The method of the present invention can be used to replace the traditional method which forms the back chamber and the pressure-sensitive single-crystal silicon film from the bottom surface of the silicon wafer.

Abstract: A method and a system for forming a copper indium gallium sulfur selenide (CIGSSe) absorption layer and a cadmium sulfide (CdS) buffer layer under non-vacuum condition is disclosed. A coating layer is formed on the back electrode layer on the substrate by mixing the slurry on the back electrode layer, and the coating layer formed on the back electrode layer is densified by a densification device after initially dried, and then a primary selenization/sulfurization reaction process is carried out to form a primary CIGSSe layer, and then a thermal process is carried out to improve the lattice match of the primary CIGSSe layer, and then an impurity cleaning process is carried out by using potassium cyanide or bromide to remove the impurities of cuprous selenide and copper sulfide, and then a rear-stage selenization/sulfurization reaction process is carried out to produce the required rear-stage CIGSSe absorption layer.

Abstract: A multichip module defining a dc to dc converter employs a monolithic chip containing at least two III-nitride switches (a monolithic CSC chip) mounted on a conductive lead frame. The CSC chip is copacked with an IC driver for the switches and with the necessary passives. The module defines a buck converter; a boost converter, a buck boost converter, a forward converter and a flyback converter. The drain, source and gate pads of the monolithic CSC chip are connected to a lead frame by solder or epoxy or by bumping attach and a conductive connector or wire bonds connect the switch terminal to lead frame.

Abstract: A spin-torque based memory device includes a write portion including a fixed ferromagnetic spin-polarizing layer, a spin-transport layer having a spin accumulation region formed above the fixed ferromagnetic spin-polarizing layer. The memory device further includes a read portion in electrical contact with the spin-transport layer. The read portion includes a free layer magnet, a read non-magnetic layer, and a reference layer. The memory device further includes a metal contact region formed overlying the read portion and a nonlinear resistor formed between an upper surface of the spin transport layer and the metal contact region and modulating write and read current paths depending on an applied voltage, thereby creating different current paths for write and read processes.

Abstract: Resistive memory and methods of processing resistive memory are described herein. One or more method embodiments of processing resistive memory include conformally forming a cell material in an opening in an interlayer dielectric such that a seam is formed in the cell material, forming a conductive pathway by modifying the seam, and forming an electrode on the cell material and the seam.

Abstract: A method of manufacturing a nonvolatile memory device having a three-dimensional memory device includes alternately stacking a plurality of first and second material layers having a different etching selectivity on a semiconductor substrate; forming an opening penetrating the plurality of first and second material layers; removing the first material layers exposed by the opening to form extended portions extending in a direction perpendicular to the semiconductor substrate from the opening; conformally forming a charge storage layer along a surface of the opening and the extended portions; and removing the charge storage layer formed on sidewalls of the second material layers to locally form the charge storage layer patterns in the extended portions.

Abstract: The thermal management and method for large scale processing of CIS and/or CIGS based thin film overlaying glass substrates. According to an embodiment, the present invention provides a method for fabricating a copper indium diselenide semiconductor film. The method includes providing a plurality of substrates, each of the substrates having a copper and indium composite structure. The method also includes transferring the plurality of substrates into a furnace, each of the plurality of substrates provided in a vertical orientation with respect to a direction of gravity, the plurality of substrates being defined by a number N, where N is greater than 5. The method further includes introducing a gaseous species including a selenide species and a carrier gas into the furnace and transferring thermal energy into the furnace to increase a temperature from a first temperature to a second temperature, the second temperature ranging from about 350° C. to about 450° C.

Abstract: The thermal management and method for large scale processing of CIS and/or CIGS based thin film overlaying glass substrates. According to an embodiment, the present invention provides a method for fabricating a copper indium diselenide semiconductor film. The method includes providing a plurality of substrates, each of the substrates having a copper and indium composite structure. The method also includes transferring the plurality of substrates into a furnace, each of the plurality of substrates provided in a vertical orientation with respect to a direction of gravity, the plurality of substrates being defined by a number N, where N is greater than 5. The method further includes introducing a gaseous species including a selenide species and a carrier gas into the furnace and transferring thermal energy into the furnace to increase a temperature from a first temperature to a second temperature, the second temperature ranging from about 350° C. to about 450° C.

Abstract: A method of forming molding standoff structures on integrated circuit devices is disclosed which includes forming a plurality of standoff structures on a substantially rectangular sheet of transparent material and, after forming the standoff structures, singulating the substantially rectangular sheet of transparent material into a plurality of individual transparent members, each of which comprise at least one of the plurality of standoff structures.

Abstract: A micro electro-mechanical systems (MEMS) package is described herein. The package includes a carrier substrate having a top side, a MEMS chip mounted on the top side of the carrier substrate, and at least one chip component on or above the top side of the carrier substrate or embedded in the carrier substrate. The package also includes a thin metallic shielding layer covering the MEMS chip and the chip component and forming a seal with the top side of the carrier substrate.

Abstract: A method for manufacturing a MOS device. The method includes providing a semiconductor substrate. The method forms a gate dielectric layer overlying the semiconductor substrate and a polysilicon gate overlying the gate dielectric layer. The polysilicon gate is characterized by a thickness, a width and a polysilicon footing profile. In a specific embodiment, the method performs a TCAD simulation and determines a response of device performance due to the polysilicon footing profile from the model. The method uses the model to provide a process control window for fabricating the polysilicon gate.

Abstract: A method of making a light emitting device includes mixing a glass powder with a phosphor powder including at least one of a sulfide phosphor, an aluminate phosphor and a silicate phosphor to produce a mixed powder in which the phosphor powder is dispersed in the glass powder, heating and softening the mixed powder to provide an integrated material, and subsequently solidifying the integrated material to provide a phosphor-dispersed glass, and fusion-bonding the phosphor-dispersed glass onto a mounting portion on which a light emitting element is mounted by hot pressing, and simultaneously sealing the light emitting element with the phosphor-dispersed glass on the mounting portion.

Abstract: A light emitting diode having high light extraction efficiency and a method of manufacturing the same are provided. The LED includes a semiconductor multiple layer including an active layer; a transparent electrode layer formed on the semiconductor multiple layer; and refraction field unit embedded in the transparent electrode layer and formed of a material having a different refractive index than the transparent electrode layer.

Abstract: A method of making a mounted gallium nitride (GaN) device includes obtaining a device structure comprising a silicon layer, a silicon carbide (SiC) layer over the silicon layer, and a GaN layer over the SiC layer. The GaN layer is processed to form an active layer of active devices and interconnect over the GaN layer. After the step of processing the GaN layer, a gold layer is formed on the silicon layer. The device structure is attached to a heat sink structure using the gold layer. The mounted GaN device includes the SiC layer over the polysilicon layer and the GaN layer over the SiC layer. The active layer is over the GaN layer.

Abstract: A method of manufacturing a back side illumination image sensor is provided. The method can include forming an ion implantation layer in a front side of a first substrate, forming a photodetector and a readout circuit on the first substrate, forming an interlayer dielectric layer and a metal line on the front side of the first substrate, bonding a second substrate with the front side of the first substrate, removing a lower portion of the first substrate on the basis of the ion implantation layer, performing an annealing process with respect on a back side of the first substrate, and forming a microlens over the photodetector.

Abstract: A method and resulting device for reducing crosstalk in a back-illuminated imager is disclosed, comprising providing a substrate comprising an insulator layer and a seed layer substantially overlying the insulator layer, an interface being formed where the seed layer comes in contact with the insulator layer; forming an epitaxial layer substantially overlying the seed layer, the epitaxial layer defining plurality of pixel regions, each pixel region outlining a collection well for collecting charge carriers; and forming one of an electrical, optical, and electrical and optical barrier about the outlined collection well extending into the epitaxial layer to the interface between the seed layer and the insulator layer.

Abstract: A semiconductor device includes a carrier, a chip coupled to the carrier, a dielectric layer coupled to the carrier and the chip, and conducting elements connected to both the carrier and contacts of the chip. The chip includes a first face with a first contact spaced apart from a second contact. The dielectric layer includes a photoinitiator that configures the dielectric layer to be selectively opened to expose the first and second contacts and the carrier. A first conducting element is connected to the first contact, a second conducting element is connected to the second contact, and a third conducting element is connected to the carrier.

Abstract: A method of manufacturing a transistor, typically a MESFET, includes providing a substrate including single crystal diamond material having a growth surface on which further layers of diamond material can be deposited. The substrate is preferably formed by a CVD process and has high purity. The growth surface has a root-mean-square roughness of 3 nm or less, or is free of steps or protrusions larger than 3 nm. Further diamond layers are deposited on the growth surface to define the active regions of the transistor. An optional n+ shielding layer can be formed in or on the substrate, following which an additional layer of high purity diamond is deposited. A layer of intrinsic diamond may be formed directly on the upper surface of the high purity layer, followed by a boron doped (“delta doped”) layer. A trench is formed in the delta doped layer to define a gate region.

Abstract: Method of manufacturing a MEMS device integrated in a silicon substrate. In parallel to the manufacturing of the MEMS device passive components as trench capacitors with a high capacitance density can be processed. The method is especially suited for MEMS resonators with resonance frequencies in the range of 10 MHz.

Abstract: A semiconductor memory device includes plural word lines, plural first bit lines, plural plate lines formed corresponding to the word lines, plural second bit lines formed corresponding to the first bit lines, plural first ferroelectric capacitors each including a ferroelectric film between two electrodes, plural cell transistor formed corresponding to the first ferroelectric capacitors, and including a gate coupled to the word lines, plural second ferroelectric capacitors each including a ferroelectric film between two electrodes, and a sense amplifier configured to detect data stored in the first ferroelectric capacitors through the first bit lines or data stored in the second ferroelectric capacitors through the second bit line, or to write data in the first ferroelectric capacitors or the second ferroelectric capacitors.

Abstract: The invention relates to a method for producing a MEMS/NEMS structure from a substrate made in a monocrystalline semiconductor material, the structure comprising a flexible mechanical element connected to the substrate by at least one anchoring zone, the method comprising the following steps: the formation of a protection layer on one face of the substrate, the protection layer being made in a monocrystalline material different from the material of the substrate, etching of the protection layer and the substrate in order to produce at least one cavity, the etching being done so as to leave an overhang made in the material of the protection layer on the edges of the cavity, filling in of the cavity with an electrically insulating material in order to obtain an insulating anchoring portion, epitaxy of a semiconductor material from the protection layer and the electrically insulating material in order to obtain a layer designed to produce the flexible mechanical element, liberation of the flexible mechanical

Abstract: An image sensor pixel includes a substrate doped to have a first conductivity type. A first epitaxial layer is disposed over the substrate and doped to also have the first conductivity type. A transfer transistor gate is formed on the first epitaxial layer. An epitaxially grown photo-sensor region is disposed in the first epitaxial layer and has a second conductivity type. The epitaxially grown photo-sensor region includes an extension region that extends under a portion of the transfer transistor gate.

Abstract: An MEMS element (A1) includes a substrate (1), and a first electrode (2) formed on the substrate (1). The MEMS element (A1) further includes a second electrode (3) including a movable portion (31) spaced from the first electrode (2) and facing the first electrode. The movable portion (31) is formed with a plurality of through-holes (31a). Each of the through-holes (31a) may have a rectangular cross section.

Abstract: Light Emitting Diodes (LEDs) where the emission region, usually a (Al,In,Ga)N layer, is structured for efficient light extraction, are disclosed. The structuring is designed for light extraction from thin films, such as a photonic crystal acting as a diffraction grating. In addition, the structuring controls the in-plane emission and allows new modes into which light will be emitted. Various electrode designs are proposed, including ZnO structures which are known to lead to both excellent electrical properties, such as good carrier injection, and high transparency. Alternatively, the (Al,In,Ga)N layer can be replaced by structures with other materials compositions, in order to achieve efficient light extraction.

Abstract: A method for manufacturing a MEMS sensor and its thin film and cantilever beam includes steps of etching a top surface of a single-crystal silicon wafer in combination of a deposition process, an outer epitaxial growth process, a wet etching process and a back etching process in order to form a pressure-sensitive single-crystal silicon film, a cantilever beam, a mass block, a front chamber, a back chamber and trenches connecting the front and the back chambers. The single-crystal silicon film is prevented from etching so that the thickness thereof can be well controlled. The method of the present invention can be used to replace the traditional method which forms the back chamber and the pressure-sensitive single-crystal silicon film from the bottom surface of the silicon wafer.

Abstract: An apparatus for depositing a solid film onto a substrate from a reagent solution includes reservoirs of reagent solutions maintained at a sufficiently low temperature to inhibit homogeneous reactions within the reagent solutions. The chilled solutions are dispensed through showerheads, one at a time, onto a substrate. One of the showerheads includes a nebulizer so that the reagent solution is delivered as a fine mist, whereas the other showerhead delivers reagent as a flowing stream. A heater disposed beneath the substrate maintains the substrate at an elevated temperature at which the deposition of a desired solid phase from the reagent solutions may be initiated. Each reagent solution contains at least one metal and either S or Se, or both. At least one of the reagent solutions contains Cu. The apparatus and its associated method of use are particularly suited to forming films of Cu-containing compound semiconductors.

Abstract: A MEMS may integrate movable MEMS parts, such as mechanical elements, flexible membranes, and sensors, with the low-cost device package, leaving the electronics and signal-processing parts in the integrated circuitry of the semiconductor chip. The package may be a leadframe-based plastic molded body having an opening through the thickness of the body. The movable part may be anchored in the body and extend at least partially across the opening. The chip may be flip-assembled to the leads to span across the foil, and may be separated from the foil by a gap. The leadframe may be a prefabricated piece part, or may be fabricated in a process flow with metal deposition on a sacrificial carrier and patterning of the metal layer. The resulting leadframe may be flat or may have an offset structure useful for stacked package-on-package devices.

Abstract: Provided are a light-emitting element, a light-emitting device including the same, and methods of fabricating the light-emitting element and the light-emitting device. The light-emitting element includes a substrate on which a dome pattern is formed and a light-emitting structure conformally formed on the dome pattern. The light-emitting structure includes a first conductive layer of a first conductivity type, a light-emitting layer, and a second conductive layer of a second conductivity type sequentially stacked on the substrate. The light-emitting element also includes a first electrode formed on the first conductive layer and a second electrode formed on the second conductive layer.

Abstract: A sensor element is described that includes at least one semiconductor component having a gas-sensitive layer which is attached to a substrate by the flip-chip method, the gas-sensitive layer facing the substrate and a supply arrangement being provided to supply a gas to be examined to the gas-sensitive layer. The semiconductor component is enclosed in a casing. Also described is a method for manufacturing the sensor element, in which a semiconductor component having a gas-sensitive layer is attached by the flip-chip method to a substrate in such a way that the gas-sensitive layer faces the substrate. After that, the casing is applied by a plasma sputtering method, in particular an atmospheric plasma sputtering method. Finally, a use of the sensor element in the exhaust system of an internal combustion engine is also described.

Abstract: An inductively coupled plasma source is provided with a peripheral ionization source for producing a high-density plasma in a vacuum chamber for semiconductor wafer coating or etching. The source includes a segmented configuration having high and low radiation segments and produces a generally ring-shaped array of alternating high and low energy concentrations in the plasma around the periphery of the chamber. Energy is coupled from a segmented low inductance antenna through a dielectric window or array of windows and through a segmented shield or baffle.

Abstract: A method, a system and a computer readable medium for integrated in-vacuo repair of low-k dielectric thin films damaged by etch and/or strip processing. A repair chamber is integrated onto a same platform as a plasma etch and/or strip chamber to repair a low-k dielectric thin film without breaking vacuum between the damage event and the repair event. UV radiation may be provided on the integrated etch/repair platform in any combination of before, after, or during the low-k repair treatment to increase efficacy of the repair treatment and/or stability of repair.

Abstract: A light panel includes a light source having a generally planar, light emitting surface and a perimeter edge. A backsheet is disposed in substantially parallel relation with the light emitting surface, and an electrical feed-through region extends through the backsheet at a location spaced inwardly from the perimeter. A generally planar, flexible connector cable extends over the backsheet from the perimeter to the electrical feed-through region for establishing electrical connection with the light source. Openings in conductive pads provided in the flexible cable permit a conductive material to be inserted there through and mechanically and electrically interconnect the cable and the light panel.

Abstract: The invention provides a method of depositing a layer of a conductive material, e.g. metal, metal oxide or electroconductive polymer, from a patterned stamp, preferably a soft, elastomeric stamp, to a substrate after an organic layer has been transferred from a patterned stamp to an organic layer over the substrate. The patterned metal or organic layer may be used for example, in a wide range of electronic devices. The present methods are particularly suitable for nanoscale patterning of organic electronic components.

Abstract: Described is a device having an anti-reflection surface. The device comprises a silicon substrate with a plurality of silicon spikes formed on the substrate. A first metallic layer is formed on the silicon spikes to form the anti-reflection surface. The device further includes an aperture that extends through the substrate. A second metallic layer is formed on the substrate. The second metallic layer includes a hole that is aligned with the aperture. A spacer is attached with the silicon substrate to provide a gap between an attached sensor apparatus. Therefore, operating as a Micro-sun sensor, light entering the hole passes through the aperture to be sensed by the sensor apparatus. Additionally, light reflected by the sensor apparatus toward the first side of the silicon substrate is absorbed by the first metallic layer and silicon spikes and is thereby prevented from being reflected back toward the sensor apparatus.

Abstract: A process and associated system for vapor deposition of a thin film layer on a photovoltaic (PV) module substrate is includes establishing a vacuum chamber and introducing the substrates individually into the vacuum chamber. The substrates are pre-heated as they are conveyed through the vacuum chamber, and are then conveyed in serial arrangement through a vapor deposition apparatus in the vacuum chamber wherein a thin film of a sublimed source material is deposited onto an upper surface of the substrates. The substrates are conveyed through the vapor deposition apparatus at a controlled constant linear speed such that leading and trailing sections of the substrate in a conveyance direction are exposed to the same vapor deposition conditions within the vapor deposition apparatus. The vapor deposition apparatus may be supplied with source material in a manner so as not to interrupt the vapor deposition process or non-stop conveyance of the substrates through the vapor deposition apparatus.

Abstract: Provided are a light-emitting element and a light-emitting device, and methods of fabricating the same. The method of fabricating a light-emitting element includes forming a buffer layer on a substrate and forming photonic crystal patterns and a pad pattern on the buffer layer. Each of the pad pattern and the photonic crystal patterns are made of a metal material, and the pad pattern is physically connected to the photonic crystal patterns. Forming a light-emitting structure includes sequentially stacking a first conductive pattern of a first conductivity type, a light-emitting pattern, and a second conductive pattern of a second conductivity type on the buffer layer. And the method also includes forming a first electrode that is electrically connected to the first conductive pattern and forming a second electrode that is electrically connected to the second conductive pattern.

Abstract: The present invention relates to a semiconductor-on-insulator structure including a semiconductor component comprised of substantially single-crystal semiconductor material layer and a single-crystal semiconductor material with an enhanced oxygen content layer; an oxide glass material layer; and a glass-ceramic layer.

Abstract: The thermal management and method for large scale processing of CIS and/or CIGS based thin film overlaying glass substrates. According to an embodiment, the present invention provides a method for fabricating a copper indium diselenide semiconductor film. The method includes providing a plurality of substrates, each of the substrates having a copper and indium composite structure. The method also includes transferring the plurality of substrates into a furnace, each of the plurality of substrates provided in a vertical orientation with respect to a direction of gravity, the plurality of substrates being defined by a number N, where N is greater than 5. The method further includes introducing a gaseous species including a selenide species and a carrier gas into the furnace and transferring thermal energy into the furnace to increase a temperature from a first temperature to a second temperature, the second temperature ranging from about 350° C. to about 450° C.

Abstract: A STT-MRAM integration scheme is disclosed wherein the connection between a MTJ and CMOS metal is simplified by forming an intermediate via contact (VAC) on a CMOS landing pad, a metal (VAM) pad that contacts and covers the VAC, and a MTJ on the VAM. A dual damascene process is performed to connect BIT line metal to CMOS landing pads through VAC/VAM/MTJ stacks in a device region, and to connect BIT line connection pads to CMOS connection pads through BIT connection vias outside the device region. The VAM pad is a single layer or composite made of Ta, TaN, or other conductors which serves as a diffusion barrier, has a highly smooth surface for MTJ formation, and provides excellent selectivity with refill dielectric materials during a chemical mechanical polish process. Each VAC is from 500 to 3000 Angstroms thick to minimize additional circuit resistance and minimize etch burden.