Chemical Etching (epo) Patents (Class 257/E21.219)
  • Publication number: 20110256728
    Abstract: A wafer thinning apparatus for treating wafers each having at least a circuit-forming surface thereof protected, by immersing the wafers in a treating solution. The apparatus includes a support table for receiving, as placed thereon, containers each containing a plurality of wafers in one of groups into which the wafers are sorted according to predetermined ranges of thickness, a treating tank for storing the treating solution and receiving the containers, a transport mechanism for transporting the containers between the support table and the treating tank, and a control unit for controlling the transport mechanism to transport the containers successively to the treating tank, and for changing an immersion time of the containers in the treating tank for each group.
    Type: Application
    Filed: July 1, 2011
    Publication date: October 20, 2011
    Inventors: Toshio HIROE, Kenichiro ARAI
  • Publication number: 20110250762
    Abstract: A method of simultaneously cleaning inorganic and organic contaminants from semiconductor wafers and micro-etching the semiconductor wafers. After the semiconductor wafers are cut or sliced from ingots, they are contaminated with cutting fluid as well as metal and metal oxides from the saws used in the cutting process. Aqueous alkaline cleaning and micro-etching solutions containing alkaline compounds and mid-range alkoxylates are used to simultaneously clean and micro-etch the semiconductor wafers.
    Type: Application
    Filed: October 14, 2010
    Publication date: October 13, 2011
    Applicant: Rohm and Haas Electronic Materials LLC
    Inventors: Robert K. Barr, Raymond Chan
  • Patent number: 8034721
    Abstract: A first film and a second film are formed on a semiconductor substrate in this order. A resist pattern is formed on the second film. An opening is formed by removing the second film exposed between the resist pattern at a state where the second film remains on the bottom. A first removal preventing film is formed on the side wall of the opening and the residual film is removed at a state where the projecting part of the second film protruding from the side wall to the opening remains. The first film exposed in the opening is removed. A second removal preventing film is formed on the first removal preventing film and the surface of the semiconductor substrate exposed in the opening is removed at a state where the projecting part of the semiconductor substrate protruding from the side wall to the opening remains and a round part is formed at the projecting part of the semiconductor substrate. The semiconductor substrate exposed in the opening is further removed.
    Type: Grant
    Filed: March 4, 2010
    Date of Patent: October 11, 2011
    Assignee: Panasonic Corporation
    Inventors: Masaru Yamada, Akihiko Tsudumitani
  • Publication number: 20110241088
    Abstract: A field effect transistor includes a high resistance layer on a substrate, a semiconductor operation layer that is formed on the high resistance layer and includes a channel layer that has the carbon concentration of not more than 1×1018 cm?3 and has the layer thickness of more than 10 nm and not more than 100 nm, a recess that is formed up to the inside of the channel layer in the semiconductor operation layer, source and drain electrodes that are formed on the semiconductor operation layer with the recess intervening therebetween, a gate insulating film that is formed on the semiconductor operation layer so as to cover the recess, and a gate electrode that is formed on the gate insulating film in the recess.
    Type: Application
    Filed: March 30, 2011
    Publication date: October 6, 2011
    Applicant: FURUKAWA ELECTRIC CO., LTD.
    Inventors: Yoshihiro SATO, Takehiko NOMURA, Nariaki IKEDA, Takuya KOKAWA, Masayuki IWAMI, Sadahiro KATO
  • Patent number: 8026148
    Abstract: Some embodiments include methods of forming capacitors. Storage nodes are formed within a material. The storage nodes have sidewalls along the material. Some of the material is removed to expose portions of the sidewalls. The exposed portions of the sidewalls are coated with a substance that isn't wetted by water. Additional material is removed to expose uncoated regions of the sidewalls. The substance is removed, and then capacitor dielectric material is formed along the sidewalls of the storage nodes. Capacitor electrode material is then formed over the capacitor dielectric material. Some embodiments include methods of utilizing a silicon dioxide-containing masking structure in which the silicon dioxide of the masking structure is coated with a substance that isn't wetted by water.
    Type: Grant
    Filed: January 12, 2011
    Date of Patent: September 27, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Niraj B. Rana, Nishant Sinha, Prashant Raghu, Jim J. Hofmann, Neil Joseph Greeley
  • Publication number: 20110230053
    Abstract: The present invention is directed to provide an etching agent for a semiconductor substrate, which is capable of etching a titanium (Ti)-based metal film or a tungsten (W)-based metal film on a semiconductor substrate and an etching method using relevant etching agent, and relates to a liquid for preparing the etching agent for a semiconductor substrate composed of a solution comprising (A) hydrogen peroxide, (B) a phosphonic acid chelating agent having a hydroxyl group, (C) a basic compound, and (D-1) a copper anticorrosive and/or (D-2) 0.
    Type: Application
    Filed: December 19, 2008
    Publication date: September 22, 2011
    Applicant: WAKO PURE CHEMICAL INDUSTRIES, LTD.
    Inventors: Osamu Matsuda, Nobuyuki Kikuchi, Ichiro Hayashida, Satoshi Shirahata
  • Publication number: 20110220199
    Abstract: An inkjet ink comprises phosphoric acid; one or more solvents for the phosphoric acid, preferably ethyl lactate and water; and one or more aprotic organic sulfoxides, preferably dimethyl sulfoxide (DMSO) or dimethyl sulfone (SMSO2). The inks do not leave a carbon residue on heating and so are suited to use in etching and/or doping silicon wafers, e.g. in the production of crystalline silicon solar cells.
    Type: Application
    Filed: October 30, 2009
    Publication date: September 15, 2011
    Applicant: CONDUCTIVE INKJET TECHNOLOGY LIMITED
    Inventors: Martyn John Robinson, Philip Gareth Bentley
  • Publication number: 20110223772
    Abstract: An etching process for selectively etching exposed metal surfaces of a substrate and forming a conductive capping layer over the metal surfaces is described. In some embodiments, the etching process involves oxidation of the exposed metal to form a metal oxide that is subsequently removed from the surface of the substrate. The exposed metal may be oxidized by using solutions containing oxidizing agents such as peroxides or by using oxidizing gases such as those containing oxygen or ozone. The metal oxide produced is then removed using suitable metal oxide etching agents such as glycine. The oxidation and etching may occur in the same solution. In other embodiments, the exposed metal is directly etched without forming a metal oxide. Suitable direct metal etching agents include any number of acidic solutions. The process allows for controlled oxidation and/or etching with reduced pitting.
    Type: Application
    Filed: May 26, 2011
    Publication date: September 15, 2011
    Inventors: Steven T. Mayer, Daniel A. Koos, Eric Webb
  • Publication number: 20110223766
    Abstract: A method for manufacturing a semiconductor device includes: exposing an insulating film including a siloxane bond to an energy beam or plasma; and exposing the insulating film to a gas (excluding N2 and H2O gases) including at least one element selected from the group consisting of hydrogen, carbon, nitrogen and silicon, as an constituent element, wherein, in the exposing to the gas, after a relative permittivity of the insulating film descends by the exposing the insulating film to the gas, the exposing is completed before a time point when the relative permittivity of the insulating film first ascends.
    Type: Application
    Filed: May 20, 2011
    Publication date: September 15, 2011
    Applicant: FUJITSU LIMITED
    Inventors: Yasushi Kobayashi, Yoshihiro Nakata, Yuichi Minoura
  • Publication number: 20110223741
    Abstract: A method and a system are described herein for applying etchant to edges of a plurality of wafers. The system includes a sump configured for holding etchant, a roller having an outer surface in fluid communication with the sump and configured to have etchant thereon, a wafer cassette configured to retain wafers positioned therein so that edges of the wafers are in contact with the roller. The cassette permits axial rotation of the wafers about an axis. A method of applying etchant to the edge of the wafer includes placing the wafer edge in contact with the roller and rotating the roller about a longitudinal axis of the roller. At least a portion of the roller contact an etchant contained in a sump during rotation so that etchant is applied to the wafer edge.
    Type: Application
    Filed: November 16, 2009
    Publication date: September 15, 2011
    Applicant: MEMC ELECTRONIC MATERIALS, INC.
    Inventor: Robert W. Standley
  • Publication number: 20110223771
    Abstract: The present invention provides a method of wet etching a silicon slice including a silicon substrate and a metal film layer thereon comprising steps of: performing lithographic process to the silicon slice forming a masked silicon slice comprising the silicon substrate and a partially masked metal film thereon; immersing the masked silicon slice into an etchant; rotating the masked silicon slice in the etchant; injecting high-purity nitrogen gas into the etchant for agitating the etchant; removing the masked silicon slice out of the etchant, upon completion of etching; and rinsing the masked silicon slice with deionized water.
    Type: Application
    Filed: March 15, 2010
    Publication date: September 15, 2011
    Inventors: Yadong Jiang, Zhiming Wu, Tao Wang, Weizhi Li, Xiaolin Han
  • Publication number: 20110217804
    Abstract: A method for fabricating a micromirror in a wafer, including the steps of: depositing and etching layers forming two arms; etching the wafer such that in the back face only a thin portion of the wafer remains in the region of formation of the micromirror and the arms; performing an anisotropic etch, such that the thin portion remains only in the areas of the micromirror and the arms; and performing an isotropic etch to remove the thin portions under the arms, the etching step for forming the arms being performed following their shape and so as to form holes traversing the arms, the holes being positioned at edges of the region separating the micromirror and the wafer on both the side of the micromirror and the side of the portions of the wafer remaining after the anisotropic etching step. The invention also concerns the micromirror.
    Type: Application
    Filed: June 24, 2008
    Publication date: September 8, 2011
    Applicant: ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL)
    Inventors: Nicolas Abele, Faouzi Khechana, Philippe Renaud
  • Publication number: 20110215441
    Abstract: The present invention provides silicon nanostructures and their producing method. By employing a metal-assisted chemical etching method, the bottom of the produced silicon nanostructures, connected to the silicon substrate, is porous and side etched, such that the silicon nanostructures can be easily transferred to a hetero-substrate by a physical manner.
    Type: Application
    Filed: May 28, 2010
    Publication date: September 8, 2011
    Applicant: NATIONAL TAIWAN UNIVERSITY
    Inventors: CHING-FUH LIN, SHU-JIA SYU
  • Publication number: 20110217848
    Abstract: A processing chamber successfully removes hardened photoresist via direct infrared radiation onto the wafer, in the presence of an acid such as sulfuric acid, optionally along with an oxidizer such as hydrogen peroxide. The processing chamber includes a fixture for holding and optionally rotating the wafer. An infrared irradiating assembly has infrared lamps outside of the processing chamber positioned to radiate infrared light into the processing chamber. The infrared lamps may be arranged to irradiate substantially the entire surface of a wafer on the rotor. A cooling assembly can be associated with the infrared radiating assembly to provide a quick cool down and avoid over-processing. Photoresist is removed using small amounts of chemical solutions.
    Type: Application
    Filed: March 3, 2010
    Publication date: September 8, 2011
    Inventors: Eric J. Bergman, Jerry Dustin Leonhard, Bryan Puch, Jason Rye
  • Publication number: 20110212620
    Abstract: Processes for forming high density gap-filling silicon oxide on a patterned substrate are described. The processes increase the density of gap-filling silicon oxide particularly in narrow trenches. The density may also be increased in wide trenches and recessed open areas. The densities of the gap-filling silicon oxide in the narrow and wide trenches/open areas become more similar following the treatment which allows the etch rates to match more closely. This effect may also be described as a reduction in the pattern loading effect. The process involves forming then planarizing silicon oxide. Planarization exposes a new dielectric interface disposed closer to the narrow trenches. The newly exposed interface facilitates a densification treatment by annealing and/or exposing the planarized surface to a plasma.
    Type: Application
    Filed: March 8, 2011
    Publication date: September 1, 2011
    Applicant: Applied Materials, Inc.
    Inventors: Jingmei Liang, Nitin K. Ingle, Shankar Venkataraman
  • Publication number: 20110195579
    Abstract: Controlling scribe line orientation during wet-bench processes has been found to improve yield and reduce particles from inadequate draining when the scribe lines are oriented about 45 degrees from horizontal. A wafer is provided to the wet bench apparatus and immersed in a solution. When removed from the solution, the wafer should be oriented vertically with scribe lines oriented about 45 degrees, plus or minus 15 degrees from horizontal. Wafer scribe line orientation are checked and changed before the wet bench process or during the wet bench processing.
    Type: Application
    Filed: February 11, 2010
    Publication date: August 11, 2011
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Yi-Tung YEN
  • Patent number: 7994062
    Abstract: A process for etching a silicon layer disposed on a substrate, including anisotropically etching a first trench in the silicon layer; selectively anisotropic wet etching silicon surfaces in the first trench, the wet etching comprising exposing the silicon surfaces to an aqueous composition including an aromatic tri(lower)alkyl quaternary onium hydroxide, and an unsymmetrical tetraalkyl quaternary phosphonium salt; in which the wet etching etches (110) and (100) planes of the silicon layer at about equal rates and preferentially to the (111) plane to form an enlarged trench having a sidewall in the (111) plane. A silicon alloy may be epitaxially deposited in the thus-produced trench as part of a process of introducing stress into at least a portion of the silicon layer.
    Type: Grant
    Filed: October 30, 2009
    Date of Patent: August 9, 2011
    Assignee: Sachem, Inc.
    Inventors: William A. Wojtczak, Sian Collins
  • Patent number: 7994067
    Abstract: A semiconductor manufacturing apparatus and a semiconductor manufacturing method, and has as one object to process a wafer easily and stably irrespective of thickness. To achieve the above object, a semiconductor manufacturing apparatus includes: an open-topped cassette that encases a semiconductor substrate; a plurality of processors for performing a predetermined processing of the semiconductor substrate; and a transporting mechanism that transports the cassette encasing the semiconductor substrate between the plurality of processors.
    Type: Grant
    Filed: September 27, 2004
    Date of Patent: August 9, 2011
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Norifumi Tokuda
  • Publication number: 20110183524
    Abstract: A method for chemically treating a disc-shaped substrate having a bottom surface, a top surface and side surfaces by contacting a process medium that is fluid-chemically active with at least the bottom surface of the substrate. The substrate is moved relative to the process medium while forming a triple line between the substrate, the substrate medium and the atmosphere surrounding the substrate and medium. In order to chemically remove errors, particularly in the side surfaces, relative motion should be carried out while avoiding a contacting of the process medium with the top surface of the substrate, where the triple line is formed at a desired height of the side surface facing away from the process medium flow side in relation to the relative motion between the substrate and the process medium. In this way, the atmosphere can be adjusted in relation to the partial pressures of the components in the process medium such that the top surface preserves hydrophobic characteristics.
    Type: Application
    Filed: September 29, 2009
    Publication date: July 28, 2011
    Applicant: SCHOTT SOLAR AG
    Inventors: Andreas Teppe, Berthold Schum, Dieter Franke, Ingo Schwirtlich, Knut Vaas, Wilfried Schmidt
  • Publication number: 20110183520
    Abstract: The invention is directed to a method for removing copper oxide from a copper surface to provide a clean copper surface, wherein the method involves exposing the copper surface containing copper oxide thereon to an anhydrous vapor containing a carboxylic acid compound therein, wherein the anhydrous vapor is generated from an anhydrous organic solution containing the carboxylic acid and one or more solvents selected from hydrocarbon and ether solvents.
    Type: Application
    Filed: January 28, 2010
    Publication date: July 28, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Tien-Jen Cheng, Stephan Grunow, Zhengwen Li, Huilong Zhu
  • Publication number: 20110183522
    Abstract: A method is provided for processing a wafer used in fabricating semiconductor devices. The method can comprise forming high-aspect ratio features on the wafer, which is followed by wet processing and drying. During drying, pattern collapse can occur. This pattern collapse can be repaired to allow for additional processing of the wafer. In some instance, pattern collapse can be repaired via etching where the etching breaks bonds that can have formed during pattern collapse.
    Type: Application
    Filed: January 26, 2010
    Publication date: July 28, 2011
    Applicant: LAM RESEARCH CORPORATION
    Inventors: Katrina Mikhaylichenko, Denis Syomin, Qian Fu, Glenn W. Gale, Shenjian Liu, Mark H. Wilcoxson
  • Publication number: 20110183448
    Abstract: A liquid composition used to carry out crystal anisotropic etching of a silicon substrate provided with an etching mask formed of a silicon oxide film with the silicon oxide film used as a mask includes cesium hydroxide, an alkaline organic compound, and water.
    Type: Application
    Filed: January 26, 2011
    Publication date: July 28, 2011
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Hiroyuki Abo, Taichi Yonemoto, Shuji Koyama, Kenta Furusawa, Keisuke Kishimoto
  • Publication number: 20110176572
    Abstract: A vertical cavity surface emitting laser (VCSEL) (100) has a substrate (104), on which are disposed first and second distributed Bragg reflectors (DBRs) (106, 112), each DBR comprising a stack of layers of alternating refractive index, an active layer (108) disposed between the DBRs, and an aperture layer (110) disposed either between the DBRs or within one of the DBRs. The aperture layer (110) has a border (116) having an internal boundary with a plurality of indented portions defining one or more apertures. Such a VCSEL is easily manufacturable and provides a narrow bandwidth output, as well as mitigating at least some of the problems of prior art VCSELs. Mesa (102) may be etched to be non-circular and subsequent selective oxidation of aperture layer (110) results in a non-circular current confinement aperture (114) promoting higher-order lateral modes (LP21).
    Type: Application
    Filed: September 30, 2009
    Publication date: July 21, 2011
    Applicant: OCLARO TECHNOLOGY LIMITED
    Inventors: Michael Moser, Sven Eitel, Wolfgang Kaiser
  • Publication number: 20110174799
    Abstract: A micro-hotplate is provided in the form of a device comprising a sensor and one or more resistive heaters within the micro-hotplate arranged to heat the sensor. Furthermore a controller is provided for applying a bidirectional drive current to at least one of the heaters to reduce electromigration. The controller also serves to drive the heater at a substantially constant temperature. Such an arrangement is advantageous over an arrangement in which a unidirectional DC drive current is applied to the heater. This is because the unidirectional drive current causes electromigration which results in an increase in resistance over time. This is undesirable because it can lead to failure of the micro-hotplate. In contrast, the application of the bidirectional current reduces electromigration and as a result there is insignificant change in the resistance of the heater over time and under high temperature.
    Type: Application
    Filed: January 21, 2010
    Publication date: July 21, 2011
    Inventors: Syed Zeeshan ALI, Florin Udrea, Julian William Gardner
  • Patent number: 7981787
    Abstract: A semiconductor device manufacturing method includes: providing a laminated member in which at least a first GaAs layer, an InAlGaAs layer and a second GaAs layer are laminated on or above a substrate in this order; and etching the second GaAs layer using the InAlGaAs layer as an etching stopper layer. A ratio of In:Al of the InAlGaAs layer is in a range of approximately 4:6 to approximately 6:4 and a ratio of (In+Al):Ga of the InAlGaAs layer is in a range of approximately 1.5:8.5 to approximately 5:5.
    Type: Grant
    Filed: August 17, 2009
    Date of Patent: July 19, 2011
    Assignee: OKI Semiconductor Co., Ltd.
    Inventors: Takayuki Izumi, Ryoji Shigemasa, Tomoyuki Ohshima
  • Publication number: 20110171834
    Abstract: In etching processing of silicon, in particular anisotropic etching processing of silicon in a manufacturing step of MEMS parts, an etchant having a long life of etchant and an etching method are provided by suppressing a lowering of an etching rate at the time of warming which is characteristic of a hydroxylamine-containing etchant. A silicon etchant for anisotropically dissolving monocrystalline silicon therein, which is an alkaline aqueous solution containing (A) tetramethylammonium hydroxide, (B) hydroxylamine and (C) carbon dioxide (CO2) and/or a carbonic acid salt of tetramethylammonium and having a pH of 13 or more, and an etching method of silicon using this etchant are provided.
    Type: Application
    Filed: June 25, 2009
    Publication date: July 14, 2011
    Applicant: Mitsubishi Gas Chemical Company, Inc.
    Inventors: Kazuyoshi Yaguchi, Ryuji Sotoaka
  • Publication number: 20110165719
    Abstract: A method of forming a sensor with an embedded cavity can include forming at least one cavity (50) in a substrate (52). The cavity (50) can include at least one membrane wall (54) having a plurality of holes (64) in the membrane wall (54), the plurality of holes (64) being formed in a two-dimensional array. A piezoresistive system (58) can be mechanically associated with the membrane wall (54). The method can be a front-side or back-side process for forming the cavity (50). The membrane (54) simultaneously acts as a diaphragm and a fluid passage into the cavity (50). Such sensors can be suitable as pressure sensors, chemical sensors, flow sensors and the like.
    Type: Application
    Filed: March 13, 2009
    Publication date: July 7, 2011
    Inventors: Florian Solzbacher, Michael Orthner
  • Patent number: 7972966
    Abstract: The present invention in one embodiment provides an etch method that includes providing a structure including a tungsten (W) portion and a titanium nitride (TiN) portion; applying a first etch feed gas of sulfur hexafluoride (SF6) and oxygen (O2), in which the ratio of sulfur hexafluoride (SF6) to oxygen (O2) ranges from 1:3.5 to 1:4.5; and applying a second etch feed gas of nitrogen trifluoride (NF3), helium (He) and chlorine (Cl2), in which the ratio of nitrogen trifluoride (NF3) to chlorine (Cl2) ranges from 1:5 to 2:5 and the ratio of helium (He) to nitrogen trifluoride (NF3) and chlorine (Cl2) ranges from 1:3 to 1:1.
    Type: Grant
    Filed: May 19, 2009
    Date of Patent: July 5, 2011
    Assignee: International Business Machines Corporation
    Inventors: Matthew J. Breitwisch, Eric A. Joseph, Chung H. Lam, Alejandro G. Schrott, Brandon Yee
  • Patent number: 7972963
    Abstract: A polished semiconductor wafer has a front surface and a back surface and an edge R, which is located at a distance of a radius from a center of the semiconductor wafer, forms a periphery of the semiconductor wafer and is part of a profiled boundary of the semiconductor wafer. The maximum deviation of the flatness of the back surface from an ideal plane in a range between R-6 mm and R-1 mm of the back surface is 0.7 ?m or less. A process for producing the semiconductor wafer, comprises at least one treatment of the semiconductor wafer with a liquid etchant and at least one polishing of at least a front surface of the semiconductor wafer, the etchant flowing onto a boundary of the semiconductor wafer during the treatment, and the boundary of the semiconductor wafer which faces the flow of etchant being at least partially shielded from being struck directly by the etchant. The shielding extends in the direction of a thickness d of the semiconductor wafer and is at least d+100 ?m long.
    Type: Grant
    Filed: October 11, 2007
    Date of Patent: July 5, 2011
    Assignee: Siltronic AG
    Inventors: Thomas Teuschler, Guenter Schwab, Maximilian Stadler
  • Publication number: 20110159670
    Abstract: Provided is a photoresist that includes a polymer having a backbone that is breakable and a photo acid generator that is free of bonding from the polymer. Further, provided is a method of fabricating a semiconductor device. The method includes providing a device substrate. A material layer is formed over the substrate. A photoresist material is formed over the material layer. The photoresist material has a polymer that includes a backbone. The photoresist material is patterned to form a patterned photoresist layer. A fabrication process is then performed to the material layer, wherein the patterned photoresist layer serves as a mask in the fabrication process. Thereafter, the patterned photoresist layer is treated in a manner that breaks the backbone of the polymer. The patterned photoresist layer is then removed.
    Type: Application
    Filed: December 30, 2009
    Publication date: June 30, 2011
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Wei Wang, Ming-Feng Shieh, Ching-Yu Chang
  • Publication number: 20110151672
    Abstract: An exemplary method of patterning oxide layer and removing residual nitride includes steps of forming a first oxide layer, a nitride layer, a second oxide layer and a complex hard mask on a substrate in turn. The first oxide layer covers an insulating structure. The second oxide layer, the complex hard mask and the nitride layer are etched by utilizing a patterned photoresist as an etching mask, so as to expose the first oxide layer. In addition, the part of the nitride layer covering the insulating structure can be further removed. Accordingly, the present invention can effectively control layout patterns of material layers and doped regions and thereby can improve the performance of a narrow width device.
    Type: Application
    Filed: December 18, 2009
    Publication date: June 23, 2011
    Inventor: Ping-Chia SHIH
  • Patent number: 7964512
    Abstract: In one implementation, a method is provided for etching a high k dielectric material in a plasma etch reactor, the method comprising plasma etching the high k dielectric material with a first plasma gas reactant mixture having BCl3. The high k dielectric material may include Al2O3 in a stack having a silicon layer. The etching may include supplying a passivation gas, for example C2H4, and may further include supplying a diluent gas such as a noble gas, for example He. In some implementations, the etching may be performed with a reactive ion etch process.
    Type: Grant
    Filed: August 22, 2005
    Date of Patent: June 21, 2011
    Assignee: Applied Materials, Inc.
    Inventors: Xikun Wang, Wei Liu, Yan Du, Mei Hua Shen
  • Publication number: 20110143543
    Abstract: Some embodiments include methods of forming capacitors. Storage nodes are formed within a material. The storage nodes have sidewalls along the material. Some of the material is removed to expose portions of the sidewalls. The exposed portions of the sidewalls are coated with a substance that isn't wetted by water. Additional material is removed to expose uncoated regions of the sidewalls. The substance is removed, and then capacitor dielectric material is formed along the sidewalls of the storage nodes. Capacitor electrode material is then formed over the capacitor dielectric material. Some embodiments include methods of utilizing a silicon dioxide-containing masking structure in which the silicon dioxide of the masking structure is coated with a substance that isn't wetted by water.
    Type: Application
    Filed: February 22, 2011
    Publication date: June 16, 2011
    Applicant: Micro Technology Inc.
    Inventors: NIRAJ RANA, Nishant Sinha, Prashant Raghu, Jim Hofmann, Neil Greeley
  • Publication number: 20110136345
    Abstract: C4 compounds selected from the group of trifluorobutadienes and tetrafluorobutenes can be used as etching gases, especially for anisotropic etching in the production of etched items, for example, of semiconductors, e.g. semiconductor memories or semiconductor logic circuits, flat panels, or solar cells. Preferred compounds are 1,1,3-trifluoro-1,3-butadiene, (E)-1,1,1,3-tetrafluoro-2-butene, 2,4,4,4-tetrafluoro-1-butene and (Z)-1,1,1,3-tetrafluoro-2-butene which can be obtained from halotetrafluorobutanes or 1,1,1,3,3-pentafluorobutane by thermal, base-induced or catalytic dehydrohalogenation, especially by catalytic dehydrofluorination. The C4 compounds have the especial advantage that they allow the direct etching of photoresist-protected items where the pattern of the photoresist is defined by light of a wavelength of 193 nm, or even “extreme UV light”. Nodes with a very narrow gap, for example, nodes with gaps of 130 nm, 90 nm, 45 or 32 nm and even 22 nm can be produced.
    Type: Application
    Filed: July 14, 2009
    Publication date: June 9, 2011
    Applicant: SOLVAY FLUOR GMBH
    Inventor: Marcello Riva
  • Patent number: 7955440
    Abstract: After a water film is formed on a wafer front surface in a chamber, the water film is supplied sequentially with an oxidizing component of an oxidation gas, an organic acid component of an organic acid mist, an HF component of an HF gas, the organic acid mist, and the oxidizing component of the oxidation gas. As a result, the HF component and the organic acid component provide cleaning effect on the wafer surface, and a concentration of the cleaning components in the water film within a wafer surface can be even.
    Type: Grant
    Filed: November 21, 2008
    Date of Patent: June 7, 2011
    Assignee: Sumco Corporation
    Inventors: Shigeru Okuuchi, Kazushige Takaishi
  • Patent number: 7955982
    Abstract: Disclosed is a method for smoothing the surface of at least one side of a wafer which is obtained by slicing a semiconductor ingot. In this method, a fluid is applied according to projections of the wafer surface, thereby reducing the projections. Alternatively, a fluid is applied over the wafer surface, thereby smoothing the entire surface of the wafer while reducing the projections in the wafer surface.
    Type: Grant
    Filed: January 17, 2007
    Date of Patent: June 7, 2011
    Assignee: Sumco Corporation
    Inventors: Takeo Katoh, Tomohiro Hashii, Katsuhiko Murayama, Sakae Koyata, Kazushige Takaishi
  • Publication number: 20110130001
    Abstract: A substrate processing apparatus cleaning method that includes: containing a cleaning gas in a reaction tube without generating a gas flow of the cleaning gas in the reaction tube by supplying the cleaning gas into the reaction tube and by completely stopping exhaustion of the cleaning gas from the reaction tube or by exhausting the cleaning gas at an exhausting rate which substantially does not affect uniform diffusion of the cleaning gas in the reaction tube from at a point of time of a period from a predetermined point of time before the cleaning gas is supplied into the reaction tube to a point of time when several seconds are elapsed after starting of supply of the cleaning gas into the reaction tube; and thereafter exhausting the cleaning gas from the reaction tube.
    Type: Application
    Filed: November 24, 2010
    Publication date: June 2, 2011
    Inventors: Kazuyuki OKUDA, Toru Kagaya, Masanori Sakai
  • Publication number: 20110130010
    Abstract: A method of manufacturing a semiconductor device includes preparing a semiconductor wafer having a device area, an end face, and a surface peripheral area located outside the device area and between the end face and the device area. Forming a Cu layer on the semiconductor wafer and rotating the wafer in a horizontal plane. Emitting a first liquid from an edge nozzle towards the surface peripheral area which selectively removes a first unnecessary material in the surface peripheral area. Emitting a protecting liquid toward the semiconductor wafer, thereby protecting the device area from the first liquid. An angle of a longitudinal axis of the edge nozzle with respect to a tangent of the semiconductor wafer at a point, where the longitudinal axis of the edge nozzle intersects the end face of the wafer, is set in the range of 0 to 90 degrees in plan view.
    Type: Application
    Filed: November 24, 2010
    Publication date: June 2, 2011
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Shinya YAMASAKI, Hidemitsu AOKI
  • Publication number: 20110130009
    Abstract: Improved removal of ion-implanted photoresist in a single wafer front-end wet processing station is achieved by combining gaseous ozone and heated sulfuric acid such that a gas/liquid dispersion or foam of ozone in sulfuric acid is applied in a layer to the wafer surface to be treated.
    Type: Application
    Filed: November 30, 2009
    Publication date: June 2, 2011
    Applicant: LAM RESEARCH AG
    Inventors: Robert KUMNIG, Reinhard SELLMER
  • Patent number: 7951724
    Abstract: The present invention is a wafer fixture comprising a housing body, a thrust plate, a flexure clamp, gaskets, flexure pins on an inner circumference of the housing body, locking grooves on an outer circumference of the flexure clamp, and a handle. A wafer may be placed between the gaskets of the housing body and the thrust plate. The flexure clamp may be placed over the thrust plate and secured to the housing body by rotating the flexure clamp such that locking grooves of the fixture plate mate with the flexure pins on the inner circumference of the housing body. The present invention in yet another embodiment is a wafer etch tool comprising a housing, a flexure clamp, and means for securing a wafer between the housing and the flexure clamp upon rotation of the flexure clamp within the housing.
    Type: Grant
    Filed: January 15, 2010
    Date of Patent: May 31, 2011
    Assignee: Advanced Research Corporation
    Inventors: Steve Fyten, Matthew P. Dugas, John J. Marchetti
  • Publication number: 20110117749
    Abstract: A method for reducing line width roughness (LWR) of a feature in an etch layer below a patterned photoresist mask having mask features is provided. The method includes (a) non-etching plasma pre-etch treatment of the photoresist mask, and (b) etching of a feature in the etch layer through the pre-treated photoresist mask using an etching gas. The non-etching plasma pre-etch treatment includes (a1) providing a treatment gas containing H2 and COS, (a2) forming a plasma from the treatment gas, and (a3) stopping the treatment gas.
    Type: Application
    Filed: November 17, 2009
    Publication date: May 19, 2011
    Applicant: LAM RESEARCH CORPORATION
    Inventors: Ben-Li SHEU, Martin SHIM, Jonathan KIM
  • Publication number: 20110117696
    Abstract: Disclosed are etching compositions and processes of using the same for etching the surface of CdTe-containing layers.
    Type: Application
    Filed: November 18, 2010
    Publication date: May 19, 2011
    Applicant: Air Liquide Electronics U.S. LP
    Inventor: Matthew L. FISHER
  • Publication number: 20110117752
    Abstract: The present invention relates to a method and system for removing a sacrificial layer from an MEMS structure or from any other semiconductor substrate that includes a sacrificial layer. The above etching method and system use densified carbon dioxide, fluorine compounds, and co-solvents as the processing fluid and are capable of removing the sacrificial layer in a short period of time without incurring damage on the structural layer or incurring stiction between structures. In addition, the above etching method and system do not create etching residue and thus do not require a separate cleaning process.
    Type: Application
    Filed: November 18, 2009
    Publication date: May 19, 2011
    Inventors: Kwon Taek Lim, Jae Hyeon Bae
  • Publication number: 20110117732
    Abstract: Methods for selectively depositing high quality epitaxial material include introducing pulses of a silicon-source containing vapor while maintaining a continuous etchant flow. Epitaxial material is deposited on areas of a substrate, such as source and drain recesses. Between pulses, the etchant flow continues such that lower quality epitaxial material may be removed, as well as any non-epitaxial material that may have been deposited. The pulse of silicon-source containing vapor may be repeated until a desired thickness of epitaxial material is selectively achieved in semiconductor windows, such as recessed source/drain regions.
    Type: Application
    Filed: November 17, 2009
    Publication date: May 19, 2011
    Applicant: ASM America, Inc.
    Inventors: Matthias Bauer, Shawn G. Thomas
  • Patent number: 7944025
    Abstract: The invention includes a process whereby a solvent is utilized to remove soluble portions of a resist, and subsequently the solvent can be removed with a gas-fortified liquid. In particular aspects, the gas-fortified liquid emits bubbles during the removal of the solvent. Additionally, the gas-fortified liquid can be utilized to remove residual resist scum, and in such aspects the gas-fortified liquid can emit bubbles during the scum removal.
    Type: Grant
    Filed: June 13, 2006
    Date of Patent: May 17, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Trung Tri Doan, Terry L. Gilton
  • Publication number: 20110111543
    Abstract: A thin-film transistor including a gate electrode, a drain electrode, and a source electrode is formed. A first insulating film is formed so as to cover the thin-film transistor. A second insulating film is formed on the first insulating film. A transparent conductive film is formed on the second insulating film. An etching resist which is patterned by a photolithography process is formed on the transparent conductive film. A first transparent electrode is formed by patterning the transparent conductive film by a first etching using the etching resist. A penetration hole is formed in the second insulating film at a position above one of the drain electrode and the source electrode by a second etching which is performed using the etching resist on a surface of the second insulating film exposed from the first transparent electrode.
    Type: Application
    Filed: November 9, 2010
    Publication date: May 12, 2011
    Inventor: Kikuo ONO
  • Publication number: 20110104904
    Abstract: A method of processing a silicon wafer including sequentially carrying out the steps of (1) preparing a lapped semiconductor silicon wafer, (2) cleaning the wafer with a surfactant, (3) cleaning the wafer with alkali or acid, and (4) etching the wafer with high-purity sodium hydroxide.
    Type: Application
    Filed: November 1, 2010
    Publication date: May 5, 2011
    Applicant: SILTRONIC AG
    Inventor: Shigeki Nishimura
  • Publication number: 20110104905
    Abstract: The present invention provides a chromium-free etching composition suitable for treating various silicon-containing surfaces, including strained silicon on insulator surfaces as well as stressed silicon surfaces. The novel and inventive etching composition in accordance with the present invention includes hydrofluoric acid, nitric acid, acetic acid and an alkali iodide, preferably potassium iodide, present in an amount of 1 mmol/100 ml or more.
    Type: Application
    Filed: April 24, 2009
    Publication date: May 5, 2011
    Inventors: Alexandra Abbadie, Bernd Kolbesen, Jochen Maehliss
  • Patent number: 7935554
    Abstract: Provided are a semiconductor light emitting device having a nano pattern and a method of manufacturing the semiconductor light emitting device. The semiconductor light emitting device includes: a semiconductor layer comprising a plurality of nano patterns, wherein the plurality of nano patterns are formed inside the semiconductor layer; and an active layer formed on the semiconductor layer. The optical output efficiency is increased and inner defects of the semiconductor light emitting device are reduced.
    Type: Grant
    Filed: March 19, 2009
    Date of Patent: May 3, 2011
    Assignee: Samsung LED Co., Ltd.
    Inventors: Jeong-wook Lee, Youn-joon Sung, Ho-sun Paek, Hyun-soo Kim, Joo-sung Kim, Suk-ho Yoon
  • Patent number: 7935977
    Abstract: Disclosed is a method of manufacturing an organic light emitting device, an organic light emitting device manufactured by using the method, and an electronic device including the organic light emitting device. The method includes (a) forming an insulating layer on a lower electrode, (b) etching the insulating layer to form an opening ranging from an upper surface of the insulating layer to the lower electrode so that an overhang structure having a lowermost circumference that is larger than an uppermost circumference is formed, (c) forming a conductive layer on an upper surface of the lower electrode in the opening and a surface of the insulating layer other than the overhang structure, (d) forming an organic material layer on the conductive layer formed on the upper surface of the lower electrode in the opening, and (e) forming an upper electrode on an upper surface of the conductive layer disposed on the upper surface of the insulating layer and an upper surface of the organic material layer.
    Type: Grant
    Filed: July 25, 2007
    Date of Patent: May 3, 2011
    Assignee: LG Chem, Ltd.
    Inventors: Jung-Hyoung Lee, Jae-Seung Lee, Jung-Bum Kim