Abstract: One embodiment of the present invention provides a process for obtaining high-quality boundaries for individual multilayer structures which are fabricated on a trench-partitioned substrate. During operation, the process receives a trench-partitioned substrate wherein the substrate surface is partitioned into arrays of isolated deposition platforms which are separated by arrays of trenches. The process then forms a multilayer structure, which comprises a first doped layer, an active layer, and a second doped layer, on one of the deposition platforms. Next, the process removes sidewalls of the multilayer structure.

Abstract: An etching method that uses an etch reactant retained within at least a semi-solid media (120, 220, 224, 230). The etch reactant media is applied to selectively etch a surface layer (106, 218, 222). The etch reactant media may be applied to remove metal shorts (222), smearing and eaves resulting from CMP or in failure analysis for uniform removal of a metal layer (218) without damaging the vias, contact, or underlying structures.

Abstract: Embodiments of the invention include methods of etching nanodots, to methods of removing nanodots from substrates, and to methods of fabricating integrated circuit devices. In one embodiment, a method of etching nanodots that include a late transition metal includes exposing such nanodots to a gas comprising a phosphorus and halogen-containing compound and an oxidizing agent. After the exposing, the nanodots which are remaining and were exposed are etched (either partially or completely) with an aqueous solution comprising HF.

Abstract: Treating thin film amorphous or mono- or multi-crystalline silicon wafer substrate for use in a photovoltaic cell, the wafer substrate having at least one of a pn- or np junction and a partial phosphosilicate or borosilicate glass layer on a top surface of the wafer substrate, to increase at least one of (a) the sheet resistance of he wafer and (b) the power density level of the photovoltaic cell made from said wafer. The treatment solution being an acidic treatment solution of a buffered oxide etch (BOE) solution of at least one tetraalkylammonium hydroxide, acetic acid, at least one non-ionic surfactant, at least one metal chelating agent, a metal free source of ammonia, a metal free source, of fluoride ions, and water, mixed with an oxidizer solution and optionally water.

Abstract: The present disclosure relates to an implantable medical device. The implantable medical device includes a component comprising a first substrate bonded to a second substrate. A method for forming the component includes removing a first portion of tin (Sn) from gold tin (AuSn) through a halogen plasma. A first portion of gold (Au) is exposed in response to removing the first portion of the Sn. The first portion of the Au through a wet etch. A second portion of the Sn is exposed in response to removing the first portion of Au.

Abstract: A method for forming an offset spacer of a MOS device is disclosed. The method includes the steps of: providing a substrate having a gate structure thereon; forming a dielectric stack on the substrate and the gate structure, wherein the dielectric stack comprises a first dielectric layer, a second dielectric layer, a third dielectric layer, and a fourth dielectric layer; and performing an etching process on the dielectric stack to form an offset spacer around the gate structure.

Abstract: A semiconductor on insulator (SOI) wafer includes a semiconductor substrate having first and second main surfaces opposite to each other. A dielectric layer is disposed on at least a portion of the first main surface of the semiconductor substrate. A device layer has a first main surface and a second main surface. The second main surface of the device layer is disposed on a surface of the dielectric layer opposite to the semiconductor substrate. A plurality of intended die areas are defined on the first main surface of the device layer. The plurality of intended die areas are separated from one another. A plurality of die access trenches are formed in the semiconductor substrate from the second main surface. Each of the plurality of die access trenches are disposed generally beneath at least a respective one of the plurality of intended die areas.

Abstract: Various semiconductor devices and methods of testing such devices are disclosed. In one aspect, a method of manufacturing is provided that includes forming a bore from a backside of a semiconductor chip through a buried insulating layer and to a semiconductor device layer of the semiconductor chip. A conductor structure is formed in the bore to establish an electrically conductive pathway between the semiconductor device layer and the conductor structure. The conductor structure may provide a diagnostic pathway.

Abstract: Disclosed is a method of etching semiconductor nanocrystals, which includes dissolving semiconductor nanocrystals in a halogenated solvent containing phosphine so that anisotropic etching of the surface of semiconductor nanocrystals is induced or adding a primary amine to a halogenated solvent containing phosphine and photoexciting semiconductor nanocrystals thus inducing isotropic etching of the surface of the nanocrystals, thereby reproducibly controlling properties of semiconductor nanocrystals including absorption wavelength, emission wavelength, emission intensity, average size, size distribution, shape, and surface state.

Abstract: A method of fabricating a semiconductor device including providing a substrate having a front surface and a back surface. A masking element is formed on the front surface of the substrate. The masking element includes a first layer having a first opening and a second layer having a second opening of a greater width than the first opening. The second opening is a tapered opening. The method further includes etching a tapered profile via extending from the front surface to the back surface of the substrate using the formed masking element.

Abstract: A wafer thinning apparatus for treating wafers each having at least a circuit-forming surface thereof protected, by immersing the wafers in a treating solution. The apparatus includes a support table for receiving, as placed thereon, containers each containing a plurality of wafers in one of groups into which the wafers are sorted according to predetermined ranges of thickness, a treating tank for storing the treating solution and receiving the containers, a transport mechanism for transporting the containers between the support table and the treating tank, and a control unit for controlling the transport mechanism to transport the containers successively to the treating tank, and for changing an immersion time of the containers in the treating tank for each group.

Abstract: A method of simultaneously cleaning inorganic and organic contaminants from semiconductor wafers and micro-etching the semiconductor wafers. After the semiconductor wafers are cut or sliced from ingots, they are contaminated with cutting fluid as well as metal and metal oxides from the saws used in the cutting process. Aqueous alkaline cleaning and micro-etching solutions containing alkaline compounds and mid-range alkoxylates are used to simultaneously clean and micro-etch the semiconductor wafers.

Abstract: A first film and a second film are formed on a semiconductor substrate in this order. A resist pattern is formed on the second film. An opening is formed by removing the second film exposed between the resist pattern at a state where the second film remains on the bottom. A first removal preventing film is formed on the side wall of the opening and the residual film is removed at a state where the projecting part of the second film protruding from the side wall to the opening remains. The first film exposed in the opening is removed. A second removal preventing film is formed on the first removal preventing film and the surface of the semiconductor substrate exposed in the opening is removed at a state where the projecting part of the semiconductor substrate protruding from the side wall to the opening remains and a round part is formed at the projecting part of the semiconductor substrate. The semiconductor substrate exposed in the opening is further removed.

Abstract: A field effect transistor includes a high resistance layer on a substrate, a semiconductor operation layer that is formed on the high resistance layer and includes a channel layer that has the carbon concentration of not more than 1×1018 cm?3 and has the layer thickness of more than 10 nm and not more than 100 nm, a recess that is formed up to the inside of the channel layer in the semiconductor operation layer, source and drain electrodes that are formed on the semiconductor operation layer with the recess intervening therebetween, a gate insulating film that is formed on the semiconductor operation layer so as to cover the recess, and a gate electrode that is formed on the gate insulating film in the recess.

Abstract: Some embodiments include methods of forming capacitors. Storage nodes are formed within a material. The storage nodes have sidewalls along the material. Some of the material is removed to expose portions of the sidewalls. The exposed portions of the sidewalls are coated with a substance that isn't wetted by water. Additional material is removed to expose uncoated regions of the sidewalls. The substance is removed, and then capacitor dielectric material is formed along the sidewalls of the storage nodes. Capacitor electrode material is then formed over the capacitor dielectric material. Some embodiments include methods of utilizing a silicon dioxide-containing masking structure in which the silicon dioxide of the masking structure is coated with a substance that isn't wetted by water.

Abstract: The present invention is directed to provide an etching agent for a semiconductor substrate, which is capable of etching a titanium (Ti)-based metal film or a tungsten (W)-based metal film on a semiconductor substrate and an etching method using relevant etching agent, and relates to a liquid for preparing the etching agent for a semiconductor substrate composed of a solution comprising (A) hydrogen peroxide, (B) a phosphonic acid chelating agent having a hydroxyl group, (C) a basic compound, and (D-1) a copper anticorrosive and/or (D-2) 0.

Abstract: The present invention provides a method of wet etching a silicon slice including a silicon substrate and a metal film layer thereon comprising steps of: performing lithographic process to the silicon slice forming a masked silicon slice comprising the silicon substrate and a partially masked metal film thereon; immersing the masked silicon slice into an etchant; rotating the masked silicon slice in the etchant; injecting high-purity nitrogen gas into the etchant for agitating the etchant; removing the masked silicon slice out of the etchant, upon completion of etching; and rinsing the masked silicon slice with deionized water.

Abstract: An etching process for selectively etching exposed metal surfaces of a substrate and forming a conductive capping layer over the metal surfaces is described. In some embodiments, the etching process involves oxidation of the exposed metal to form a metal oxide that is subsequently removed from the surface of the substrate. The exposed metal may be oxidized by using solutions containing oxidizing agents such as peroxides or by using oxidizing gases such as those containing oxygen or ozone. The metal oxide produced is then removed using suitable metal oxide etching agents such as glycine. The oxidation and etching may occur in the same solution. In other embodiments, the exposed metal is directly etched without forming a metal oxide. Suitable direct metal etching agents include any number of acidic solutions. The process allows for controlled oxidation and/or etching with reduced pitting.

Abstract: A method for manufacturing a semiconductor device includes: exposing an insulating film including a siloxane bond to an energy beam or plasma; and exposing the insulating film to a gas (excluding N2 and H2O gases) including at least one element selected from the group consisting of hydrogen, carbon, nitrogen and silicon, as an constituent element, wherein, in the exposing to the gas, after a relative permittivity of the insulating film descends by the exposing the insulating film to the gas, the exposing is completed before a time point when the relative permittivity of the insulating film first ascends.

Abstract: An inkjet ink comprises phosphoric acid; one or more solvents for the phosphoric acid, preferably ethyl lactate and water; and one or more aprotic organic sulfoxides, preferably dimethyl sulfoxide (DMSO) or dimethyl sulfone (SMSO2). The inks do not leave a carbon residue on heating and so are suited to use in etching and/or doping silicon wafers, e.g. in the production of crystalline silicon solar cells.

Abstract: A method and a system are described herein for applying etchant to edges of a plurality of wafers. The system includes a sump configured for holding etchant, a roller having an outer surface in fluid communication with the sump and configured to have etchant thereon, a wafer cassette configured to retain wafers positioned therein so that edges of the wafers are in contact with the roller. The cassette permits axial rotation of the wafers about an axis. A method of applying etchant to the edge of the wafer includes placing the wafer edge in contact with the roller and rotating the roller about a longitudinal axis of the roller. At least a portion of the roller contact an etchant contained in a sump during rotation so that etchant is applied to the wafer edge.

Abstract: A processing chamber successfully removes hardened photoresist via direct infrared radiation onto the wafer, in the presence of an acid such as sulfuric acid, optionally along with an oxidizer such as hydrogen peroxide. The processing chamber includes a fixture for holding and optionally rotating the wafer. An infrared irradiating assembly has infrared lamps outside of the processing chamber positioned to radiate infrared light into the processing chamber. The infrared lamps may be arranged to irradiate substantially the entire surface of a wafer on the rotor. A cooling assembly can be associated with the infrared radiating assembly to provide a quick cool down and avoid over-processing. Photoresist is removed using small amounts of chemical solutions.

Abstract: The present invention provides silicon nanostructures and their producing method. By employing a metal-assisted chemical etching method, the bottom of the produced silicon nanostructures, connected to the silicon substrate, is porous and side etched, such that the silicon nanostructures can be easily transferred to a hetero-substrate by a physical manner.

Abstract: A method for fabricating a micromirror in a wafer, including the steps of: depositing and etching layers forming two arms; etching the wafer such that in the back face only a thin portion of the wafer remains in the region of formation of the micromirror and the arms; performing an anisotropic etch, such that the thin portion remains only in the areas of the micromirror and the arms; and performing an isotropic etch to remove the thin portions under the arms, the etching step for forming the arms being performed following their shape and so as to form holes traversing the arms, the holes being positioned at edges of the region separating the micromirror and the wafer on both the side of the micromirror and the side of the portions of the wafer remaining after the anisotropic etching step. The invention also concerns the micromirror.

Abstract: Processes for forming high density gap-filling silicon oxide on a patterned substrate are described. The processes increase the density of gap-filling silicon oxide particularly in narrow trenches. The density may also be increased in wide trenches and recessed open areas. The densities of the gap-filling silicon oxide in the narrow and wide trenches/open areas become more similar following the treatment which allows the etch rates to match more closely. This effect may also be described as a reduction in the pattern loading effect. The process involves forming then planarizing silicon oxide. Planarization exposes a new dielectric interface disposed closer to the narrow trenches. The newly exposed interface facilitates a densification treatment by annealing and/or exposing the planarized surface to a plasma.

Abstract: Controlling scribe line orientation during wet-bench processes has been found to improve yield and reduce particles from inadequate draining when the scribe lines are oriented about 45 degrees from horizontal. A wafer is provided to the wet bench apparatus and immersed in a solution. When removed from the solution, the wafer should be oriented vertically with scribe lines oriented about 45 degrees, plus or minus 15 degrees from horizontal. Wafer scribe line orientation are checked and changed before the wet bench process or during the wet bench processing.

Abstract: A semiconductor manufacturing apparatus and a semiconductor manufacturing method, and has as one object to process a wafer easily and stably irrespective of thickness. To achieve the above object, a semiconductor manufacturing apparatus includes: an open-topped cassette that encases a semiconductor substrate; a plurality of processors for performing a predetermined processing of the semiconductor substrate; and a transporting mechanism that transports the cassette encasing the semiconductor substrate between the plurality of processors.

Abstract: A process for etching a silicon layer disposed on a substrate, including anisotropically etching a first trench in the silicon layer; selectively anisotropic wet etching silicon surfaces in the first trench, the wet etching comprising exposing the silicon surfaces to an aqueous composition including an aromatic tri(lower)alkyl quaternary onium hydroxide, and an unsymmetrical tetraalkyl quaternary phosphonium salt; in which the wet etching etches (110) and (100) planes of the silicon layer at about equal rates and preferentially to the (111) plane to form an enlarged trench having a sidewall in the (111) plane. A silicon alloy may be epitaxially deposited in the thus-produced trench as part of a process of introducing stress into at least a portion of the silicon layer.

Abstract: The invention is directed to a method for removing copper oxide from a copper surface to provide a clean copper surface, wherein the method involves exposing the copper surface containing copper oxide thereon to an anhydrous vapor containing a carboxylic acid compound therein, wherein the anhydrous vapor is generated from an anhydrous organic solution containing the carboxylic acid and one or more solvents selected from hydrocarbon and ether solvents.

Abstract: A method is provided for processing a wafer used in fabricating semiconductor devices. The method can comprise forming high-aspect ratio features on the wafer, which is followed by wet processing and drying. During drying, pattern collapse can occur. This pattern collapse can be repaired to allow for additional processing of the wafer. In some instance, pattern collapse can be repaired via etching where the etching breaks bonds that can have formed during pattern collapse.

Abstract: A method for chemically treating a disc-shaped substrate having a bottom surface, a top surface and side surfaces by contacting a process medium that is fluid-chemically active with at least the bottom surface of the substrate. The substrate is moved relative to the process medium while forming a triple line between the substrate, the substrate medium and the atmosphere surrounding the substrate and medium. In order to chemically remove errors, particularly in the side surfaces, relative motion should be carried out while avoiding a contacting of the process medium with the top surface of the substrate, where the triple line is formed at a desired height of the side surface facing away from the process medium flow side in relation to the relative motion between the substrate and the process medium. In this way, the atmosphere can be adjusted in relation to the partial pressures of the components in the process medium such that the top surface preserves hydrophobic characteristics.

Abstract: A liquid composition used to carry out crystal anisotropic etching of a silicon substrate provided with an etching mask formed of a silicon oxide film with the silicon oxide film used as a mask includes cesium hydroxide, an alkaline organic compound, and water.

Abstract: A vertical cavity surface emitting laser (VCSEL) (100) has a substrate (104), on which are disposed first and second distributed Bragg reflectors (DBRs) (106, 112), each DBR comprising a stack of layers of alternating refractive index, an active layer (108) disposed between the DBRs, and an aperture layer (110) disposed either between the DBRs or within one of the DBRs. The aperture layer (110) has a border (116) having an internal boundary with a plurality of indented portions defining one or more apertures. Such a VCSEL is easily manufacturable and provides a narrow bandwidth output, as well as mitigating at least some of the problems of prior art VCSELs. Mesa (102) may be etched to be non-circular and subsequent selective oxidation of aperture layer (110) results in a non-circular current confinement aperture (114) promoting higher-order lateral modes (LP21).

Abstract: A micro-hotplate is provided in the form of a device comprising a sensor and one or more resistive heaters within the micro-hotplate arranged to heat the sensor. Furthermore a controller is provided for applying a bidirectional drive current to at least one of the heaters to reduce electromigration. The controller also serves to drive the heater at a substantially constant temperature. Such an arrangement is advantageous over an arrangement in which a unidirectional DC drive current is applied to the heater. This is because the unidirectional drive current causes electromigration which results in an increase in resistance over time. This is undesirable because it can lead to failure of the micro-hotplate. In contrast, the application of the bidirectional current reduces electromigration and as a result there is insignificant change in the resistance of the heater over time and under high temperature.

Abstract: A semiconductor device manufacturing method includes: providing a laminated member in which at least a first GaAs layer, an InAlGaAs layer and a second GaAs layer are laminated on or above a substrate in this order; and etching the second GaAs layer using the InAlGaAs layer as an etching stopper layer. A ratio of In:Al of the InAlGaAs layer is in a range of approximately 4:6 to approximately 6:4 and a ratio of (In+Al):Ga of the InAlGaAs layer is in a range of approximately 1.5:8.5 to approximately 5:5.

Abstract: In etching processing of silicon, in particular anisotropic etching processing of silicon in a manufacturing step of MEMS parts, an etchant having a long life of etchant and an etching method are provided by suppressing a lowering of an etching rate at the time of warming which is characteristic of a hydroxylamine-containing etchant. A silicon etchant for anisotropically dissolving monocrystalline silicon therein, which is an alkaline aqueous solution containing (A) tetramethylammonium hydroxide, (B) hydroxylamine and (C) carbon dioxide (CO2) and/or a carbonic acid salt of tetramethylammonium and having a pH of 13 or more, and an etching method of silicon using this etchant are provided.

Abstract: A method of forming a sensor with an embedded cavity can include forming at least one cavity (50) in a substrate (52). The cavity (50) can include at least one membrane wall (54) having a plurality of holes (64) in the membrane wall (54), the plurality of holes (64) being formed in a two-dimensional array. A piezoresistive system (58) can be mechanically associated with the membrane wall (54). The method can be a front-side or back-side process for forming the cavity (50). The membrane (54) simultaneously acts as a diaphragm and a fluid passage into the cavity (50). Such sensors can be suitable as pressure sensors, chemical sensors, flow sensors and the like.

Abstract: A polished semiconductor wafer has a front surface and a back surface and an edge R, which is located at a distance of a radius from a center of the semiconductor wafer, forms a periphery of the semiconductor wafer and is part of a profiled boundary of the semiconductor wafer. The maximum deviation of the flatness of the back surface from an ideal plane in a range between R-6 mm and R-1 mm of the back surface is 0.7 ?m or less. A process for producing the semiconductor wafer, comprises at least one treatment of the semiconductor wafer with a liquid etchant and at least one polishing of at least a front surface of the semiconductor wafer, the etchant flowing onto a boundary of the semiconductor wafer during the treatment, and the boundary of the semiconductor wafer which faces the flow of etchant being at least partially shielded from being struck directly by the etchant. The shielding extends in the direction of a thickness d of the semiconductor wafer and is at least d+100 ?m long.

Abstract: The present invention in one embodiment provides an etch method that includes providing a structure including a tungsten (W) portion and a titanium nitride (TiN) portion; applying a first etch feed gas of sulfur hexafluoride (SF6) and oxygen (O2), in which the ratio of sulfur hexafluoride (SF6) to oxygen (O2) ranges from 1:3.5 to 1:4.5; and applying a second etch feed gas of nitrogen trifluoride (NF3), helium (He) and chlorine (Cl2), in which the ratio of nitrogen trifluoride (NF3) to chlorine (Cl2) ranges from 1:5 to 2:5 and the ratio of helium (He) to nitrogen trifluoride (NF3) and chlorine (Cl2) ranges from 1:3 to 1:1.

Abstract: Provided is a photoresist that includes a polymer having a backbone that is breakable and a photo acid generator that is free of bonding from the polymer. Further, provided is a method of fabricating a semiconductor device. The method includes providing a device substrate. A material layer is formed over the substrate. A photoresist material is formed over the material layer. The photoresist material has a polymer that includes a backbone. The photoresist material is patterned to form a patterned photoresist layer. A fabrication process is then performed to the material layer, wherein the patterned photoresist layer serves as a mask in the fabrication process. Thereafter, the patterned photoresist layer is treated in a manner that breaks the backbone of the polymer. The patterned photoresist layer is then removed.

Abstract: An exemplary method of patterning oxide layer and removing residual nitride includes steps of forming a first oxide layer, a nitride layer, a second oxide layer and a complex hard mask on a substrate in turn. The first oxide layer covers an insulating structure. The second oxide layer, the complex hard mask and the nitride layer are etched by utilizing a patterned photoresist as an etching mask, so as to expose the first oxide layer. In addition, the part of the nitride layer covering the insulating structure can be further removed. Accordingly, the present invention can effectively control layout patterns of material layers and doped regions and thereby can improve the performance of a narrow width device.

Abstract: In one implementation, a method is provided for etching a high k dielectric material in a plasma etch reactor, the method comprising plasma etching the high k dielectric material with a first plasma gas reactant mixture having BCl3. The high k dielectric material may include Al2O3 in a stack having a silicon layer. The etching may include supplying a passivation gas, for example C2H4, and may further include supplying a diluent gas such as a noble gas, for example He. In some implementations, the etching may be performed with a reactive ion etch process.

Abstract: Some embodiments include methods of forming capacitors. Storage nodes are formed within a material. The storage nodes have sidewalls along the material. Some of the material is removed to expose portions of the sidewalls. The exposed portions of the sidewalls are coated with a substance that isn't wetted by water. Additional material is removed to expose uncoated regions of the sidewalls. The substance is removed, and then capacitor dielectric material is formed along the sidewalls of the storage nodes. Capacitor electrode material is then formed over the capacitor dielectric material. Some embodiments include methods of utilizing a silicon dioxide-containing masking structure in which the silicon dioxide of the masking structure is coated with a substance that isn't wetted by water.

Abstract: C4 compounds selected from the group of trifluorobutadienes and tetrafluorobutenes can be used as etching gases, especially for anisotropic etching in the production of etched items, for example, of semiconductors, e.g. semiconductor memories or semiconductor logic circuits, flat panels, or solar cells. Preferred compounds are 1,1,3-trifluoro-1,3-butadiene, (E)-1,1,1,3-tetrafluoro-2-butene, 2,4,4,4-tetrafluoro-1-butene and (Z)-1,1,1,3-tetrafluoro-2-butene which can be obtained from halotetrafluorobutanes or 1,1,1,3,3-pentafluorobutane by thermal, base-induced or catalytic dehydrohalogenation, especially by catalytic dehydrofluorination. The C4 compounds have the especial advantage that they allow the direct etching of photoresist-protected items where the pattern of the photoresist is defined by light of a wavelength of 193 nm, or even “extreme UV light”. Nodes with a very narrow gap, for example, nodes with gaps of 130 nm, 90 nm, 45 or 32 nm and even 22 nm can be produced.

Abstract: After a water film is formed on a wafer front surface in a chamber, the water film is supplied sequentially with an oxidizing component of an oxidation gas, an organic acid component of an organic acid mist, an HF component of an HF gas, the organic acid mist, and the oxidizing component of the oxidation gas. As a result, the HF component and the organic acid component provide cleaning effect on the wafer surface, and a concentration of the cleaning components in the water film within a wafer surface can be even.

Abstract: Disclosed is a method for smoothing the surface of at least one side of a wafer which is obtained by slicing a semiconductor ingot. In this method, a fluid is applied according to projections of the wafer surface, thereby reducing the projections. Alternatively, a fluid is applied over the wafer surface, thereby smoothing the entire surface of the wafer while reducing the projections in the wafer surface.

Abstract: A method of manufacturing a semiconductor device includes preparing a semiconductor wafer having a device area, an end face, and a surface peripheral area located outside the device area and between the end face and the device area. Forming a Cu layer on the semiconductor wafer and rotating the wafer in a horizontal plane. Emitting a first liquid from an edge nozzle towards the surface peripheral area which selectively removes a first unnecessary material in the surface peripheral area. Emitting a protecting liquid toward the semiconductor wafer, thereby protecting the device area from the first liquid. An angle of a longitudinal axis of the edge nozzle with respect to a tangent of the semiconductor wafer at a point, where the longitudinal axis of the edge nozzle intersects the end face of the wafer, is set in the range of 0 to 90 degrees in plan view.

Abstract: Improved removal of ion-implanted photoresist in a single wafer front-end wet processing station is achieved by combining gaseous ozone and heated sulfuric acid such that a gas/liquid dispersion or foam of ozone in sulfuric acid is applied in a layer to the wafer surface to be treated.

Abstract: A substrate processing apparatus cleaning method that includes: containing a cleaning gas in a reaction tube without generating a gas flow of the cleaning gas in the reaction tube by supplying the cleaning gas into the reaction tube and by completely stopping exhaustion of the cleaning gas from the reaction tube or by exhausting the cleaning gas at an exhausting rate which substantially does not affect uniform diffusion of the cleaning gas in the reaction tube from at a point of time of a period from a predetermined point of time before the cleaning gas is supplied into the reaction tube to a point of time when several seconds are elapsed after starting of supply of the cleaning gas into the reaction tube; and thereafter exhausting the cleaning gas from the reaction tube.

Abstract: The present invention is a wafer fixture comprising a housing body, a thrust plate, a flexure clamp, gaskets, flexure pins on an inner circumference of the housing body, locking grooves on an outer circumference of the flexure clamp, and a handle. A wafer may be placed between the gaskets of the housing body and the thrust plate. The flexure clamp may be placed over the thrust plate and secured to the housing body by rotating the flexure clamp such that locking grooves of the fixture plate mate with the flexure pins on the inner circumference of the housing body. The present invention in yet another embodiment is a wafer etch tool comprising a housing, a flexure clamp, and means for securing a wafer between the housing and the flexure clamp upon rotation of the flexure clamp within the housing.