Abstract: In some implementations, a method is provided in a plasma processing chamber for stabilizing etch-rate distributions during a process transition from one process step to another process step. The method includes performing a pre-transition compensation of at least one other process parameter so as to avoid unstable plasma states by inhibiting formation of a parasitic plasma during the process transition. In some implementations, a method is provided for processing a workpiece in plasma processing chamber, which includes inhibiting deviations from an expected etch-rate distribution by avoiding unstable plasma states during a process transition from one process step to another process step.

Abstract: A method for manufacturing an array substrate of liquid crystal display is performed with the following steps: providing a substrate having gate lines, a gate insulating layer and an active layer pattern formed thereon in this order; depositing a first transparent conductive layer and a source/drain metal layer in this order on the substrate; forming a photoresist layer on the source/drain metal layer through a triple-tone mask; performing a wet-etching process on the source/drain metal layer and the first transparent conductive layer exposed from the photoresist layer; performing a first ashing process on the photoresist layer and performing a dry-etching process on the source/drain metal layer, the first transparent conductive layer and the active layer pattern exposed by the first ashing process; performing a second ashing process on the photoresist layer and performing a wet-etching process on the source/drain metal layer exposed by the second ashing process; and removing the remaining photoresist layer.

Abstract: A method and system for forming dual damascene structures in a semiconductor package. In one embodiment, the method includes forming an intermediate dielectric layer on a bottom stop layer; forming an ashing removable dielectric layer on the intermediate dielectric layer; forming a patterned photoresist layer above the ashing removable dielectric layer in the semiconductor structure; and defining an in-situ hard mask in the ashing removable dielectric layer having an opening with a profile selected from the group consisting of a via, a trench, or a combination thereof. The profile of the in-situ mask preferably is capable of being transferred to the intermediate dielectric layer by etching.

Abstract: A semiconductor device includes an interlayer insulating layer including a plurality of trenches connecting to a number of via holes formed on a semiconductor substrate including lower interconnections, wherein widths of the trenches are greater than widths of the via holes, and metal interconnections formed by burying metal thin films in the via holes and the trenches. Depths of the trenches are adjusted differently from each other depending on required resistances of the metal interconnections.

Abstract: A semiconductor device according to an embodiment of the present invention includes a semiconductor substrate; a wiring formed in predetermined pattern above the semiconductor substrate, a first insulating film lying right under the wiring, and a second insulating film lying in a peripheral portion other than a portion right under the wiring, in which a surface layer of the first insulating film lying in a boundary surface between the first insulating film and the second insulating film is chemically modified to reinforce the surface layer.

Abstract: A method for forming a semiconductor structure includes the following steps. A hard mask layer is formed over a semiconductor region. The hard mask layer has inner portions that are thinner than its outer portions, and the inner portions define an exposed surface area of the semiconductor region. A portion of the semiconductor region is removed through the exposed surface area of the semiconductor region. The thinner portions of the hard mask layer are removed to expose surface areas of the semiconductor region underlying the thinner portions. An additional portion of the semiconductor region is removed through all exposed surface areas of the semiconductor region thereby forming a trench having an upper portion that is wider than its lower portion.

Abstract: In a method of forming a hole, an insulation layer is formed on a substrate, and a preliminary hole exposing the substrate is formed through the insulation layer. A photosensitive layer pattern including an organic polymer is then formed on the substrate to fill the preliminary hole. An etching gas including hydrogen fluoride (HF) or fluorine (F2) is then provided onto the photosensitive layer pattern to etch the insulation layer so that width of the preliminary hole is increased.

Abstract: A method of producing a semiconductor element includes the steps of forming a wiring portion layer on a substrate; forming an interlayer insulation layer over the substrate and the wiring portion layer, in which a third insulation film, a second insulation film, and a first insulation film are laminated in this order from the substrate; forming a mask pattern on the first insulation film; removing a contact hole forming area of the first insulation film through a wet etching process; removing a contact hole forming area of the second insulation film through an etching process; removing a contact hole forming area of the third insulation film through an etching process; and a contact hole forming step of forming a contact hole in the interlayer insulation layer so that a surface of the wiring portion layer is exposed.

Abstract: A shallow trench isolation (STI) structure and method for forming the same is provided that reduces defects in a nitride film used as a field oxide mask and variations in pad oxide thickness. Generally, the method involves depositing a nitride over pad oxide on a substrate using plasma enhanced chemical vapor deposition (PECVD), and patterning the PECVD nitride to form a field oxide mask. In certain embodiments, patterning the PECVD nitride involves: (i) forming a patterned resist layer on the PECVD nitride; (ii) etching in a process chamber at least one opening through at least the PECVD nitride; and (iii) stripping the patterned resist layer in-situ in the same process chamber in which the at least one opening was etched through the PECVD nitride using a fluorine based plasma. Other embodiments are also disclosed.

Abstract: Methods for etching a dielectric barrier layer with high selectivity to a dielectric bulk insulating layer are provided. In one embodiment, the method includes providing a substrate having a portion of a dielectric barrier layer exposed through a dielectric bulk insulating layer in a reactor, flowing a gas mixture containing H2 gas, fluorine containing gas, at least an insert gas into the reactor, and etching the exposed portion of the dielectric barrier layer selectively to the dielectric bulk insulating layer.

Abstract: A vacuum processing method includes mounting a sample to be processed on a sample mounting surface on a sample holder placed in a vacuum container whose inside can be depressurized, feeding a processing gas and electric field to a space above the sample holder inside of the vacuum container to generate plasma, and etching films of a plurality of layers laid over the surface of the sample into a predetermined shape. A heat conducting gas is fed between the sample mounting surface and the backside of the sample, and at the same time, the pressure of the heat conducting gas is changed stepwise in accordance with the progress of the processing of the films of a plurality of layers of the sample.

Abstract: Prototype semiconductor structures each including a semiconductor link portion and two adjoined pad portions are formed by lithographic patterning of a semiconductor layer on a dielectric material layer. The sidewalls of the semiconductor link portions are oriented to maximize hole mobility for a first-type semiconductor structures, and to maximize electron mobility for a second-type semiconductor structures. Thinning by oxidation of the semiconductor structures reduces the width of the semiconductor link portions at different rates for different crystallographic orientations. The widths of the semiconductor link portions are predetermined so that the different amount of thinning on the sidewalls of the semiconductor link portions result in target sublithographic dimensions for the resulting semiconductor nanowires after thinning.

Abstract: A method of fabricating a semiconductor device forms a micro-sized gate, and mitigates short channel effects. The method includes a pull-back process to form the gate on a substrate. The method also includes forming inner and outer spacers on the gate that are asymmetric to one another with respect to the gate, and using the spacers in forming junction regions in the substrate on opposite sides of the gate. In particular, the inner and outer spacers are formed on opposite sides of the gate so as to have different thicknesses at the bottom of the gate. The inner and outer junction regions are formed by doping the substrate before and after the spacers are formed. Thus, the inner and outer junction regions have extension regions under the inner and outer spacers, respectively, and the extension regions have different lengths.

Abstract: An accumulation-mode field effect transistor includes a drift region of a first conductivity type, channel regions of the first conductivity type over and in contact with the drift region, and gate trenches having sidewalls abutting the channel regions. The gate trenches extend into and terminate within the drift region. The transistor further includes a first plurality of silicon regions of a second conductivity type forming P-N junctions with the channel regions along vertical walls of the first plurality of silicon regions. The first plurality of silicon regions extend into the drift region and form P-N junctions with the drift region along bottoms of the first plurality of silicon regions.

Abstract: By forming a highly non-conformal stressed overlayer, such as a contact etch stop layer, the efficiency of the stress transfer into the respective channel region of a field effect transistor may be significantly increased. For instance, non-conformal PECVD techniques may be used for forming highly stressed silicon nitride in a non-conformal manner, thereby achieving higher transistor performance for otherwise identical stress conditions.

Abstract: Methods are provided for forming contacts for a semiconductor device. The methods may include depositing various materials, such as polysilicon, nitride, oxide, and/or carbon materials, over the semiconductor device. The methods may also include forming a contact hole and filling the contact hole to form the contact for the semiconductor device.

Abstract: Provided is a sacrifice layer formed on a first substrate. A thin film laminated body is formed on the sacrifice layer. A separation groove exposing the sacrifice layer is formed to divide the thin film laminated body into at least one thin film device. The sacrifice layer is partially removed using a dry etching process. After the partial removal of the sacrifice layer, a remaining sacrifice layer region maintains the thin film device on the first substrate. A supporting structure is temporarily joined to the thin film device. The thin film device joined to the supporting structure is separated from the first substrate. Then, the remaining sacrifice layer is removed. The thin film device joined to the supporting structure is joined to a second substrate. Finally, the supporting structure is separated from the thin film device.

Abstract: A plasma processing apparatus that enables polymer to be removed from an electrically insulated electrode. A susceptor of the plasma processing apparatus is disposed in a substrate processing chamber having a processing space therein. A radio frequency power source is connected to the susceptor. An upper electrode plate is electrically insulated from a wall of the substrate processing chamber and from the susceptor. A DC power source is connected to the upper electrode plate. A controller of the plasma processing apparatus determines a value of a negative DC voltage to be applied to the upper electrode plate in accordance with processing conditions for RIE processing to be carried out.

Abstract: Provided is near-field optical probe including: a cantilever arm support portion that is formed of a lower silicon layer of a silicon-on-insulator (SOI) substrate, the cantilever arm support portion having a through hole formed therein at a side of the lower silicon layer; and a cantilever arm forming of a junction oxidation layer pattern and an upper silicon layer pattern on the SOI substrate that are supported on an upper surface of the lower silicon layer and each have a smaller hole than the through hole, a silicon oxidation layer pattern having a tip including an aperture at a vertical end, corresponding with the hole on the upper silicon layer pattern, and an optical transmission prevention layer that is formed on the silicon oxidation layer pattern and does not cover the aperture.

Abstract: A semiconductor device having a capacitor and a method of fabricating the same may be provided. A method of fabricating a semiconductor device may include forming an etch stop layer and a mold layer sequentially on a substrate, patterning the mold layer to form a mold electrode hole exposing a portion of the etch stop layer, etching selectively the exposed etch stop layer by an isotropic dry etching process to form a contact electrode hole through the etch stop layer to expose a portion of the substrate, forming a conductive layer on the substrate and removing the conductive layer on the mold layer on the mold layer to form a cylindrical bottom electrode in the mold and contact electrode holes. The isotropic dry etching process may utilize a process gas including main etching gas and selectivity adjusting gas. The selectivity adjusting gas may increase an etch rate of the etch stop layer by more than an etch rate of the mold layer by the isotropic wet etching process.

Abstract: When an interconnect structure is built on porous ultra low k (ULK) material, the bottom of the trench and/or via is usually damaged by a following metallization process which may be suitable for dense higher dielectric materials. Embodiment of the present invention may provide a method of forming an interconnect structure on an inter-layer dielectric (ILD) material. The method includes steps of treating an exposed area of said ILD material to create a densified area, and metallizing said densified area.

Abstract: Provision of a process capable of preferably etching particularly PtMn used for a pin layer of an MRAM is an object: a dry etching method for performing dry etching on a layer including platinum and/or manganese by using pulse plasma and a production method of an MRAM, wherein the dry etching method is applied to processing of the pin layer. The MRAM is configured to have a memory portion comprising a magnetic memory element composed of tunnel magnetoresistive effect element formed by stacking a magnetic fixed layer having a fixed magnetization direction, a tunnel barrier layer and a magnetic layer capable of changing the magnetization direction.

Abstract: The present invention relates to an LED lamp including a pair of lead terminals 2 and 3, a cup portion 8 formed at an end of one of the lead terminals by denting the end and having a conical inner peripheral surface serving as a light-reflective surface 9, an LED chip 4, a transparent synthetic resin member 6 covering the ends of the paired lead terminals 2 and 3. The LED chip 4 includes an upper surface provided with an n-electrode 4d or a p-electrode 4e and a lower surface provided with a p-electrode 4e or an n-electrode 4d. An n-type semiconductor layer 4a and a p-type semiconductor layer 4b are provided between the n-electrode 4d and the p-electrode 4e and laminated to each other via a light emitting layer 4c interposed therebetween. The side surface of the LED chip 4 except for the n-electrode 4d and the p-electrode 4e is coated with light-transmitting synthetic resin 10 containing powder of a fluorescent material.

Abstract: Disclosed are an image sensor and a method for manufacturing the same, capable of increasing a light absorbing coefficient by forming a rough surface on a photodiode. The image sensor includes a semiconductor substrate with a plurality of photodiodes thereon having rough upper surfaces, a dielectric layer on the semiconductor substrate, a color filter layer on the dielectric layer, a planarization layer on an entire surface of the semiconductor substrate including the color filter layer, and a plurality of micro-lenses formed on the planarization layer to correspond to the color filter layer.

Abstract: A method of high density plasma (HDP) gap-filling with a minimization of gas phase nucleation (GPN) is provided. The method includes providing a substrate having a trench in a reaction chamber. Next, a first deposition step is performed to partially fill a dielectric material in the trench. Then, an etch step is performed to partially remove the dielectric material in the trench. Thereafter, a second deposition step is performed to partially fill the dielectric material in the trench. A reaction gas used in the second deposition step includes a carrier gas, an oxygen-containing gas, a silicon-containing gas, and a hydrogen-containing gas. After the carrier gas and oxygen-containing gas are introduced into the reaction chamber and a radio frequency (RF) power is turned on for a period of time, the silicon-containing gas and hydrogen-containing gas are introduced into the reaction chamber.

Abstract: A method of manufacturing a semiconductor device comprising a wiring structure that includes a vertical wiring section is disclosed. The method comprises a step of forming an interlayer insulation film made of a low dielectric constant material on a wiring layer, a step of forming a silicon oxide film by CVD using SiH4 gas and CO2 gas on the interlayer insulation film, a step of forming a chemically amplified resist film to cover the silicon oxide film, and a step of forming a first opening in a position on the chemically amplified resist film where the vertical wiring section is to be formed.

Abstract: In a substrate processing method of processing a substrate that includes an oxide layer as a mask layer and a silicon layer as a target layer to be processed, the silicon layer is etched while depositing a deposit on a surface of the oxide layer by a plasma generated from a mixed gas of a fluorine-based gas, a bromine-based gas, O2 gas, and SiCl4 gas to secure a thickness of the mask layer.

Abstract: A method of removing a portion of an oxide layer includes forming first byproducts by reacting a reaction gas with the oxide layer, the reaction gas including fluorine and nitrogen, reacting the reaction gas with the first byproducts to form second byproducts, and removing the second byproducts.

Abstract: A process is implemented to form a contact opening in a semiconductor device that includes a gate electrode on a substrate, a spacer on a sidewall of the gate electrode and a dielectric material covering the gate electrode. The process comprises forming a photoresist pattern on a surface of the dielectric material, etching the dielectric material until the bottom liner layer is exposed, forming a protective layer on a sidewall of the spacer while etching the dielectric material, and etching the bottom liner layer.

Abstract: A method of removing a silicon nitride or a nitride-based bottom etch stop layer in a copper damascene structure by etching the bottom etch stop layer is disclosed, with the method using a high density, high radical concentration plasma containing fluorine and oxygen and further optionally N2 and any one of inert gases, to minimize back sputtering of copper underlying the bottom etch stop layer and surface roughening of the low-k interlayer dielectric caused by the plasma.

Abstract: A method for fabricating a semiconductor device is provided. The method of fabricating a semiconductor device provides a semiconductor substrate; forming a first insulating layer, a first conductive layer and a chemical mechanical polishing (CMP) stop layer over the semiconductor substrate in sequence; forming openings in the chemical mechanical polishing (CMP) stop layer and the underlying first conductive layer to expose the first insulating layer, thereby leaving a patterned chemical mechanical polishing (CMP) stop layer and a patterned first conductive layer; forming a second insulating layer on the patterned chemical mechanical polishing (CMP) stop layer, filling in the openings; performing a planarization process to remove a portion of the second insulating layer until the patterned chemical mechanical polishing (CMP) stop layer is exposed, thereby leaving a remaining second insulating layer in the openings; removing the patterned chemical mechanical polishing (CMP) stop layer.

Abstract: Methods for removing photoresist from semiconductor structures are provided. In an exemplary embodiment, a method for removing photoresist from a semiconductor structure having a high-k dielectric material layer overlying a substrate comprises depositing a photoresist overlying the high-k dielectric material layer and patterning the photoresist. The temperature of the substrate is adjusted to a temperature of no less than about 400° C. and hydrogen gas is excited to form a hydrogen plasma of excited H and H2 species. The photoresist is subjected to the excited H and H2 species from the hydrogen plasma.

Abstract: An LED (20) includes a base (24), a chip (21) and an encapsulation (22) made of a transparent material. The base has a concave depression (240). The chip is mounted on a bottom of the concave depression. The first encapsulation is received in the depression for sealing the chip. The chip includes a light emitting surface (210). The encapsulation includes a light output surface (25) over the light emitting surface. The light output surface defines a plurality of recesses (26). A mixture (29) formed by mixing another transparent material (27) and fluorescent powder (28) is filled in each of the recesses.

Abstract: In a method for manufacturing a semiconductor device, insulation resistance of the porous film is stabilized, and leakage current between adjacent interconnects provides an improved reliability in signal propagation therethrough. The method includes: sequentially forming over a semiconductor substrate a porous film and a patterned resist film; forming a concave exposed surface of the substrate; forming a non-porous film covering the interior wall of the concave portion and the porous film; selectively removing the non-porous film from the bottom of the concave portion and the non-porous film by anisotropic etch; forming a barrier metal film covering the porous film and the interior wall; and forming a metallic film on the barrier metal film to fill the concave portion. The anisotropic etch process uses an etching gas with mixing ratio MR, 45?MR?100, where MR=((gaseous “nitrogen” containing compound)+(inert gas))/(gaseous “fluorine” containing compound).

Abstract: When a substrate is etched by using a processing gas including a first gas containing halogen and carbon and having a carbon number of two or less per molecule, while supplying the processing gas toward the substrate independently from a central and a peripheral portion of a gas supply unit, which face the central and the periphery part of the substrate respectively, the processing gas is supplied such that a gas flow rate is greater in the central portion than in the peripheral portion. When the substrate is etched by using a processing gas including a second gas containing halogen and carbon and having a carbon number of three or more per molecule, the processing gas is supplied such that a gas flow rate is greater in the peripheral portion than in the central portion.

Abstract: A method for fabricating an integrated circuit device. A plurality of MOS transistor devices are formed overlying a semiconductor substrate. Each of the MOS transistor devices includes a nitride cap and nitride sidewall spacers. An interlayer dielectric layer is formed overlying the plurality of MOS transistor devices. A portion of the interlayer dielectric material is removed to expose at least portions of three MOS transistor devices and expose at least three regions between respective MOS transistor devices. The method deposits polysilicon fill material overlying the exposed three regions and overlying the three MOS transistor devices. The method performs a chemical mechanical planarization process on the polysilicon material to reduce a thickness of the polysilicon material exposing a portion of the interlayer dielectric material until the cap nitride layer on each of the MOS transistors has been exposed using the cap nitride layer as a polish stop layer.

Abstract: A system for forming a feature includes forming a mask of a first material on an underlying layer, the mask having an incorrect profile. The profile of the mask is corrected and a feature is formed in the underlying layer. A method of forming a feature is also disclosed.

Abstract: A semiconductor device comprises a substrate, a first conductive film, a first insulation film, a second insulation film, a second conductive film, and a third conductive film. The first conductive film is formed on the substrate. The first insulation film is formed on the first conductive film and has a first opening. The first opening is formed as having multiple crossing trenches each having a predetermined width. The second insulation film is formed on the sides and bottom of the first opening. The second conductive film is formed on the second insulation film in the interior of the first opening. The third conductive film is formed on the second insulation film and the second conductive film.

Abstract: A method of treating a substrate comprises depositing silicon oxycarbide on the substrate and removing the silicon oxycarbide from the substrate. The silicon oxycarbide on the substrate is decarbonized by exposure to an energized oxygen-containing gas that heats the substrate and converts the layer of silicon oxycarbide into a layer of silicon oxide. The silicon oxide is removed by exposure to a plasma of fluorine-containing process gas. Alternatively, the remaining silicon oxide can be removed by a fluorine-containing acidic bath. In yet another version, a plasma of a fluorine-containing gas and an oxygen-containing gas is energized to remove the silicon oxycarbide from the substrate.

Abstract: Methods and apparatus for producing self-assembling quantum nanostructures by nanoheating a substrate with one or more laser interference patterns.

Abstract: A method of manufacturing a semiconductor device is disclosed. In the method of manufacturing the semiconductor device, a first insulating layer is formed on a semiconductor substrate. A metal line layer and an etch-stop layer are formed over the first insulating layer. The etch-stop layer and the metal line layer are patterned to form a metal line. A second insulating layer is formed on the first insulating layer and the etch-stop layer. A first etch process for etching part of the second insulating layer is performed by using a first etch gas so that the etch-stop layer is exposed. A second etch process for removing the etch-stop layer is performed by using a second etch gas so that the metal line is exposed.

Abstract: A gas for plasma reaction comprising a chainlike perfluoroalkyne having 5 or 6 carbon atoms, preferably perfluoro-2-pentyne. This plasma reaction gas is suitable for dry etching for formation of a fine pattern, for plasma CVD for formation of a thin film, and for plasma ashing. The plasma reaction gas is synthesized by contacting a dihydrofluoroalkane compound or a monohydrofluoroalkene compound with a basic compound.

Abstract: Disclosed are: (i) a method for forming an intermetal dielectric layer between metal wirings using a low-k dielectric material, and (ii) a semiconductor device with an intermetal dielectric layer comprising a low-k dielectric material. The method comprises the steps of: (a) forming a metal layer on a semiconductor substrate; (b) forming a plurality of metal wiring patterns by etching the metal layer selectively; (c) forming a first dielectric layer on the substrate and the plurality of metal wiring patterns; (d) forming a low-k dielectric layer on the first dielectric layer, the low-k dielectric layer having a lower dielectric constant than the first dielectric layer; and (e) forming a second dielectric layer on the low-k dielectric layer.

Abstract: A method for clearing native oxide is described. A substrate is provided, including an exposed portion whereon a native oxide layer has been formed. A clearing process is performed to the substrate using nitrogen trifluoride (NF3) and ammonia (NH3) as a reactant gas, wherein the volumetric flow rate of NF3 is greater than that of NH3.

Abstract: A method of forming a metal line in a semiconductor device including forming a first insulation layer and a first etch stop layer on a conductive layer, and forming a first photosensitive layer pattern on the first etch stop layer; forming a first opening by etching the first etch stop layer; forming a second insulation layer and a second etch stop layer on the first insulation layer and the first etch stop layer, and forming a second photosensitive layer pattern on the second etch stop layer; forming a second opening by etching the second etch stop layer; simultaneously forming an inter-connection groove and a via hole by etching the first insulation layer and the second insulation layer using the second etch stop layer and the first etch stop layer as a mask; and forming a metal line by filling the inter-connection groove and the via hole with conductive materials.

Abstract: Presented are methods of fabricating three-dimensional integrated circuits that include post-contact back end of line through-hole via integration for the three-dimensional integrated circuits. In one embodiment, the method comprises forming metal plug contacts through a hard mask and a premetal dielectric to transistors in the semiconductor. The method also includes etching a hole for a through-hole via through the hard mask to the semiconductor using a patterned photoresist process, removing the patterned photoresist and using a hard mask process to etch the hole to an amount into the semiconductor. The method further includes depositing a dielectric liner to isolate the hole from the semiconductor, depositing a gapfill metal to fill the hole, and planarizing the surface of the substrate to the hard mask. Another aspect of the present invention includes three-dimensional integrated circuits fabricated according to methods of the present invention.

Abstract: Methods are provided for etching during fabrication of a semiconductor device. The method includes initially etching to partially remove a portion of one or more lithographic-aiding layers overlying an oxide layer while etching a first portion of the oxide layer in accordance with a mask formed by the one or more lithographic-aiding layers, and thereafter additionally etching to remove remaining portions of the one or more lithographic-aiding layers while etching a remaining portion of the oxide layer.

Abstract: This invention provides a method for manufacturing a semiconductor silicon substrate by use of carbon dioxide in a supercritical state, which method is capable of making the semiconductor silicon substrate highly reliable one. Specifically, this invention provides a method for manufacturing a semiconductor silicon substrate including at least two of: a cleaning step of cleaning a substrate to be treated in a presence of carbon dioxide in a supercritical state; a film forming step of forming at least one of a conducting film, an insulating film and barrier film on the substrate to be treated in the presence of carbon dioxide in the supercritical state; an etching step of etching the substrate to be treated in the presence of carbon dioxide in the supercritical state; and a resist removing step of removing a resist on the substrate to be treated in the presence of carbon dioxide in the supercritical state.

Abstract: The voltage of a wafer on the pedestal of an RF plasma reactor is instantly determined from the applied bias current and the applied bias voltage sampled during plasma processing of the wafer using a pair constants. Prior to plasma processing of the wafer, a determination is made of first and second constants based upon electrical characteristics of a transmission line through which RF power is coupled to the pedestal. During plasma processing of the wafer, the wafer voltage is determined by performing the steps of sampling an RF input current and an RF input voltage at the impedance match circuit; multiplying the RF input voltage by the first constant to produce a first product; multiplying the RF input current by the second constant to produce a second product; and computing a sum of the first and second products.

Abstract: A semiconductor device structure is described, including a MOS transistor, a silicon-rich silicon nitride layer having a refractive index of about 2.00-2.30, and a dielectric layer. The silicon-rich silicon nitride layer is disposed between the MOS transistor and the dielectric layer, and covers the source/drain region, the spacer and the gate conductor of the MOS transistor.