Abstract: An etching method in accordance with the present disclosure includes providing a substrate, which includes a silicon-containing film, in a chamber; and etching the silicon-containing film with a chemical species in plasma generated from a process gas supplied in the chamber. The process gas includes a phosphorus gas component and a fluorine gas component.

Abstract: A semiconductor device is provided. The semiconductor device includes a dielectric layer over a substrate and a contact structure embedded in the dielectric layer. The contact structure includes a diffusion barrier contacting the dielectric layer, the diffusion barrier including a titanium (Ti)-containing alloy. The contact structure further includes a liner on the diffusion barrier, the liner including a noble metal. The contact structure further includes a conductive plug on the liner.

Abstract: An exemplary semiconductor fabrication stack includes underlying layers; an organic planarization layer atop the underlying layers; a metal oxide hardmask atop the organic planarization layer and doped with both carbon and nitrogen; and an organic photoresist directly atop the doped metal oxide hardmask. In one or more embodiments, the doped metal oxide hardmask exhibits a water contact angle of greater than 80°.

Abstract: Disclosed are embodiments of an improved apparatus and system, and associated methods for optically diagnosing a semiconductor manufacturing process. A hyperspectral imaging system is used to acquire spectrally-resolved images of emissions from the plasma, in a plasma processing system. Acquired hyperspectral images may be used to determine the chemical composition of the plasma and the plasma process endpoint. Alternatively, a hyperspectral imaging system is used to acquire spectrally-resolved images of a substrate before, during, or after processing, to determine properties of the substrate or layers and features formed on the substrate, including whether a process endpoint has been reached; or before or after processing, for inspecting the substrate condition.

Abstract: There is provided a technique capable of improving a uniformity of a substrate processing on a substrate surface. According to one aspect thereof, there is provided a substrate processing apparatus including: a substrate processing room; a plasma generation room; a gas supplier supplying a gas into the plasma generation room; a first coil surrounding the plasma generation room and to which an electric power is supplied; and a second coil surrounding the plasma generation room and to which an electric power is supplied. An axial direction of the second coil is equal to that of the first coil, a winding diameter of the second coil is different from that of the first coil, and a peak of a voltage distribution generated by supplying the electric power to the second coil does not overlap with a peak of a voltage distribution generated by the first coil.

Abstract: A method includes depositing a first dielectric layer covering an electrical connector, depositing a second dielectric layer over the first dielectric layer, and performing a first etching process to etch-through the second dielectric layer and the first dielectric layer. An opening is formed in the first dielectric layer and the second dielectric layer to reveal the electrical connector. A second etching process is performed to laterally etch the first dielectric layer and the second dielectric layer. An isolation layer is deposited to extend into the opening. The isolation layer has a vertical portion and a first horizontal portion in the opening, and a second horizontal portion overlapping the second dielectric layer. An anisotropic etching process is performed on the isolation layer, with the vertical portion of the isolation layer being left in the opening.

Abstract: A method for forming a semiconductor device. A substrate having a first region and a second region surrounding the first region is provided. The first region includes a first active area and a first gate. A dummy pattern is disposed on the substrate within the second region around a perimeter of the first region. A resist pattern masks the second region and includes an opening that exposes the first region. An ion implantation process is performed to implant dopants through the opening into the first active area not covered by the first gate within the first region, thereby forming doped regions in the first active area. A resist stripping process is performed to remove the resist pattern by using a sulfuric acid-hydrogen peroxide mixture (SPM) solution at a temperature that is higher than or equal to 120˜190 degrees Celsius. The substrate is subjected to a cleaning process.

Abstract: A substrate processing method includes a providing step, a forming step, and an etching step. In the providing step, a substrate including an etching target film, a first mask formed on the etching target film, and a second mask formed to cover at least a part of the first mask is provided. In the forming step, a protective film is formed on a side wall of the second mask by plasma generated from a first gas. In the etching step, the etching target film is etched with plasma generated from a second gas.

Abstract: The memory bit-cell formed using the ferroelectric capacitor results in a taller and narrower bit-cell compared to traditional memory bit-cells. As such, more bit-cells can be packed in a die resulting in a higher density memory that can operate at lower voltages than traditional memories while providing the much sought after non-volatility behavior. The pillar capacitor includes a plug that assists in fabricating a narrow pillar.

Abstract: An array antenna radiates an electromagnetic wave into a chamber of a plasma processing apparatus. The array antenna includes antennas and coupling prevention elements arranged at intervals between the antennas. Each of the coupling prevention elements includes a first member connected to a ceiling wall which is a ground surface in the chamber and a second member connected to a tip end of the first member or a vicinity of the tip end of the first member.

Abstract: A semiconductor device includes a first metal wiring layer, an interlayer insulating layer formed over the first metal layer, a second metal wiring structure embedded in the interlayer dielectric layer and connected to the first metal wiring layer, and an etch-stop layer disposed between the first metal wiring and the first interlayer dielectric layer. The etch-stop layer includes one or more sub-layers. The etch-stop layer includes a first sub-layer made of an aluminum-based insulating material, hafnium oxide, zirconium oxide or titanium oxide.

Abstract: When a plasma processing apparatus changes processing parameters of a plasma processing that include at least a temperature of a stage and a temperature of each zone obtained by dividing a placing surface of the stage into multiple patterns, and measures the temperature of each zone and a supply current to a hater in a state where the temperature is stabilized, an acquisition unit acquires the measurement data. The generator generates a prediction model using the measurement data, assuming that heat with heat quantity proportional to a temperature difference between adjacent zones moves therebetween, heat with heat quantity proportional to a temperature difference between the stage and each zone moves therebetween, heat with heat quantity calculated from the supply current to the heater of each zone is input to the zone, and quantity of heat input and quantity of heat output in each zone are consistent.

Abstract: A bilayer hardmask is formed on layers, the bilayer hardmask including a first hardmask layer and a second hardmask layer on the first hardmask layer. A first pattern is formed in the second hardmask layer, the first pattern including tapered sidewalls forming a first spacing in the second hardmask layer. A second pattern is formed in the first hardmask layer based on the first pattern, the second pattern comprising vertical sidewalls forming a second spacing in the first hardmask layer, the second spacing being reduced in size from the first spacing.

Abstract: Embodiments of the invention describe low capacitance interconnect structures for semiconductor devices and methods for manufacturing such devices. According to an embodiment of the invention, a low capacitance interconnect structure comprises an interlayer dielectric (ILD). First and second interconnect lines are disposed in the ILD in an alternating pattern. The top surfaces of the first interconnect lines may be recessed below the top surfaces of the second interconnect lines. Increases in the recess of the first interconnect lines decreases the line-to-line capacitance between neighboring interconnects. Further embodiments include utilizing different dielectric materials as etching caps above the first and second interconnect lines. The different materials may have a high selectivity over each other during an etching process. Accordingly, the alignment budget for contacts to individual interconnect lines is increased.

Abstract: A plasma treatment method is provided. The method includes generating a planar plasma in a plasma treatment chamber, observing an effective influence region of the planar plasma by using an optical observation system in which an observation lens has a transparent substrate and a fluorescent coating thereon, adjusting a location of the observation lens to observe a brightness change of the fluorescent coating and the transparent substrate to obtain a location and a thickness range of the effective influence region of the planar plasma, and then adjusting a location of the observation lens to observe a brightness change of the fluorescent coating and the transparent substrate to obtain a location and a thickness range of the effective influence region of the planar plasma. A location of a sample is adjusted to within the effective influence region, and a plasma treatment is then performed on the sample.

Abstract: A semiconductor structure is provided that includes non-metal semiconductor alloy containing contact structures for field effect transistors (FETs), particularly p-type FETs. Notably, each non-metal semiconductor alloy containing contact structure includes a highly doped epitaxial semiconductor material directly contacting a topmost surface of a source/drain region of the FET, a titanium liner located on the highly doped epitaxial semiconductor material, a diffusion barrier liner located on the titanium liner, and a contact metal portion located on the diffusion barrier liner.

Abstract: A method of fabricating a semiconductor device includes providing a substrate, and forming an interlayered insulating layer on the substrate. The method includes forming a preliminary via hole in the interlayered insulating layer. The method includes forming a passivation spacer on an inner side surface of the preliminary via hole. The method includes forming a via hole using the passivation spacer as an etch mask. The method includes forming a conductive via in the via hole. The passivation spacer includes an insulating material different from an insulating material included in the interlayered insulating layer.

Abstract: A method of manufacturing a semiconductor device includes etching a via through a dielectric layer and an etch stop layer (ESL) to a source/drain contact, forming a recess in the top surface of the source/drain contact such that the top surface of the source/drain contact is concave, and forming an oxide liner on the sidewalls of the via. The oxide liner traps impurities left behind by the etching of the via through the dielectric layer and the ESL, wherein the etching, the forming the recess, and the forming the oxide liner are performed in a first chamber. The method further includes performing a pre-cleaning that removes the oxide liner and depositing a metal in the via.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate, a gate, and a phosphorus containing dielectric layer. The gate is on the substrate. The phosphorus containing dielectric layer is on the gate. The phosphorus containing dielectric layer has a varied phosphorus dopant density distribution profile.

Abstract: A method of making a device includes forming an opening in a dielectric layer to expose a conductive region in a substrate. The method further includes depositing a conformal layer of dopant material along sidewalls of the opening and along a top surface of the dielectric layer. The method further includes diffusing the dopant from the conformal layer of dopant material into the dielectric layer using an anneal process.

Abstract: Integrated chips and methods of forming the same include forming lines of alternating first and second sacrificial fills in a film. A dielectric cut is formed in at least one of the first sacrificial fills. A dielectric cut is formed in at least one of the second sacrificial fills. Remaining first and second sacrificial fill material is replaced with a conductive material. The film is replaced with a final dielectric material.

Abstract: Provided is a plasma etching method comprising supplying both hexafluoroisopropanol (HFIP) gas and argon (Ar) gas to a plasma chamber receiving an etching target therein, thereby to plasma-etch the etching target.

Abstract: A method of increasing the surface area of a contact to an electrical device that in one embodiment includes forming a contact stud extending through an intralevel dielectric layer to a component of the electrical device, and selectively forming a contact region on the contact stud. The selectively formed contact region has an exterior surface defined by a curvature and has a surface area that is greater than a surface area of the contact stud. An interlevel dielectric layer is formed on the intralevel dielectric layer, wherein an interlevel contact extends through the interlevel dielectric layer into direct contact with the selectively formed contact region.

Abstract: A plasma processing apparatus includes a processing chamber, a substrate disposed in the processing chamber, and a plurality of electron sources configured to supply electrons to a plasma generated in the processing chamber. Each of the plurality of electron sources includes a first side facing the plasma in the processing chamber. Each of the plurality of electron sources also includes a resonant structure disposed at the first side and configured to be held at a negative direct current bias voltage.

Abstract: A method for making a semiconductor device is disclosed. A substrate comprising semiconductor device elements is provided. A top conductive pad and an anti-reflective coating are patterned over the substrate. The anti-reflective coating is disposed on the top conductive pad. At least one passivation film is formed over the substrate and the anti-reflective coating. The at least one passivation film and the anti-reflective coating are etched to form a trench therein so as to expose a portion of the top conductive pad.

Abstract: A method of fabricating an array substrate, an array substrate, a display panel, and a display device are provided. In an embodiment, a gate insulating layer above a channel region is doped with fluorine atoms. Since a fluorine-containing inorganic layer can absorb hydrogen atoms, it can block hydrogen atoms from diffusing downward into a metal oxide semiconductor, thereby avoiding affecting electrical properties of thin film transistors. Simultaneously, only a metal is required to use as a metal gate layer, which simplifies process and reduces production costs.

Abstract: A spacer structure and a fabrication method thereof are provided. First and second conductive structures are formed over a substrate. A first patterned dielectric layer is formed to cover the first conductive structure and exposing the second conductive structure. A second dielectric layer is formed to cover the first patterned dielectric layer and an upper surface and sidewalls of the second conductive structure. The second dielectric layer disposed over an upper surface of the first conductive structure and the upper surface of the second conductive structure is removed. The first patterned dielectric layer and the second dielectric layer disposed on sidewalls of the first conductive structure form a first spacer structure, and the second dielectric layer disposed on the sidewalls of the second conductive structure forms a second spacer structure. A width of the first spacer structure is larger than a width of the second spacer structure.

Abstract: An imprint apparatus that forms a pattern on a substrate by using a mold, the apparatus comprises a supply unit configured to supply an imprint material to the substrate; a contact unit configured to contact the imprint material that has been supplied to the substrate with a mold; a substrate stage configured to move the substrate; a gas supply unit that is provided between the supply unit and the contact unit, and supply gas toward the substrate; and a flow volume adjustment unit configured to adjust a flow volume of the gas that is supplied from the gas supply unit, while the substrate stage moves the substrate from a supply position at which the imprint material is supplied by the supply unit to a contact position at which the imprint material is contacted with the mold by the contact unit.

Abstract: A semiconductor structure includes a substrate, a first gate structure, a first spacer, a source/drain structure, a conductor, and a contact etch stop layer. The first gate structure is present on the substrate. The first spacer is present on at least one sidewall of the first gate structure, in which the first spacer has a top portion and a bottom portion between the top portion and the substrate. The source/drain structure is present adjacent to the bottom portion of the first spacer. The conductor is electrically connected to the source/drain structure. The protection layer is present at least between the conductor and the top portion of the first spacer. The contact etch stop layer is present at least partially between the conductor and the bottom portion of the first spacer while absent between the protection layer and the top portion of the first spacer.

Abstract: A method includes forming a first hard mask layer and a second hard mask layer over the first hard mask layer, and forming a tri-layer including a bottom layer, a middle layer, and a patterned upper layer. The method further includes etching the middle layer to extend an opening in the patterned upper layer into the middle layer, wherein the opening has a first portion in the middle layer, and the first portion has a first top width and a first bottom width smaller than the first top width; etching the bottom layer to extend the opening into the bottom layer; and etching the second hard mask layer to extend the opening into the second hard mask layer. The opening has a second portion in the second hard mask layer, and the second portion has a second top width and a second bottom width smaller than the second top width.

Abstract: A method includes depositing a hardmask layer over a magnetoresistive (MR) structural layer formed on a substrate, the hardmask layer being formed from tungsten or a tungsten-based composition. A photoresist layer is deposited over the hardmask layer and is patterned to expose a first portion of the hardmask layer. A first etch process is performed to remove the first portion of the hardmask layer and expose a second portion of the MR structural layer and a dry etch process is performed to remove the second portion of the MR structural layer and produce an MR sensor structure. Following the dry etch process, a composite structure remains that includes the MR sensor structure and a hardmask section of the hardmask layer, the hardmask section overlying the MR sensor structure. A spacer formed from a protective, dielectric material layer may additionally be formed surrounding the composite structure.

Abstract: The surface layer of a semiconductor wafer lying on a rotatable plate within an etching chamber is etched by a process whereby homogeneous etching of the surface is obtained by introducing an etching gas into the etching chamber in such a way that the flow of the etching gas is not directed directly to the wafer but is allowed first to distribute within the etching chamber before coming into contact with the surface of the semiconductor wafer to be etched.

Abstract: A substrate processing technique is described herein for etching layers, such as dielectric layers, and more particularly low k dielectric layers in a manner that minimizes etch lag effects. Multiple etch processes are utilized. A first etch process may exhibit etch lag. A second etch process is a multi-step process that may include a deposition sub-step, a purge sub-step and an etch sub-step. The second etch process may exhibit inverse etch lag. The second etch process may be a cyclic process which performs the deposition, purge and etch sub-steps a plurality of times. The second etch process may be an atomic layer etch based process, and more particularly a quasi-atomic layer etch. The combination of the first etch process and the second etch process may provide the desired net effect for the overall etch lag when etching the dielectric layer.

Abstract: Certain embodiments provide a method for manufacturing a semiconductor device including forming a first interconnection layer having a first conductive layer and a first insulating layer which are exposed from a surface of the first interconnection layer, forming a second interconnection layer having a second conductive layer and a second insulating layer which are exposed from a surface of the second interconnection layer, forming a first non-bonded surface on the surface of the first insulating layer by making a partial area of the surface of the first insulating layer lower than the surface of the first conductive layer, the partial area containing surroundings of the first conductive layer, and connecting the surface of the first conductive layer and the surface of the second conductive layer and bonding the surface of the first insulating layer excluding the first non-bonded surface and the surface of the second insulating layer.

Abstract: A method for fabricating a semiconductor device includes the steps of: providing a first dielectric layer having a metal layer therein; forming a second dielectric layer on the first dielectric layer and the metal layer; forming a metal oxide layer on the second dielectric layer; performing a first etching process by using a chlorine-based etchant to remove part of the metal oxide layer to forma via opening and expose the second dielectric layer; forming a block layer on sidewalls of the metal oxide layer and a top surface of the second dielectric layer; and performing a second etching process by using a fluorine-based etchant to remove part of the block layer and part of the second dielectric layer for exposing a top surface of the metal layer.

Abstract: A plasma processing device includes a chamber; a substrate stage that supports a substrate inside the chamber; a plasma generator that generates plasma by which the substrate is processed in a space above the substrate inside the chamber; and an electromagnet. The electromagnet is provided in each of a plurality of regions, which are provided on a top of the chamber in an upper part thereof, so as to be independently movable. The plasma processing device further includes a controller configured to move the electromagnet to produce a uniform plasma density onto the substrate.

Abstract: The present invention disclosed herein relates to a substrate treating apparatus, and more particularly, to an apparatus for treating a substrate using plasma. Embodiments of the present invention provide substrate treating apparatuses including a chamber having a treating space defined therein, a support member disposed in the chamber to support a substrate, a gas supply unit supplying a gas into the chamber, a plasma source generating plasma from the gas supplied into the chamber, a baffle disposed to surround the support member in the chamber and having through holes to exhaust a gas in the treating space, and a shielding unit preventing an electromagnetic field from an inside of the chamber to an outside of the chamber.

Abstract: A plasma monitoring apparatus includes a reflective structure disposed on a processing chamber providing a space in which plasma for processing a substrate is formed, the reflective structure configured to receive fragments of light incident in a plurality of incident directions from the plasma, and output the fragments of light in a plurality of exit directions by reflecting the fragments of light within the reflective structure; at least one light sensor configured to receive the fragments of light passing through the reflective structure in the plurality of exit directions; and at least one optical spectrometer connected to the at least one light sensor.

Abstract: Apparatus, systems, and methods for determining a temperature excursion are provided. In one example, a system can comprise a temperature switch component that experiences a temperature excursion associated with a metal alloy of the temperature switch component and one or more electrodes, wherein the temperature excursion is based on a temperature of the metal alloy exceeding a defined threshold value. Additionally, the system can comprise a radio frequency identification tag component that receives a signal, from an external reader device, utilized to determine that the temperature excursion has occurred based on a parameter change, associated with the temperature excursion, from a first parameter to a second parameter different than the first parameter.

Abstract: A semiconductor device includes a semiconductor substrate, an element region including an active element formed at the semiconductor substrate, a channel stopper formed in an outer peripheral region of the semiconductor substrate, and an insulating film that covers a surface of the semiconductor substrate and that has a first contact hole by which the channel stopper is exposed. The semiconductor device further includes a first field plate, a second field plate, and an equipotential ring electrode. The first field plate is formed on the insulating film, and faces the semiconductor substrate between the channel stopper and the element region through the insulating film. The second field plate is embedded in the insulating film, and faces the semiconductor substrate between the first field plate and the channel stopper through the insulating film. The equipotential ring electrode is formed along an outer peripheral region of the semiconductor substrate.

Abstract: The present invention provides a method for fabricating a semiconductor structure. A multilayer structure on is formed a substrate, the multilayer structure includes at least a first dielectric layer, a second dielectric layer and an amorphous silicon layer, next, a first etching step is performed, to forma first recess in the amorphous silicon layer and in the second dielectric layer, parts of the first dielectric layer is exposed by the first recess, afterwards, a hard mask layer is formed in the first recess, a second etching step is then performed to remove the hard mask layer and to expose a surface of the first dielectric layer, and a third etching step is performed with the remaining hard mask layer, to remove a portion of the first dielectric layer, so as to form a second recess in the first dielectric layer.

Abstract: A method of manufacturing a semiconductor device is provided. The method comprises forming a first insulator above the substrate, forming a second insulator on the first insulator, performing a first etching process of etching the second insulator by fluorine and hydrogen contained gas to expose the first insulator while leaving a portion of the second insulator which covers a side face of the gate electrode and performing a second etching process of etching a portion of the first insulator exposed by the first etching process. The first etching process includes a first process and a second process performed after the first process. A reaction product is less deposited in the first process than in the second process and etching selectivity of the second insulator with respect to the first insulator is higher in the second process than in the first process.

Abstract: A method of increasing the surface area of a contact to an electrical device that in one embodiment includes forming a contact stud extending through an intralevel dielectric layer to a component of the electrical device, and selectively forming a contact region on the contact stud. The selectively formed contact region has an exterior surface defined by a curvature and has a surface area that is greater than a surface area of the contact stud. An interlevel dielectric layer is formed on the intralevel dielectric layer, wherein an interlevel contact extends through the interlevel dielectric layer into direct contact with the selectively formed contact region.

Abstract: The present invention discloses a semiconductor structure with capacitor landing pad and a method for fabricating a capacitor landing pad. The semiconductor structure with capacitor landing pad includes a substrate having a plurality of contact structures, a first dielectric layer disposed on the substrate and the contact structures, and a plurality of capacitor landing pads, each of the capacitor landing pads being located in the first dielectric layer and electrically connected to the contact structure, wherein the capacitor landing pads presents a shape of a wide top and a narrow bottom and a top surface of the capacitor landing pads have a concave shape.

Abstract: Embodiments describe the selective electroless plating of dielectric layers. According to an embodiment, a dielectric layer is patterned to form one or more patterned surfaces. A seed layer is then selectively formed along the patterned surfaces of the dielectric layer. An electroless plating process is used to deposit metal only on the patterned surfaces of the dielectric layer. According to an embodiment, the dielectric layer is doped with an activator precursor. Laser assisted local activation is performed on the patterned surfaces of the dielectric layer in order to selectively form a seed layer only on the patterned surfaces of the dielectric layer by reducing the activator precursor to an oxidation state of zero. According to an additional embodiment, a seed layer is selectively formed on the patterned surfaces of the dielectric layer with a colloidal or ionic seeding solution.

Abstract: The invention discloses cleaning compositions which employ a synergistic combination of a ester solvent, preferably a fatty acid methyl ester in combination with one or more linear alkyl amines. The alkyl amines act as to remove and suspend organic oils which have been burnt or adhered to a surface with heat and may even be used alone as a soil removal agent. The cleaning compositions have particular use in cleaning of distillation towers associated with biofuel, and vegetable oil refining, but also find use in cleaning ovens, food cooking surfaces and even dry cleaning.

Abstract: A storage device includes a first electrode, a stacked feature, a spacer and a barrier structure. The stacked feature is position over the first electrode, and includes a storage element and a second electrode over the storage element. The spacer is positioned on a sidewall of the stacked feature, the spacer having a notch positioned on a top surface of the spacer, in which the notch of the spacer has a surface which is continuous with a top surface of the stacked feature. The barrier structure is embedded in a lateral of the spacer. The barrier structure has a top extending upwards past a bottom of the notch.

Abstract: A method of etching a substrate is described. The method includes disposing a substrate having a surface exposing a first material and a second material in a processing space of a plasma processing system, and performing a modulated plasma etching process to selectively remove the first material at a rate greater than removing the second material. The modulated plasma etching process comprises a power modulation cycle having sequential power application steps that includes: applying a radio frequency (RF) signal to the plasma processing system at a first power level, applying the RF signal to the plasma processing system at a second power level, and applying the RF signal to the plasma processing system at a third power level. Thereafter, the power modulation cycle is repeated at least one more cycle, wherein each modulation cycle includes a modulation time period.

Abstract: The present invention provides an array substrate, a manufacturing method thereof and a display panel. The array substrate includes a substrate and an insulation layer provided on the substrate, the insulation layer including a via therein formed by etching. The insulation layer further includes a plurality of insulation sub-layers stacked on each other, and an insulation sub-layer among the plurality of insulation sub-layers which is farther away from the substrate has a larger etching rate under an etching condition for forming the via.

Abstract: A method of manufacturing a redistribution circuit structure and a method of manufacturing an INFO package at least include the following steps. An inter-dielectric layer is formed over a substrate. A seed layer is formed over the inter-dielectric layer. A plurality of conductive patterns are formed over the seed layer. The seed layer and the conductive patterns include a same material. While maintain a substantially uniform pitch width in the conductive pattern, the seed layer exposed by the conductive patterns is selectively removed through a dry etch process to form a plurality of seed layer patterns. The conductive patterns and the seed layer patterns form a plurality of redistribution conductive patterns.