Abstract: An LED (20) includes a base (24), a chip (21) and an encapsulation (22) made of a transparent material. The base has a concave depression (240). The chip is mounted on a bottom of the concave depression. The first encapsulation is received in the depression for sealing the chip. The chip includes a light emitting surface (210). The encapsulation includes a light output surface (25) over the light emitting surface. The light output surface defines a plurality of recesses (26). A mixture (29) formed by mixing another transparent material (27) and fluorescent powder (28) is filled in each of the recesses.

Abstract: A transistor is fabricated upon a semiconductor substrate, where the yield strength or elasticity of the substrate is enhanced or otherwise adapted. A strain inducing layer is formed over the transistor to apply a strain thereto to alter transistor operating characteristics, and more particularly to enhance the mobility of carriers within the transistor. Enhancing carrier mobility allows transistor dimensions to be reduced while also allowing the transistor to operate as desired. However, high strain and temperature associated with fabricating the transistor result in deleterious plastic deformation. The yield strength of the silicon substrate is therefore adapted by incorporating nitrogen into the substrate, and more particularly into source/drain extension regions and/or source/drain regions of the transistor. The nitrogen can be readily incorporated during transistor fabrication by adding it as part of source/drain extension region formation and/or source/drain region formation.

Abstract: A process for forming an interconnect structure in a low-k dielectric layer includes etching to form trenches in the dielectric layer, removal of photoresist, and further etching to remove damaged portions of the dielectric layer in sidewalls of the trenches. An interconnect structure includes a low-k dielectric layer formed on a substrate, and a conductor embedded in the dielectric layer, the conductor having an edge portion with an inwardly rounded shape.

Abstract: A semiconductor device comprises a substrate, a first conductive film, a first insulation film, a second insulation film, a second conductive film, and a third conductive film. The first conductive film is formed on the substrate. The first insulation film is formed on the first conductive film and has a first opening. The first opening is formed as having multiple crossing trenches each having a predetermined width. The second insulation film is formed on the sides and bottom of the first opening. The second conductive film is formed on the second insulation film in the interior of the first opening. The third conductive film is formed on the second insulation film and the second conductive film.

Abstract: A method and deposition system for increasing deposition rates of metal layers from metal-carbonyl precursors using CO gas and a dilution gas. The method includes providing a substrate in a process chamber of a processing system, forming a process gas containing a metal-carbonyl precursor vapor and a CO gas, diluting the process gas in the process chamber, and exposing the substrate to the diluted process gas to deposit a metal layer on the substrate by a thermal chemical vapor deposition process.

Abstract: One or more embodiments relate to a method of making a heterojunction bipolar transistor (HBT) structure. The method includes: forming a partially completed heterojunction bipolar transistor (HBT) structure where the partially completed heterojunction bipolar transistor (HBT) structure includes a silicon layer having an exposed surface and a nitride layer having an exposed surface. The method includes growing a first oxide on the silicon layer and etching the nitride layer using an etchant.

Abstract: A method of forming an integrated circuit structure, the method includes providing a semiconductor substrate; forming a dielectric layer over the semiconductor substrate; forming an opening in the dielectric layer; forming a seed layer in the opening; forming a copper line on the seed layer, wherein at least one of the seed layer and the copper line includes an alloying material; and forming an etch stop layer on the copper line.

Abstract: A method of pre-treating a mask layer prior to etching an underlying thin film is described. A thin film, such as a dielectric film, is etched using plasma that is enhanced with a ballistic electron beam. In order to reduce the loss of pattern definition, such as line edge roughness effects, the mask layer is treated with an oxygen-containing plasma or halogen-containing plasma or a noble gas plasma or a combination of two or more thereof prior to proceeding with the etching process.

Abstract: A method for fabricating dual material gate structures in a device is provided. The dual material gate structures have different gate electrode materials in different regions of the device. In one embodiment, the method includes providing a substrate having a patterned first gate electrode and a patterned first gate dielectric layer disposed on the substrate, removing a portion of the first gate electrode from the substrate to define a trench on the substrate, and filling the trench to form a second gate electrode.

Abstract: In order to achieve low cost of manufacture of a display device by reducing the use of primary material used in a manufacturing process of a display device and saving labor taken for a vacuum process, according to the invention, liquid droplets containing conductive particles are ejected on a film being processed by using a first liquid droplet ejecting apparatus having a liquid droplet ejecting head provided with a plurality of liquid droplet ejecting orifices, thereby a conductive film is formed. After that, a resist pattern is locally formed on the conductive film by using a second liquid droplet ejecting apparatus having a liquid droplet ejecting head provided with a plurality of liquid droplet ejecting orifices. The conductive film is etched with the resist pattern as a mask to form a wiring.

Abstract: A first aspect of the invention provides a method of selectively forming an epitaxial layer on a substrate. The method includes heating the substrate to a temperature of less than about 800° C. and employing both silane and dichlorosilane as silicon sources during epitaxial film formation. Numerous other aspects are provided.

Abstract: The present invention pertains to methods for removing unwanted material from a semiconductor wafer during wafer manufacturing. More specifically, the invention pertains to stripping photo-resist material and removing etch-related residues from a semiconductor wafer. Methods involve implementing a plasma operation using hydrogen and a weak oxidizing agent, such as carbon dioxide. The invention is effective at stripping photo-resist and removing residues from low-k dielectric material used in Damascene devices.

Abstract: A method of fabricating a ferroelectric device includes forming a ferroelectric layer on a substrate in a reaction chamber. An inactive gas is provided into the reaction chamber while unloading the substrate therefrom to thereby substantially inhibit formation of an impurity layer on the ferroelectric layer.

Abstract: Embodiments relate to a method for forming a wiring in a semiconductor device, that may include laminating a conductive layer for wiring formation on a semiconductor substrate, forming a photoresist layer pattern on the conductive layer, performing primary dry etching for the conductive layer after employing the photoresist layer pattern as a mask, thereby forming a wiring pattern, partially removing the photoresist layer pattern through secondary dry etching, thereby forming a passivation layer on a surface of the wiring pattern, performing tertiary dry etching for the wiring pattern and a diffusion barrier after employing the photoresist layer pattern as a mask, thereby forming a metal wiring, and removing the photoresist layer pattern.

Abstract: Defects and fixed charge in a gate dielectric near the gate dielectric-substrate interface are reduced by performing a gate dielectric relaxation anneal step prior to source-drain ion implantation, in which the wafer temperature is ramped gradually to near a melting temperature of the substrate equal to a peak post-ion implantation anneal peak temperature. The ramping rates are sufficiently gradual so that the gate dielectric is held above its reflow temperature for a significant duration.

Abstract: Methods and devices for selective etching in a semiconductor process are shown. Chemical species generated in a reaction chamber provide both a selective etching function and concurrently form a protective coating on other regions. An electron beam provides activation to selective chemical species. In one example, reactive species are generated from a plasma source to provide an increased reactive species density. Addition of other gasses to the system can provide functions such as controlling a chemistry in a protective layer during a processing operation.

Abstract: Methods of forming capping structures on one or more different material surfaces are provided. One embodiment includes disposing a semiconductor structure in a reduced pressure chamber, forming a capping GCIB within the reduced pressure chamber, and directing the capping GCIB onto at least one of the one or more different material surfaces, so as to form at least one capping structure on the one or more surfaces onto which the capping GCIB is directed.

Abstract: A method for increasing the removal rate of a photoresist layer used as an ion implant mask. The method includes performing a pre-treatment of a substrate, such as a plasma process, before forming the photoresist layer. The method can be applied to the fabrication of semiconductor devices for increasing the removal rate of the photoresist layer.

Abstract: Means and methods for producing surface-activated semiconductor nanoparticles suitable for in vitro and in vivo applications that can fluoresce in response to light excitation. Semiconductor nanostructures can be produced by generating a porous layer in semiconductor substrate comprising a network of nanostructures. Prior or subsequent to cleavage from the substrate, the nanostructures can be activated by an activation means such as exposing their surfaces to a plasma, oxidation or ion implantation. In some embodiments, the surface activation renders the nanostructures more hydrophilic, thereby facilitating functionalization of the nanoparticles for either in vitro or in vivo use.

Abstract: An object of the present invention is to prevent an increase in film thickness and inhibit a reduction in capacity of a capacitor. In a semiconductor device having a capacitor, the capacitor includes a lower electrode, an upper electrode, and an insulating film interposed between the lower electrode and the upper electrode. A surface of the lower electrode on an insulating layer side is nitrided. If the lower electrode is made of polysilicon, nitriding the surface thereof increases oxidation resistance at the time of heat treatment in a post process. Particularly in a DRAM, the capacity of the capacitor is large, and therefore, this effect is significant. Further, leakage current inside the capacitor is also reduced.

Abstract: A method of plasma doping includes generating a plasma comprising dopant ions proximate to a platen supporting a substrate in a plasma chamber. The platen is biased with a bias voltage waveform having a negative potential that attracts ions in the plasma to the substrate for plasma doping. At least one sensor measuring data related to charging conditions favorable for forming an electrical discharge is monitored. At least one plasma process parameter is modified in response to the measured data, thereby reducing a probability of forming an electrical discharge.

Abstract: There is provided a method for manufacturing a semiconductor device including processing a substrate to be processed by using an amorphous carbon hard mask that includes processing an amorphous carbon film formed on the substrate to be processed to provide a hard mask, and forming a protective film comprising a silicon oxide film on a sidewall of the amorphous carbon film exposed during or after processing the amorphous carbon film; and the protective film preferably formed by sputtering an intermediate mask comprising at least a silicon oxide on the amorphous carbon film.

Abstract: A method includes providing a glass substrate and bonding a semiconductor layer to the glass substrate. The semiconductor layer is formed to a thickness such that it does not yield due to temperature-induced strain at device processing temperatures.

Abstract: Methods of depositing a dielectric layer in a gap formed on a substrate are described. The methods include introducing an organo-silicon precursor and an oxygen precursor to a deposition chamber. The organo-silicon precursor has a C:Si atom ratio of less than 8, and the oxygen precursor comprises atomic oxygen that is generated outside the deposition chamber. The precursors are reacted to form the dielectric layer in the gap. Methods of filling gaps with dielectric materials are also described. These methods include providing an organo-silicon precursor having a C:Si atom ratio of less than 8 and an oxygen precursor, and generating a plasma from the precursors to deposit a first portion of the dielectric material in the gap. The dielectric material may be etched, and a second portion of dielectric material may be formed in the gap. The first and second portions of the dielectric material may be annealed.

Abstract: In a method for using a film formation apparatus for a semiconductor process, process conditions of a film formation process are determined. The process conditions include a preset film thickness of a thin film to be formed on a target substrate. Further, a timing of performing a cleaning process is determined in accordance with the process conditions. The timing is defined by a threshold concerning a cumulative film thickness of the thin film. The cumulative film thickness does not exceed the threshold where the film formation process is repeated N times (N is a positive integer), but exceeds the threshold where the film formation process is repeated N+1 times. The method includes continuously performing first to Nth processes, each consisting of the film formation process, and performing the cleaning process after the Nth process and before an (N+1)th process consisting of the film formation process.

Abstract: A method of making an interconnect that includes providing an interconnect structure in a dielectric material, recessing the dielectric material such that a portion of the interconnect structure extends above an upper surface of the dielectric; and depositing an encasing cap over the extended portion of the interconnect structure.

Abstract: A method of fabricating a floating gate of a flash memory device is provided. The method includes: forming a tunneling oxide layer on a substrate; forming a conductive thin layer on the tunneling oxide layer; applying a photoresist on the conductive thin layer; defining a floating gate region by patterning the photoresist; forming polymer sidewalls on the sides of the patterned photoresist; and selectively removing the conductive thin layer using the photoresist and the polymer sidewalls as a mask to form a floating gate.

Abstract: A method for processing a substrate in a plasma processing chamber is provided. The substrate is disposed above a chuck and surrounded by a first edge ring. The first edge ring is electrically isolated from the chuck. The method includes providing a second edge ring. The second edge ring is disposed below an edge of the substrate. The method also includes providing a coupling ring. The coupling ring is configured to facilitate RF coupling from an ESC (electrostatic chuck) assembly to the first edge ring, thereby causing the first edge ring to have an edge ring potential during substrate processing and causing the RF coupling to be maximized at the first edge ring and minimized at the second edge ring during the substrate processing.

Abstract: Methods of forming interconnect structures include forming a first metal wiring pattern on a first dielectric layer and forming a capping layer (e.g., SiCN layer) on the first copper wiring pattern. An adhesion layer is deposited on the capping layer, using a first source gas containing octamethylcyclotetrasilane (OMCTS) at a volumetric flow rate in a range from about 500 sccm to about 700 sccm and a second gas containing helium at a volumetric flow rate in a range from about 1000 to about 3000 sccm. The goal of the deposition step is to achieve an adhesion layer having an internal compressive stress of greater than about 150 MPa therein, so that the adhesion layer is less susceptible to etching/cleaning damage and moisture absorption during back-end processing steps. Additional dielectric and metal layers are then deposited on the adhesion layer.

Abstract: The present invention provides a method for manufacturing a semiconductor device having multiple gate dielectric thickness layers. The method, in one embodiment, includes forming a first layer of gate dielectric material over a semiconductor substrate in a first active region and a second active region of a semiconductor device, and patterning a masking layer to expose the first layer of gate dielectric material located in the first active region.

Abstract: A dry etching method for forming tungsten wiring having a tapered shape and having a large specific selectivity with respect to a base film is provided. If the bias power density is suitably regulated, and if desired portions of a tungsten thin film are removed using an etching gas having fluorine as its main constituent, then the tungsten wiring having a desired taper angle can be formed.

Abstract: A method of forming a dielectric layer includes providing a substrate that has a copper region and a non-copper region. The substrate is etched to remove any copper oxides from the copper region. A dielectric cap is then selectively formed over the copper region of the substrate so that little or no dielectric cap is formed over the non-copper region of the substrate.

Abstract: A method of forming a pre-patterned high-k dielectric film onto a support layer. The method includes: providing a support layer; providing a template defining template openings therein exhibiting a pattern that is a mirror image of a pattern of the pre-patterned high-k dielectric film; disposing the template onto the support layer; providing a high-k precursor material inside the template openings; curing the high-k precursor material inside the template openings to yield a cured film; and removing the template from the support layer after curing to leave the cured film on the conductive film.

Abstract: A method of integrated processing of a patterned substrate for copper metallization. The method includes providing the patterned substrate containing a via and a trench in a vacuum processing tool, and performing an integrated process on the patterned substrate in the vacuum processing tool by depositing a first metal-containing layer over the patterned substrate, removing by sputter etching the first metal-containing layer from the bottom of the via and at least partially removing the first metal-containing layer from the bottom of the trench, depositing a conformal Ru layer onto the sputter etched first metal-containing layer, depositing a non-conformal Cu layer on the conformal Ru layer, and plating Cu over the patterned substrate. According to one embodiment of the invention, the method can further include depositing a second metal-containing layer onto the sputter etched first metal-containing layer prior to depositing the conformal Ru layer.

Abstract: A method for making a film stack containing one or more metal-containing layers and a substrate processing system for forming the film stack on a substrate are provided. The substrate processing system includes at least one transfer chamber coupled to at least one load lock chamber, at least one first physical vapor deposition (PVD) chamber configured to deposit a first material layer on a substrate, and at least one second PVD chamber for in-situ deposition of a second material layer over the first material layer within the same substrate processing system without breaking the vacuum or taking the substrate out of the substrate processing system to prevent surface contamination, oxidation, etc. The substrate processing system is configured to provide high throughput and compact footprint for in-situ sputtering of different material layers in designated PVD chambers.

Abstract: In a method of achieving uniform lengths of Carbon NanoTubes (CNTs) and a method of manufacturing a Field Emission Device (FED) using such CNTs, an organic film is coated to cover CNTs formed on a predetermined material layer. The organic film is etched to a predetermined depth to remove projected portions of the CNTs. After that, the organic film is removed.

Abstract: A semiconductor device manufacturing method wherein a metal suicide layer is formed via an in-situ process. The method includes forming a gate electrode on a semiconductor substrate; forming an insulation side wall at either lateral surface of the gate electrode; forming a source/drain region in a surface of the semiconductor substrate at either side of the gate electrode; forming a metal layer on the surface of the semiconductor substrate including the gate electrode; performing a plasma treatment on the metal layer; forming a capping material layer on the metal layer; performing an annealing process upon the semiconductor substrate, to form a metal silicide layer on the surface of the semiconductor substrate at positions corresponding to the gate electrode and the source/drain region; and removing the capping material layer and the metal layer remained without reaction with the gate electrode and the semiconductor substrate.

Abstract: Capacitors having upper electrodes that include a lower electrode, a dielectric layer and an upper electrode that includes a conductive metal nitride layer and a doped polysilicon germanium layer are provided. At least part of the conductive metal nitride layer is oxidized and/or at least part of the dielectric layer is nitridized.

Abstract: A method for manufacturing a SIMOX wafer includes: heating a silicon wafer, implanting oxygen ions so as to form a high oxygen concentration layer; implanting oxygen ions into the silicon wafer obtained by the forming of the high oxygen concentration layer to form an amorphous layer; and heat-treating the silicon wafer to form a buried oxide layer, wherein in the forming of the amorphous layer, the implantation of oxygen ions is carried out after preheating the silicon wafer to a temperature lower than the heating temperature of the forming of the high oxygen concentration layer. Alternatively, the method for manufacturing a SIMOX wafer includes: in the formation of the high oxygen concentration layer, implanting oxygen ions while heating a silicon wafer at a temperature of 300° C. or more; and in the formation of the amorphous layer, implanting oxygen ions after preheating the silicon wafer to a temperature of less than 300° C.

Abstract: An adhesive film is formed on an electrode film, and a coating film is formed thereon. Nickel, chrome, molybdenum, tungsten, aluminum or an alloy of them is used as a constituent material of the adhesive film. Gold, silver, platinum or an alloy of them is used as a constituent material of the coating film.

Abstract: In one embodiment the present invention includes a method of fabricating a quad flat no-lead (QFN) chip package. The method includes forming a stamped lead frame; forming a die pad and a lead shrink on one side of the stamped lead frame; mounting a die on the die pad; performing wire bonding; encapsulating the die and the wire bond with a molding compound; removing the stamped lead frame after encapsulating; and sawing the molding compound after the stamped lead frame has been removed. Such method results in improved quality of wire leads, improved lifespan of cutting blades, and reduction of burrs as compared to many existing methods of fabricating QFN chip packages.

Abstract: A PLZT film (30) is formed as the material film of a capacitor dielectric film and a top electrode film (31) is formed on the PLZT film (30). The top electrode film (31) comprises two IrOx films having different composition. Subsequently, back face of a semiconductor substrate (11) is cleaned and an Ir adhesion film (32) is formed on the top electrode film (31). Substrate temperature is set at 400° C. or above at that time. Thereafter, a TiN film and a TEOS film are formed sequentially as a hard mask. In such a method, carbon remaining on the top electrode film (31) after cleaning the back face is discharged into the chamber while the temperature of the semiconductor substrate (11) is kept at 400° C. or above in order to form the Ir adhesion film (32). Consequently, adhesion is enhanced between a TiN film being formed subsequently and the Ir adhesion film (32) thus preventing the TiN film from being stripped.

Abstract: A manufacturing method of a semiconductor device using a semiconductor manufacturing unit comprising a reaction chamber, a substrate mounting stage, and a high frequency power supply coupled to the substrate mounting stage, a blocking capacitor interposed between the substrate mounting stage and the high-frequency power supply to continuously perform a plurality of dry etching processing with respect to the same substrate in the same reaction chamber, the method includes: disposing a substrate on a substrate mounting stage, and applying high-frequency powers to the substrate mounting stage while introducing a fluorocarbon-based first gas to perform a first dry etching processing with respect to the substrate, the substrate including an organic material film and a silicon compound film sequentially deposited on a surface thereof and a resist film patterned on the silicon compound film, the first dry etching processing including processing the silicon compound film with the resist film being used as a mask; and

Abstract: A starting substrate can be appropriately oxidized, while oxidation of the starting substrate can be suppressed. The present invention includes a step of generating mixed plasma by causing a mixed gas of hydrogen (H2) gas and oxygen (O2) or oxygen-containing gas supplied to a starting substrate to form a plasma discharge, and processing the starting substrate by the mixed plasma; and a step of generating hydrogen plasma by causing hydrogen (H2) gas supplied to the starting substrate to form a plasma discharge, and processing the starting substrate by the hydrogen plasma.

Abstract: A method of manufacturing a semiconductor device contact including forming an insulating layer over a substrate and forming an agglutinating layer over the insulating layer. The agglutinating layer is then exposed to a plasma treatment. A barrier layer is formed over the plasma-treated agglutinating layer, and a conductive layer is formed over the barrier layer.

Abstract: A process for the selective removal of a substance from a substrate for etching and/or cleaning applications is disclosed herein. In one embodiment, there is provided a process for removing a substance from a substrate comprising: providing the substrate having the substance deposited thereupon wherein the substance comprises a transition metal ternary compound, a transition metal quaternary compound, and combinations thereof; reacting the substance with a process gas comprising a fluorine-containing gas and optionally an additive gas to form a volatile product; and removing the volatile product from the substrate to thereby remove the substance from the substrate.

Abstract: A method for manufacturing semiconductor devices includes a step of etching a sample including an interlayer insulating layer containing Al2O3 and a polysilicon or SiO2 layer in contact with the interlayer insulating layer using a plasma etching system. The interlayer insulating layer is etched with a gas mixture containing BCl3, Ar, and CH4 or He. The gas mixture further contains Cl2. The interlayer insulating layer is etched in such a manner that a time-modulated high-frequency bias voltage is applied to the sample. The interlayer insulating layer is etched in such a manner that the sample is maintained at a temperature of 100° C. to 200° C. The interlayer insulating layer and the polysilicon or SiO2 layer are separately etched in different chambers.

Abstract: A method for finishing a metal line for a semiconductor device is disclosed, in which polymer generated when forming the metal line including aluminum and its alloy is effectively removed and the metal line is prevented from being eroded. A chlorine radical and a chlorine compound remaining on a surface of the metal line are removed using H2O plasma and the polymer is removed using H2O gas and HF gas not plasma. Therefore, it is possible to improve reliability and yield of the semiconductor device.

Abstract: A method of manufacturing a semiconductor device contact including forming an insulating layer over a substrate and forming an agglutinating layer over the insulating layer. The agglutinating layer is then exposed to a plasma treatment. A barrier layer is formed over the plasma-treated agglutinating layer, and a conductive layer is formed over the barrier layer.

Abstract: Processes for forming semiconductor structure comprising a transfer layer transferred from a donor substrate are provided in which the resulting structure has improved quality with respect to defects and resulting structures therefrom. For example, a semiconductor on insulator (“SeOI”) structure can be formed using a donor substrate, a support substrate and an insulating layer. The donor substrate may be formed using CZ pulling of semiconductor material at a rate that results in the existence of vacancy clusters. An insulating layer for the SeOI structure can be formed by depositing an oxide layer on the donor or support substrate. An insulating layer can also be formed by thermal oxidizing the support substrate. An SeOI structure can be formed by combining the donor substrate, the support substrate, and the insulating layer there between, and detaching the combination including a thin layer of the donor substrate using a zone of weakness that was formed in the donor substrate.