Abstract: An example method of forming a pinned photodiode includes applying a photoresist mask to a semiconductor layer at a location where a transfer gate will subsequently be formed. First dopant ions are then implanted at a first angle to form a first dopant region under an edge of the photoresist mask. Next, a photoresist mask is etched such that a thickness of the photoresist mask is reduced to form a trimmed photoresist mask. Second dopant ions are then implanted at a second angle to form a second dopant region, wherein the second dopant ions are shadowed by the trimmed photoresist mask to exclude the second dopant ions from a region partially above the first dopant region and adjacent to an edge of the trimmed photoresist mask.

Abstract: A method of fabricating a semiconductor device is provided. The method comprises: (a) providing a first and a second conductor; (b) providing a conductive layer; (c) forming a part of the conductive layer into a data storage layer by a plasma oxidation process, wherein the data storage layer is positioned between the first and the second conductor.

Abstract: A production method for a semiconductor device includes providing a semiconductor substrate having semiconductor layer of a first conductivity type formed on a surface thereof; forming a first mask so as to cover a predetermined region of the semiconductor layer; (c) forming a well region of a second conductivity type by implanting impurity ions of the second conductivity type into the semiconductor layer having the first mask formed thereon; reducing the thickness of the first mask by removing a portion of the first mask; forming a second mask covering a portion of the well region by using photolithography; and forming a source region of the first conductivity type by implanting impurity ions of the first conductivity type into the semiconductor layer having the first mask with the reduced thickness and the second mask formed thereon.

Abstract: Methods for implanting an aromatic carbon molecule or a selected ionized lower mass byproduct into a workpiece generally includes vaporizing and ionizing aromatic carbon molecule in an ion source to create a plasma and produce aromatic carbon molecules and its ionized lower mass byproducts. The ionized aromatic carbon molecules and lower mass byproducts within the plasma are then extracted to form an ion beam. The ion beam is mass analyzed with a mass analyzer magnet to permit selected ionized aromatic carbon molecules or selected ionized lower mass byproducts to pass therethrough and implant into a workpiece.

Abstract: In the substrate and the epitaxial layer, isolation regions are formed to divide the substrate and the epitaxial layer into a plurality of element formation regions. Each of the isolation regions is formed by connecting first and second P type buried diffusion layers with a P type diffusion layer. By disposing the second P type buried diffusion layer between the first P type buried diffusion layer and the P type diffusion layer, a lateral diffusion width of the first P type buried diffusion layer is reduced. This structure allows a formation region of the isolation region to be reduced in size.

Abstract: A method for fabricating a metal-oxide semiconductor transistor is disclosed. The method includes the steps of: providing a semiconductor substrate; forming a gate structure on the semiconductor substrate; and performing a first ion implantation process to implant a first molecular cluster having carbon, boron, and hydrogen into the semiconductor substrate at two sides of the gate structure for forming a doped region, wherein the molecular weight of the first molecular cluster is greater than 100.

Abstract: Provided is a photoresist that includes a polymer having a backbone that is breakable and a photo acid generator that is free of bonding from the polymer. Further, provided is a method of fabricating a semiconductor device. The method includes providing a device substrate. A material layer is formed over the substrate. A photoresist material is formed over the material layer. The photoresist material has a polymer that includes a backbone. The photoresist material is patterned to form a patterned photoresist layer. A fabrication process is then performed to the material layer, wherein the patterned photoresist layer serves as a mask in the fabrication process. Thereafter, the patterned photoresist layer is treated in a manner that breaks the backbone of the polymer. The patterned photoresist layer is then removed.

Abstract: An isotopically-enriched, boron-containing compound comprising two or more boron atoms and at least one fluorine atom, wherein at least one of the boron atoms contains a desired isotope of boron in a concentration or ratio greater than a natural abundance concentration or ratio thereof. The compound may have a chemical formula of B2F4. Synthesis methods for such compounds, and ion implantation methods using such compounds, are described, as well as storage and dispensing vessels in which the isotopically-enriched, boron-containing compound is advantageously contained for subsequent dispensing use.

Abstract: Methods and devices for forming both high-voltage and low-voltage transistors on a common substrate using a reduced number of processing steps are disclosed. An exemplary method includes forming at least a first high-voltage transistor well and a first low-voltage transistor well on a common substrate separated by an isolation structure extending a first depth into the substrate, using a first mask and first implantation process to simultaneously implant a doping material of a first conductivity type into a channel region of the low-voltage transistor well and a drain region for the high-voltage transistor well.

Abstract: First, a first layer made of Ni or an alloy including Ni may be formed on an upper surface of a semiconductor layer. Next, a second layer made of silicon oxide may be formed on an upper surface of the first layer. Next, a part, which corresponds to a semiconductor region, of the second layer may be removed. Next, second conductive type ion impurities may be injected from upper sides of the first and second layers to the semiconductor layer after the removing step.

Abstract: A method for forming a lightly doped drain (LDD) region in a semiconductor substrate. The method includes generating an ion beam of a selected species, and accelerating the ion beam, wherein the accelerated ion beam includes a first accelerated portion and a second accelerated portion. The method further includes deflecting the accelerating ion beam, wherein the first and second accelerated portions are concurrently deflected into a first path trajectory having a first deflected angle and second path trajectory having a second deflected angle. In an embodiment, the first and second path trajectories travel in the same direction, which is perpendicular to the surface region of the semiconductor wafer, and the first deflected angle is greater than the second deflected angle. In an embodiment, the selected species may include an n-type ion comprising phosphorous (P), arsenic (As), or antimony (Sb).

Abstract: Herein an improved technique for generating uniform ion beam is disclosed. In one particular exemplary embodiment, the technique may be realized as a method for processing a substrate with an ion implanter comprising an ion source. The method may comprise: introducing dopant into an ion source chamber of the ion source, the dopant may comprise molecules containing boron and hydrogen; introducing diluent into the ion source chamber, the diluent containing halogen; ionizing the dopant and the diluent into molecular ions and halogen containing ions, the molecular ions containing boron and hydrogen; extracting the molecular ions and the halogen containing ions from the ions source chamber; and directing the molecular ions toward the substrate, where the halogen containing ions may improve uniformity of the molecular ions extracted from the ion source and extend the lifetime of the ion source.

Abstract: A manufacturing method of a semiconductor device includes preparing a semiconductor substrate which is a base substrate of the semiconductor device and which is formed with a concavity and convexity part on the surface of the semiconductor substrate. The method further comprises depositing on the surface of the semiconductor substrate an impurity thin film including an impurity atom which becomes a donor or an acceptor in the semiconductor substrate and performing an ion implantation from a diagonal upper direction to the impurity thin film deposited on the concavity and convexity part of the semiconductor substrate. The method still further comprises recoiling the impurity atom from the inside of the impurity thin film to the inside of the concavity and convexity part by performing the ion implantation.

Abstract: A thin film solar cell including a substrate, a first conductive layer, a photovoltaic layer and a second conductive layer is provided. The first conductive layer is doped with boron atoms so as to have a texture structure. Isotope B10 doped in the first conductive layer accounts for more than 19.9% relative to the total boron atoms. The first conductive layer is disposed on the substrate. The photovoltaic layer is disposed on the first conductive layer. The second conductive layer is disposed on the photovoltaic layer. The present invention further provides a manufacturing method of a thin film solar cell, a method for increasing carrier mobility in a semiconductor device, and a semiconductor device.

Abstract: A semiconductor substrate and a method of its manufacture has a semiconductor substrate having a carbon concentration in a range of 6.0×1015 to 2.0×1017 atoms/cm3, both inclusively. One principal surface of the substrate is irradiated with protons and then heat-treated to thereby form a broad buffer structure, namely a region in a first semiconductor layer where a net impurity doping concentration is locally maximized. Due to the broad buffer structure, lifetime values are substantially equalized in a region extending from an interface between the first semiconductor layer and a second semiconductor layer formed on the first semiconductor layer to the region where the net impurity doping concentration is locally maximized. In addition, the local minimum of lifetime values of the first semiconductor layer becomes high.

Abstract: A plasma processing apparatus comprises a plasma source configured to produce a plasma in a plasma chamber, such that the plasma contains ions for implantation into a workpiece. The apparatus also includes a focusing plate arrangement having an aperture arrangement configured to modify a shape of a plasma sheath of the plasma proximate the focusing plate such that ions exiting an aperture of the aperture arrangement define focused ions. The apparatus further includes a processing chamber containing a workpiece spaced from the focusing plate such that a stationary implant region of the focused ions at the workpiece is substantially narrower that the aperture. The apparatus is configured to create a plurality of patterned areas in the workpiece by scanning the workpiece during ion implantation.

Abstract: [Object] To provide a deposition apparatus 1 capable of suppressing a temporal change in film formation conditions. [Solution] In the deposition apparatus 1 including a substrate holder 12 supported in a vacuum chamber 10 grounded on the earth, a substrate 14 held by the substrate holder 12, deposition sources 34, 36 placed distant from the substrate 14 so as to face the substrate, an ion gun 38 for irradiating ions to the substrate 14, and a neutralizer 40 for irradiating electrons to the substrate 14, an irradiated ion guide member 50 and an irradiated electron guide member 52 are respectively attached to the ion gun 38 and the neutralizer 40.

Abstract: Disclosed herein is a partial implantation method for manufacturing semiconductor devices. The method involves implantation of dopant ions at different densities into a plurality of wafer regions, including first and second regions, defined in a wafer by means of a boundary line. In the method, first, second and third implantation zones are defined. The first implantation zone is the remaining part of the first region except for a specific part of the first region close to the boundary line, the second implantation zone is the remaining part of the second region except for a specific part of the second region close to the boundary line, and the third implantation zone is the remaining part of the wafer except for the first and second implantation zones.

Abstract: A semiconductor device includes an active zone doped according to a first type; a drain zone formed in the active zone and doped according to a second type; a source zone formed in the active zone and doped according to the second type; an insulated gate zone separated from the active zone by an insulating layer; a deep well, doped according to the second type such that the active zone is located between the gate zone and the well; a floating gate zone formed in the active zone under a space existing between the drain zone and the source zone, the floating gate zone including defects introducing deep levels in the bandgap of the semiconductor material, the deep levels being suited to trap carriers corresponding to the first type such that a charge state of the floating gate zone is modified and a drain source current varies due to the presence of a supplementary potential on the floating gate zone, a concentration of defects in the floating gate zone being strictly greater than 1018 cm?3.

Abstract: In an ion implantation method, a substrate is placed in a process zone and ions are implanted into a region of the substrate to form an ion implanted region. A porous capping layer comprising dispersed gas pockets is deposited on the ion implanted region.

Abstract: A method for removing a photoresist is disclosed. First, a substrate including a patterned photoresist is provided. Second, an ion implantation is carried out on the substrate. Then, a non-oxidative pre-treatment is carried out on the substrate. The non-oxidative pre-treatment provides hydrogen, a carrier gas and plasma. Later, a photoresist-stripping step is carried out so that the photoresist can be completely removed.

Abstract: The invention relates to the manufacture of an epitaxial layer, with the following steps: providing a semiconductor substrate; providing a Si—Ge layer on the semiconductor substrate, having a first depth; —providing the semiconductor substrate with a doped layer with an n-type dopant material and having a second depth substantially greater than said first depth; performing an oxidation step to form a silicon dioxide layer such that Ge atoms and n-type atoms are pushed into the semiconductor substrate by the silicon dioxide layer at the silicon dioxide/silicon interface, wherein the n-type atoms are pushed deeper into the semiconductor substrate than the Ge atoms, resulting in a top layer with a reduced concentration of n-type atoms; removing the silicon dioxide layer; growing an epitaxial layer of silicon on the semiconductor substrate with a reduced outdiffusion or autodoping.

Abstract: An ion implanter has an implant wheel with a plurality of wafer carriers distributed about a periphery of the wheel. Each wafer carrier has a heat sink for removing heat from a wafer on the carrier during the implant process by thermal contact between the wafer and the heat sink. A respective wafer lift structure on each carrier is moveable between first and second positions, with the wafer supported spaced away from the heat sink and in thermal contact with the heat sink respectively. The lift structure is operated to move between the first and second positions wheel the implant is rotating. This allows control of wafer temperature during the implant process by adjusting the thermal contact between wafers and heat sinks.

Abstract: An ion implanter has an implant wheel with a plurality of wafer carriers distributed about a periphery of the wheel. Each wafer carrier has a heat sink for removing heat from a wafer on the carrier during the implant process by thermal contact between the wafer and the heat sink. The wafer carriers have wafer retaining fences formed as cylindrical rollers with axes in the respective wafer support planes of the wafer carriers. The cylindrical surfaces of the rollers provide wafer abutment surfaces which can move transversely to the wafer support surfaces so that no transverse loading is applied by the fences to wafer edges as the wafer is pushed against the heat sink by centrifugal force. The wafer support surfaces comprise layers of elastomeric material and the movable abutment surfaces of the fences allow even thermal coupling with the heat sink over the whole area of the wafer.

Abstract: A solar cell including a first semiconductor layer including a first impurity, a second semiconductor layer disposed on the first semiconductor layer, the second semiconductor layer including a second impurity, a first electrode electrically connected to the first semiconductor layer, and a second electrode electrically connected to the second semiconductor layer, wherein the first semiconductor layer includes a plurality of impurity-doped regions including a third impurity, wherein a type of the third impurity is the same as a type of the second impurity.

Abstract: A transistor suitable for high-voltage applications and a method of manufacture is provided. A first device is formed by depositing a dielectric layer and a conductive layer over a substrate. A hard mask is deposited over the conductive layer and patterned using photolithography techniques. The photoresist material is removed prior to etching the underlying conductive layer and dielectric layer. The hard mask is also used as an implant mask. Another mask may be deposited and formed over the conductive layer to form other devices in other regions of the substrate. The other mask is preferably removed from over the hard mask prior to etching the conductive layer and the dielectric layer.

Abstract: A manufacturing method of a NOR flash memory with phosphorous and arsenic ion implantations mainly implants both phosphorous and arsenic ions on a drain area of a transistor memory unit, and controls specific energy and dosage for the implantation to reduce the defects of a memory device and improve the yield rate of the NOR flash memory.

Abstract: Doping with suppressed filament deterioration can be performed even in the case of doping in various conditions with an ion doping apparatus having a filament. After ion doping is completed, supply of a material gas is stopped and hydrogen or a rare gas is kept to be supplied. After that, current of the filament is decreased and correspondingly, filament temperature is decreased. Accordingly, in decreasing the filament temperature, the material gas around the filament has been replaced with hydrogen or a rare gas.

Abstract: In order to realize a plasma doping method capable of carrying out a stable low-density doping, exhaustion is carried out with a pump while introducing a predetermined gas into a vacuum chamber from a gas supplying apparatus, the pressure of the vacuum chamber is held at a predetermined pressure and a high frequency power is supplied to a coil from a high frequency power source. After the generation of plasma in the vacuum chamber, the pressure of the vacuum chamber is lowered, and the low-density plasma doping is performed to a substrate placed on a substrate electrode. Moreover, the pressure of the vacuum chamber is gradually lowered, and the high frequency power is gradually increased, thereby the low-density plasma doping is carried out to the substrate placed on the substrate electrode.

Abstract: Methods of implanting boron-containing ions using fluorinated boron-containing dopant species that are more readily cleaved than boron trifluoride. A method of manufacturing a semiconductor device including implanting boron-containing ions using fluorinated boron-containing dopant species that are more readily cleaved than boron trifluoride. Also disclosed are a system for supplying a boron hydride precursor, and methods of forming a boron hydride precursor and methods for supplying a boron hydride precursor. In one implementation of the invention, the boron hydride precursors are generated for cluster boron implantation, for manufacturing semiconductor products such as integrated circuitry.

Abstract: Structures and methods are provided for nanosecond electrical pulse anneal processes. The method of forming an electrostatic discharge (ESD) N+/P+ structure includes forming an N+ diffusion on a substrate and a P+ diffusion on the substrate. The P+ diffusion is in electrical contact with the N+ diffusion. The method further includes forming a device between the N+ diffusion and the P+ diffusion. A method of annealing a structure or material includes applying an electrical pulse across an electrostatic discharge (ESD) N+/P+ structure for a plurality of nanoseconds.

Abstract: A method of producing a Schottky diode includes the steps of: forming a resist layer on the semiconductor substrate; performing a first exposure process on the resist layer; performing a first developing process for developing the resist layer to form a first Schottky diode having an excess region; performing a first cleaning process; performing a second exposure process on the first Schottky diode; performing a second developing process on the first Schottky diode to remove the excess region from the first Schottky diode so that a second Schottky diode corresponding to the specific Schottky diode is formed; and performing a second cleaning process.

Abstract: A semiconductor device is formed having a trench adjacent to a current carrying region of the device. The trench is formed having a depth greater than the depth of a tub region of the device. Increasing the trench depth moves a region of higher field strength from the tub region to a region along the trench. The region along the trench does not have a junction and may withstand the higher field strength.

Abstract: A method of forming complementary metal-oxide-silicon logic field effect transistors, high power transistors and electrostatic discharge protection diodes and/or electrostatic discharge protection shunt transistors on the same integrated circuit chip using ion implantations used to fabricate the field effect transistors and high-power transistor to simultaneously fabricate the electrostatic discharge protection diodes and/or electrostatic discharge protection shunt transistors.

Abstract: A compound semiconductor is placed in a reaction vessel (12) of which the inner gas is subjected to replacement with a low-vapor-pressure gas (2) whose equilibrium vapor pressure at the melting point of the compound semiconductor is 1 atm or lower. The low-vapor-pressure gas is urged to flow along the surface of the compound semiconductor while keeping the internal pressure of the reaction vessel at a value not lower than that equilibrium vapor pressure. The surface of the compound semiconductor is irradiated with a pulsed-laser light (3) whose photon energy is higher than the band gap of the compound semiconductor. Thus, only that part of the compound semiconductor which is located at the pulsed-laser light irradiation position is instantly heated and melted while keeping the atmospheric temperature of the low-vapor-pressure gas at a room temperature or a temperature equal to or lower than the decomposition temperature.

Abstract: A method of applying a silicide to a substrate while minimizing adverse effects, such as lateral diffusion of metal or “piping” is disclosed. The implantation of the source and drain regions of a semiconductor device are performed at cold temperatures, such as below 0° C. This cold implant reduces the structural damage caused by the impacting ions. Subsequently, a silicide layer is applied, and due to the reduced structural damage, metal diffusion and piping into the substrate is lessened. In some embodiments, an amorphization implant is performed after the implantation of dopants, but prior to the application of the silicide. By performing this pre-silicide implant at cold temperatures, similar results can be obtained.

Abstract: In one embodiment, a patterning method is disclosed. The method includes applying an uncured imprint material containing a first curing agent and a second curing agent onto a substrate. The method includes pressing a template against the imprint material. The method includes reacting the first curing agent with the template pressed against the imprint material. The method includes stripping the template from the imprint material. In addition, the method includes reacting the second curing agent.

Abstract: A solid-state imaging device includes a first-conductive semiconductor layer, a second-conductive semiconductor layer that is provided on the first-conductive semiconductor layer, a light receiving element that is formed in the second-conductive semiconductor layer, and an element isolation region that is formed to surround the light receiving element in an in-plane direction of the second-conductive semiconductor layer, in which the element isolation region includes a first-conductive first element isolation unit that is connected to the first-conductive semiconductor layer, a hollow that is formed on the first-conductive first element isolation unit, and a first-conductive second element isolation unit that is formed on the hollow.

Abstract: A method of implanting carbon ions into a target substrate, including: ionizing a carbon containing dopant material to produce a plasma having ions; optionally co-flowing an additional gas or series of gases with the carbon-containing dopant material; and implanting the ions into the target substrate. The carbon-containing dopant material is of the formula CwFxOyHz wherein if w=1, then x>0 and y and z can take any value, and wherein if w>1 then x or y is >0, and z can take any value. Such method significantly improves the efficiency of an ion implanter tool, in relation to the use of carbon source gases such as carbon monoxide or carbon dioxide.

Abstract: According to one embodiment, in a method for manufacturing a semiconductor device, a surface region of a semiconductor substrate is modified into an amorphous layer. A microwave is irradiated to the semiconductor substrate in which the amorphous layer is formed in a dopant-containing gas atmosphere so as to form a diffusion layer in the semiconductor substrate. The dopant is diffused into the amorphous layer and is activated.

Abstract: A sidewall spacer film or the like is removed without damaging a device structure section. Specifically disclosed is a method for manufacturing a semiconductor device, which comprises a step of forming a first thin film composed of GeCOH or GeCH on a substrate (21) to be processed, a step of removing a part of the first thin film and obtaining a remaining portion (30), and a processing step of performing a certain process on the substrate (21) through the space formed by removing the first thin film.

Abstract: In order to realize a plasma doping method capable of carrying out a stable low-density doping, exhaustion is carried out with a pump while introducing a predetermined gas into a vacuum chamber from a gas supplying apparatus, the pressure of the vacuum chamber is held at a predetermined pressure and a high frequency power is supplied to a coil from a high frequency power source. After the generation of plasma in the vacuum chamber, the pressure of the vacuum chamber is lowered, and the low-density plasma doping is performed to a substrate placed on a substrate electrode. Moreover, the pressure of the vacuum chamber is gradually lowered, and the high frequency power is gradually increased, thereby the low-density plasma doping is carried out to the substrate placed on the substrate electrode.

Abstract: A thin wafer handling structure includes a semiconductor wafer, a release layer that can be released by applying energy, an adhesive layer that can be removed by a solvent, and a carrier, where the release layer is applied on the carrier by coating or laminating, the adhesive layer is applied on the semiconductor wafer by coating or laminating, and the semiconductor wafer and the carrier is bonded together with the release layer and the adhesive layer in between. The method includes applying a release layer on a carrier, applying an adhesive layer on a semiconductor wafer, bonding the carrier and the semiconductor wafer, releasing the carrier by applying energy on the release layer, e.g. UV or laser, and cleaning the semiconductor's surface by a solvent to remove any residue of the adhesive layer.

Abstract: An integrated circuit is disclosed having symmetric and asymmetric MOS transistors of the same polarity, oriented perpendicularly to each other, formed by concurrent halo ion, LDD ion and/or S/D ion implant processes using angled, rotated sub-implants which vary the tilt angle, dose and/or energy between rotations. Implanted halo, LDD and/or S/D source and drain regions formed by angled subimplants may have different extents of overlap with, or lateral separation from, gates of the two types of transistors, producing transistors with two different sets of electrical properties. A process for concurrently fabricating the two types of transistors is also disclosed. Specific embodiments of processes for concurrently forming symmetric and asymmetric transistors are disclosed.

Abstract: Methods and devices for forming an ultra-thin doping layer in a semiconductor substrate include introducing a thin film of a dopant onto a surface of the substrate and driving at least a portion of the thin dopant layer into a surface of the semiconductor. Gas ions used in the driving-in process may be inert to minimize contamination during the drive in process. The thin films can be deposited using know methods, such as physical deposition and atomic layer deposition. The dopant layers can be driven into the surface of the semiconductor using known techniques, such as pulsed plasma discharge and ion beam. In some embodiments, a standard ion implanter can be retrofit to include a deposition source.

Abstract: A method of fabricating a semiconductor device is provided. First, a stacked structure is formed on a substrate. The stacked structure includes, from the substrate, a dielectric layer and a conductive gate in order. An ion implant process is performed to form doped regions in the substrate on the opposite sides of the stacked structure. Thereafter, source-side spacer is formed on a sidewall of the stacked structure. A thermal process is performed to activate the doped regions, thereby forming a source in the substrate under the sidewall of the stacked structure having the source-side spacer and a drain in the substrate on another side of the stacked structure.

Abstract: A method of ion implantation comprising: providing a plasma within a plasma region of a chamber; positively biasing a first grid plate, wherein the first grid plate comprises a plurality of apertures; negatively biasing a second grid plate, wherein the second grid plate comprises a plurality of apertures; flowing ions from the plasma in the plasma region through the apertures in the positively-biased first grid plate; flowing at least a portion of the ions that flowed through the apertures in the positively-biased first grid plate through the apertures in the negatively-biased second grid plate; and implanting a substrate with at least a portion of the ions that flowed through the apertures in the negatively-biased second grid plate.

Abstract: A photodiode has a carrier accumulation layer of a second conductivity type and a surface area of a first conductivity type deposited in order from an inside towards a surface of a first conductivity type well region. A transfer transistor is formed so that a transfer gate electrode of the transfer transistor partially overlaps the surface layer of the photodiode and is formed above a surface of the first conductivity type well region with a gate insulating film therebetween. The surface layer includes a first surface layer, which partially overlaps the transfer gate electrode in the direction of the x-axis, and a second surface layer adjacent to the first surface layer. A concentration of the impurity of the first conductivity type is higher in the second surface layer than in the first surface layer.

Abstract: In some aspects, a method of forming a memory cell is provided that includes (1) forming a first conductor above a substrate; (2) forming a diode above the first conductor; (3) forming a reversible resistance-switching element above the first conductor using a selective deposition process; and (4) forming a second conductor above the diode and the reversible resistance-switching element. Numerous other aspects are provided.

Abstract: In a production method for a semiconductor device relating to the present invention, first, a pattern of a resist film made of organic polymers is formed on a semiconductor substrate. Next, impurity ions with 1×1014 cm?2 or greater of dose amount are implanted into the semiconductor substrate using the resist film pattern as a mask. The resist film pattern mask is removed sequentially through an oxidation treatment, swelling treatment and removal treatment. In the oxidation treatment, a treatment to oxidize a hardened layer formed in a surface portion of the resist film pattern by the ion implantation is implemented. In the swelling treatment, a treatment to swell the organic polymers composing the resist film pattern where the hardened layer has been oxidized using a chemical solution is implemented. In the removal treatment, the swollen resist film pattern is removed using the chemical solution used for the swelling treatment.