Abstract: An image sensor and manufacturing method thereof are provided. The image sensor can include a gate, a channel region, a first p-type doped region, a second p-type doped region, an n-type doped region, and a floating diffusion region. The gate can be disposed on a semiconductor substrate, and the channel region can be disposed in the semiconductor substrate under the gate. The first p-type doped region can be disposed at a side of the gate and can be adjacent to the channel region. The second p-type doped region can be disposed under the first p-type doped region and spaced apart from the gate. The n-type doped region can be disposed under the first and second p-type doped regions, and the floating diffusion region can be disposed at another side of the gate.

Abstract: One embodiment relates to a method of forming an integrated circuit. In this method, at least one dopant species of a first conductivity type is implanted in a first manner along a first axis to form first pocket implant regions extending at least partially under some gates. At least one dopant species of the first conductivity type is then implanted in a second manner that differs from the first manner along a second axis that is laterally rotated with respect to the first axis to form second pocket implant regions extending at least partially under other gates.

Abstract: This disclosure relates to strain engineering to improve the performance of semiconductor components that include a strained region of the semiconductor substrate. The disclosure involves the amorphization of the target region and the recrystallization of the atomic lattice whilst imposing a strain on the region. The region so formed will form a strained lattice, wherein the strain is uniformly distributed throughout the region, and which retains the intrinsic strain even if the source of the mechanical strain is removed. The disclosure includes methods for forming semiconductor substrates having strained regions (such as semiconductor components having a strained channel region) and semiconductor components formed thereby, as well as variations having various properties and advantages.

Abstract: A semiconductor memory device includes a first active region, a second active region, a first element isolating region and a second element isolating region. The first active region is formed in a semiconductor substrate. The second active region is formed in the semiconductor substrate. The first element isolating region electrically separates the first active regions adjacent to each other. The second element isolating region electrically separates the second active regions adjacent to each other. An impurity concentration in a part of the second active region in contact with a side face of the second element isolating region is higher than that in the central part of the second active region, and a impurity concentration in a part of the first active region in contact with a side face of the first element isolating region is equal to that in the first active region.

Abstract: A semiconductor device is provided in which the contact resistance of the interface between an electrode and the semiconductor substrate is reduced. The semiconductor device includes a 4H polytype SiC substrate, and an electrode formed on a surface of the substrate. A 3C polytype layer, which extends obliquely relative to the surface of the substrate and whose end portion at the substrate surface is in contact with the electrode, is formed at the surface of the substrate. The 3C polytype layer has a lower bandgap than 4H polytype. Hence, electrons present in the 4H polytype region pass through the 3C polytype layer and reach the electrode. More precisely, the width of the passageway of the electrons is determined by the thickness of the 3C polytype layer. Consequently, with this semiconductor device, in which the passageway of the electrons is narrow, the electrons are able to reach the electrode at a speed close to the theoretical value, by the quantum wire effect.

Abstract: Procedure to obtain semiconductor materials with electronic levels close to the mid-bandgap (deep levels) which do not suffer from the non-radiative recombination by multiple phonon emission (MPE) associated to the existence of that kind of levels. The procedure consist in doping by any means the semiconductor with a density sufficiently high of the impurities producing the deep level, so that a Mott transition of the electron wavefunctions representing the localized states in the impurities is induced, in such a way that these wavefunctions become distributed across the whole semiconductor and are shared by all the impurities. When this happens, local charge density variations, and thus non-radiative recombination by MPE, disappear. Based on the resulting materials (semiconductors with three separate energy bands and radiative behavior (1), (2) and (3)) different optoelectronic devices can be fabricated (solar cells, photodetectors, lasers, etc.

Abstract: A method of manufacturing an IC that comprises fabricating a semiconductor device. Fabricating the device includes depositing a photoresist layer on a substrate surface and implanting one or more dopant species through openings in the photoresist layer into the substrate, and, into the photoresist layer, thereby forming an implanted photoresist layer. Fabricating the device also includes removing the implanted photoresist layer. Removing the implanted photoresist layer includes exposing the implanted photoresist layer to a mixture that includes sulfuric acid, hydrogen peroxide and ozone. The mixture is at a temperature of at least about 130°.

Abstract: The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer (110) beneath the gate dielectric (50) and source and drain regions (80) of a MOS transistor. The carbon containing layer (110) will prevent the diffusion of dopants into the region (40) directly beneath the gate dielectric layer (50).

Abstract: An integrated semiconductor structure and a method for fabricating an integrated semiconductor structure in a bulk semiconductor wafer.

Abstract: An impurity of one conductivity type is ionized and accelerated by electric field before being implanted into a semiconductor layer to form a high concentration impurity region near its surface. Then the semiconductor layer is irradiated with continuous wave laser light for melting and crystallization or recrystallization, through which a region where the concentration of the impurity is constant is formed in the semiconductor layer. The continuous wave laser light irradiation may bring the semiconductor layer to the crystalline phase from the amorphous phase as long as the impurity element is re-distributed. The impurity is segregated through this process to newly create a high concentration region. However, this region is removed and no problem arises.

Abstract: A recessed-gate transistor device includes a gate electrode embedded in a gate trench formed in a semiconductor substrate, wherein the gate trench includes a vertical sidewall and a U-shaped bottom. A source region is provided at one side of the gate trench within the semiconductor substrate. A drain region is provided at the other side thereof. An asymmetric gate dielectric layer is formed between the gate electrode and the semiconductor substrate. The asymmetric gate dielectric layer has a first thickness between the gate electrode and the drain region and a second thickness between the gate electrode and the source region, wherein the first thickness is thicker than the second thickness.

Abstract: The present invention relates to a method of forming junctions of a semiconductor device. According to the method of forming junctions of a semiconductor device in accordance with an aspect of the present invention, there is provided a semiconductor substrate in which a transistor including the junctions are formed. A first thermal treatment process for forming a passivation layer over the semiconductor substrate including the junctions is performed. Here, the passivation layer functions to prevent impurities within the junctions from being drained. A pre-metal dielectric layer is formed over the semiconductor substrate including the passivation layer.

Abstract: An exposure mask includes a transparent substrate; a first pattern portion formed on the transparent substrate using at least one light-shielding pattern having a predetermined shape; and a translucent layer which is formed at a section including a first pattern region having the first pattern portion, which allows exposure light to pass therethrough, and which has a transmittance greater than that of the light-shielding pattern.

Abstract: Means and methods for producing surface-activated semiconductor nanoparticles suitable for in vitro and in vivo applications that can fluoresce in response to light excitation. Semiconductor nanostructures can be produced by generating a porous layer in semiconductor substrate comprising a network of nanostructures. Prior or subsequent to cleavage from the substrate, the nanostructures can be activated by an activation means such as exposing their surfaces to a plasma, oxidation or ion implantation. In some embodiments, the surface activation renders the nanostructures more hydrophilic, thereby facilitating functionalization of the nanoparticles for either in vitro or in vivo use.

Abstract: Ion implantation is carried out to form a p-well region and a source region in parts of a high resistance SiC layer on a SiC substrate, and a carbon film is deposited over the substrate. With the carbon film deposited over the substrate, annealing for activating the implanted dopant ions is performed, and then the carbon film is removed. Thus, a smooth surface having hardly any surface roughness caused by the annealing is obtained. Furthermore, if a channel layer is epitaxially grown, the surface roughness of the channel layer is smaller than that of the underlying layer. Since the channel layer having a smooth surface is provided, it is possible to obtain a MISFET with a high current drive capability.

Abstract: Exemplary embodiments provide methods for implementing an ultra-high temperature (UHT) anneal on silicon germanium (SiGe) semiconductor materials by co-implanting carbon into the SiGe material prior to the UHT anneal. Specifically, the carbon implantation can be employed to increase the melting point of the SiGe material such that an ultra high temperature can be used for the subsequent anneal process. Wafer warpage can then be reduced during the UHT anneal process and potential lithographic mis-alignment for subsequent processes can be reduced. Exemplary embodiments further provide an inline control method, wherein the wafer warpage can be measured to determine the litho-mis-alignment and thus to control the fabrication process. In various embodiments, the disclosed methods can be employed for the fabrication of source/drain extension regions and/or source/drain regions of transistor devices, and/or for the fabrication of base regions of bipolar transistors.

Abstract: A method for fabricating a MOSFET having an active area and an edge termination area is disclosed. The method includes forming a first plurality of implants at the bottom of trenches located in the active area and in the edge termination area. A second plurality of implants is formed at the bottom of the trenches located in the active area. The second plurality of implants formed at the bottom of the trenches located in the active area causes the implants formed at the bottom of the trenches located in the active area to reach a predetermined concentration. In so doing, the breakdown voltage of both the active and edge termination areas can be made similar and thereby optimized while maintaining advantageous RDson.

Abstract: Disclosed is a solid-state imaging device includes for each pixel a photoelectric conversion unit, a charge accumulating portion, and a potential barrier provided between the photoelectric conversion unit and the charge accumulating portion, in a thickness direction of a substrate. When light is received, a first charge derived from one of electron-hole pairs generated by photoelectric conversion is accumulated in the photoelectric conversion unit as signal charge, and the potential barrier is modulated by a second charge derived from the other of the electron-hole pairs so that the first charge that has accumulated in the charge accumulating portion is supplied to the photoelectric conversion unit.

Abstract: This invention relates to a method of producing B2H6 (diborane) in semiconductor wafer processing apparatus. In particular, although not exclusively, this invention relates to producing a dopant gas species containing a desired dopant element, and then producing dopant ions for implanting in semiconductor wafers using an ion implanter. The present invention provides such a method by passing a flow of a boron containing gas such as BF3 over a hydrogen containing solid such as NaH thereby forming an outflow of B2H6.

Abstract: A resistance-changing function body includes an object made of a first substance and interposed between a first electrode and a second electrode, and a plurality of particles made of a second substance and arranged within the object so that an electrical resistance between the first electrode and the second electrode is changed before and after application of a specified voltage to between the first electrode and the second electrode. The first substance makes an electrical barrier against the second substance. With this constitution, by applying a specified voltage to between the first electrode and the second electrode, the electrical resistance can be changed depending on a state of the particles made of the second substance. Also, by virtue of a simple structure, a resistance-changing function body of small size is provided with low cost.

Abstract: A method for manufacturing a semiconductor device includes providing a semiconductor substrate including a first surface and a second surface which is arranged opposite to the first surface. The semiconductor substrate includes a plurality of trench structures extending from the first surface into the semiconductor substrate. The thickness of the semiconductor substrate is then reduced by removing semiconductor material at the second surface to obtain a processed second surface with exposed bottom portions of the trench structures. At least a first mask is formed on the processed second surface in a self-aligned manner with respect to the bottom portions of the trench structures, and doping regions are formed in the semiconductor substrate between the trench structures.

Abstract: A method of forming crystalline Si:C in source and drain regions is provided. After formation of shallow trench isolation and gate electrodes of field effect transistors, gate spacers are formed on gate electrodes. Preamorphization implantation is performed in the source and drain regions, followed by carbon implantation. The upper portion of the source and drain regions comprises an amorphous mixture of silicon, germanium, and/or carbon. An anti-reflective layer is deposited to enhance the absorption of a laser beam into the silicon substrate. The laser beam is scanned over the silicon substrate including the upper source and drain region with the amorphous mixture. The energy of the laser beam is controlled so that the temperature of the semiconductor substrate is above the melting temperature of the amorphous mixture but below the glass transition temperature of silicon oxide so that structural integrity of the semiconductor structure is preserved.

Abstract: A flash memory and a manufacturing method of the same includes a shallow trench isolation and an active region formed at a substrate, a plurality of stacked gates formed on and/or over the active region, a deep implant region formed at a lower portion of the shallow trench isolation and the active region between the stacked gates and a shallow implant region formed at a surface of the active region between the stacked gates.

Abstract: An image sensor and manufacturing method thereof are provided. A semiconductor substrate can include a center region and an edge region, each with a gate. A first impurity region and a second impurity region can be provided in the semiconductor substrate to a first side of each gate. A floating diffusion region can be provided to a second side of teach gate. A third impurity region can be provided in the semiconductor substrate to the first side of the gate in the edge region.

Abstract: Provided are an image sensor and a manufacturing method thereof. The image sensor can include a first epitaxial layer with a first ion implantation layer, a second epitaxial layer with a second ion implantation layer, and a third epitaxial layer with a third ion implantation layer on a substrate. The first, second, and third ion implantation layers can provide a red, green, and blue photodiode, respectively. A trench can be formed in the third epitaxial layer on the third ion implantation layer to remove the damaged surface of the third epitaxial layer.

Abstract: A method to provide a dopant profile adjustment solution in plasma doping systems for meeting both concentration and junction depth requirements. Bias ramping and bias ramp rate adjusting may be performed to achieve a desired dopant profile so that surface peak dopant profiles and retrograde dopant profiles are realized. The method may include an amorphization step in one embodiment.

Abstract: The present invention provides a method for manufacturing a semiconductor device. In one embodiment, the method for manufacturing the semiconductor device includes a method for manufacturing a zener diode, including among others, forming a doped well (240) within a substrate (210) and forming a suppression implant (420) within the substrate (210). The method for manufacturing the zener diode may further include forming a cathode (620) and an anode (520) within the substrate (210), wherein the suppression implant (420) is located proximate the doped well (240) and configured to reduce threading dislocations.

Abstract: A process for forming diffused region less than 20 nanometers deep with an average doping dose above 1014 cm?2 in an IC substrate, particularly LDD region in an MOS transistor, is disclosed. Dopants are implanted into a source dielectric layer using gas cluster ion beam (GCIB) implantation, molecular ion implantation or atomic ion implantation resulting in negligible damage in the IC substrate. A spike anneal or a laser anneal diffuses the implanted dopants into the IC substrate. The inventive process may also be applied to forming source and drain (S/D) regions. One source dielectric layer may be used for forming both NLDD and PLDD regions.

Abstract: A method of forming a Si strained layer 16 on a Si substrate 10 includes forming a first SiGe buffer layer 12 on the Si substrate 10. Then, the first SiGe buffer layer is implanted with an amorphising implant to render the first SiGe buffer layer amorphous using ion implantation. A second SiGe buffer layer 14 is grown on the first SiGe buffer layer after annealing. This produces a relaxed SiGe layer 12, 14. Then, the strained layer of Si 16 is grown.

Abstract: A semiconductor memory device that has an isolated area comprised of one conductivity and formed in part by a buried layer of a second conductivity that is implanted in a substrate. The walls of the isolated area are formed by implants that are comprised of the second conductivity and extend down to the buried layer. The isolated region has implanted source lines and is further subdivided by overlay strips of the second conductivity that extend substantially down to the buried layer. Each isolation region can contain one or more blocks of memory cells.

Abstract: A method for fabricating a flash memory device is disclosed that improves hot carrier injection efficiency by forming a gate after forming source and drain implants using a sacrificial insulating layer pattern, which includes forming a sacrificial insulating pattern layer over a flash memory channel region of a semiconductor substrate; forming source and drain regions in the semiconductor substrate by ion implantation using the sacrificial insulating pattern layer as a mask; removing portions of the sacrificial insulating pattern layer; sequentially forming an ONO-type dielectric layer and a gate material layer; selectively etching the gate material layer and at least part of the gate dielectric layer to form a gate; and forming gate sidewall spacers at sides of the gate.

Abstract: There are provided a plasma doping method and apparatus which is excellent in a repeatability and a controllability of an implanting depth of an impurity to be introduced into a sample or a depth of an amorphous layer. A plasma doping method of generating a plasma in a vacuum chamber and colliding an ion in the plasma with a surface of a sample to modify a surface of a crystal sample to be amorphous, includes the steps of carrying out a plasma irradiation over a dummy sample to perform an amorphizing treatment together with a predetermined number of samples, irradiating a light on a surface of the dummy sample subjected to the plasma irradiation, thereby measuring an optical characteristic of the surface of the dummy sample, and controlling a condition for treating the sample in such a manner that the optical characteristic obtained at the measuring step has a desirable value.

Abstract: A semiconductor component having at least one pn junction and an associated production method. The semiconductor component has a layer sequence of a first zone having a first dopant. The first zone faces a first main area. Adjacent to the first zone are a second zone having a low concentration of a second dopant, a subsequent buffer layer, the third zone, also having the second dopant and a subsequent fourth zone having a high concentration of the second dopant. The fourth zone faces a second main area. In this case, the concentration of the second doping of the buffer layer is higher at the first interface of the barrier layer with the second zone than at the second interface with the fourth zone. According to the invention, the buffer layer is produced by ion implantation.

Abstract: A method includes forming trenches in a semiconductor substrate by etching the semiconductor substrate; and then forming a first ion injection layer in sidewalls of the trenches at an active region of the semiconductor substrate; and then forming a second ion injection layer in a substantially horizontally extending surface of the active region located between the trenches; and then performing a threshold voltage adjusting implant on at least the active region, wherein the first ion injection layer and the second ion injection layer overlap at a portion of the active region to provide the overlapping portion with a higher doping concentration than a non-overlapping portion of the active region; and then forming a gate structure on the active region.

Abstract: A barrier implanted region of a first conductivity type formed in lieu of an isolation region of a pixel sensor cell that provides physical and electrical isolation of photosensitive elements of adjacent pixel sensor cells of a CMOS imager. The barrier implanted region comprises a first region having a first width and a second region having a second width greater than the first width, the second region being located below the first region. The first region is laterally spaced from doped regions of a second conductivity type of adjacent photodiodes of pixel sensor cells of a CMOS imager.

Abstract: A method for manufacturing a semiconductor device includes forming an impurity diffusion layer in a surface of a semiconductor substrate, wherein the forming the impurity diffusion layer comprises irradiating material including M1x M2y (y/x?1.2, where x is a ratio of M1, y is a ratio of M2, M1 is material which serves as acceptor or donor in the semiconductor device, M2 is material which does not serve as neither donor nor acceptor in the semiconductor device (except semiconductor of the semiconductor substrate)) onto the semiconductor substrate, and heating the semiconductor substrate by light.

Abstract: A semiconductor component includes a semiconductor body having a first side, a second side, an edge delimiting the semiconductor body in a lateral direction, an inner region and an edge region. A first semiconductor zone of a first conduction type is arranged in the inner region and in the edge region. A second semiconductor zone of a second conduction type is arranged in the inner region and adjacent to the first semiconductor zone. A trench is arranged in the edge region and has first and second sidewalls and a bottom, and extends into the semiconductor body. A doped first sidewall zone of the second conduction type is adjacent to the first sidewall of the trench. A doped second sidewall zone of the second conduction type is adjacent to the second sidewall of the trench. A doped bottom zone of the second conduction type is adjacent to the bottom of the trench. Doping concentrations of the sidewall zones are lower than a doping concentration of the bottom zone.

Abstract: It is object to provide a manufacturing method of an SOI substrate provided with a single-crystal semiconductor layer, even in the case where a substrate having a low allowable temperature limit, such as a glass substrate, is used and to manufacture a high-performance semiconductor device using such an SOI substrate. Light irradiation is performed on a semiconductor layer which is separated from a semiconductor substrate and bonded to a support substrate having an insulating surface, using light having a wavelength of 365 nm or more and 700 nm or less, and a film thickness d (nm) of the semiconductor layer which is irradiated with the light is made to satisfy d=?/2n×m±? (nm), when a light wavelength is ? (nm), a refractive index of the semiconductor layer is n, m is a natural number greater than or equal to 1 (m=1, 2, 3, 4, . . . ), and 0???10 is satisfied.

Abstract: A method for fabricating a metal-oxide semiconductor transistor is disclosed. First, a semiconductor substrate having a gate structure thereon is provided, and a spacer is formed around the gate structure. An ion implantation process is performed to implant a molecular cluster containing boron into the semiconductor substrate surrounding the spacer for forming a source/drain region. The weight ratio of each boron atom within the molecular cluster is preferably less than 10%. Thereafter, a millisecond annealing process is performed to activate the molecular cluster within the source/drain region.

Abstract: A plasma doping apparatus includes a pulsed power supply that generates a pulsed waveform having a first period with a first power level and a second period with a second power level. A plasma source generates a pulsed plasma with the first power level during the first period and with the second power level during the second period. A bias voltage power supply generates a bias voltage waveform at an output that is electrically connected to a platen which supports a substrate. The bias voltage waveform having a first voltage during a first period and second voltage with a negative potential that attract ions in the plasma to the substrate for plasma doping during a second period. At least one of the first and second power levels of the RF waveform is chosen to at least partially neutralize charge accumulating on the substrate.

Abstract: The present invention is directed to an SOI device with charging protection and methods of making same. In one illustrative embodiment, a device is formed on an SOI substrate including a bulk substrate, a buried insulation layer and an active layer. The device includes a transistor formed in an isolated portion of the active layer, the transistor including a gate electrode and a source region. The device further includes a first conductive bulk substrate contact extending through the active layer and the buried insulation layer, the first conductive bulk substrate contact being conductively coupled to the source region and the bulk substrate, and a second conductive bulk substrate contact extending through the active layer and the buried insulation layer, the second conductive bulk substrate being conductively coupled to the gate electrode and the bulk substrate.

Abstract: An approach that determines an ion implantation processing characteristic in a plasma ion implantation of a substrate is described. In one embodiment, there is a light source configured to direct radiation onto the substrate. A detector is configured to measure radiation reflected from the substrate. A processor is configured to correlate the measured radiation reflected from the substrate to an ion implantation processing characteristic.

Abstract: A semiconductor device and a method for manufacturing the device are disclosed. The device, and the method for making the device, includes the steps of forming a gate oxide film on a semiconductor substrate; forming a gate poly silicon layer on the gate oxide film; and implanting deuterium ions over the semiconductor substrate including the gate poly silicon layer.

Abstract: A process for the manufacture of a substrate having a top layer of a first material and an underlying layer of a second material whose lattice parameter is different from that of the first material. The process includes the steps of conducting an amorphization of the top layer to create an amorphous region in the top layer lying between an exposed surface and an amorphization interface, with that portion of the top layer below the interface being shielded from the amorphization and remaining as a crystalline structure; recrystallizing the amorphous region while also creating a network of defects at the interface, wherein the network forms a boundary for dislocations from the crystalline structure of the top layer, and containing the dislocations in the portion of the top layer that is located below the interface. Also, the substrates obtained by the method.

Abstract: A semiconductor device is disclosed that improves heat dissipation by providing blind contact elements on a dielectric layer. Embodiments are disclosed which include a substrate having at least one electrode contact area accessible at a surface of the substrate and a surface adjacent the electrode contact area, a dielectric layer disposed above the surface; an intermediate oxide layer disposed above the dielectric layer, a current conducting metallization layer disposed above the intermediate oxide layer; and at least one contact element vertically extending from the dielectric layer through the intermediate oxide layer to the metallization layer above the surface adjacent the electrode contact area, the at least one contact element having a heat conductivity that is higher than that of the intermediate oxide layer.

Abstract: A method for manufacturing a solid state imaging device includes steps of forming a photodiode layer buried in a semiconductor substrate by ion injection and of forming a shielding layer buried in the photodiode layer by ion injection. At least in the ion injection process in the step of forming the shielding layer, an ion injection pause period is provided at least one time during whole ion injection step. According to the method, crystal defects are prevented from generating even if ion injection is performed with high energy, thereby suppressing dark current without complexity in manufacturing process.

Abstract: A method of semiconductor manufacturing is disclosed in which doping is accomplished by the implantation of ion beams formed from ionized molecules, and more particularly to a method in which molecular and cluster dopant ions are implanted into a substrate with and without a co-implant of non-dopant cluster ion, such as a carbon cluster ion, wherein the dopant ion is implanted into the amorphous layer created by the co-implant in order to reduce defects in the crystalline structure, thus reducing the leakage current and improving performance of the semiconductor junctions. Dopant ion compounds of the form AnHx+ and AnRzHx+ are used in order to minimize crystal defects as a result of ion implantation. These compounds include co-implants of carbon clusters with implants of monomer or cluster dopants or simply implanting cluster dopants.

Abstract: Method of producing a vertically inhomogeneous platinum or gold distribution in a semiconductor substrate with a first and a second surface opposite the first surface, with diffusing (100) platinum or gold into the semiconductor substrate from one of the first and second surfaces of the semiconductor substrate, removing (102) platinum- or gold-comprising residues remaining on the one of the first and second surfaces after diffusing the platinum or gold, forming (104) a phosphorus- or boron-doped surface barrier layer on the first or second surface, and heating (105) the semiconductor substrate for local gettering of the platinum or gold by the phosphorus- or boron-doped surface barrier layer.

Abstract: A protective structure is produced by providing a semiconductor substrate with a doping of a first conductivity type. A semiconductor layer with a doping of a second conductivity type is applied at a surface of the semiconductor substrate. A buried layer with doping of a second conductivity type is formed in a first region of the semiconductor layer, wherein the buried layer is produced at the junction between the semiconductor layer and semiconductor substrate. A first dopant zone with a doping of a first conductivity type is formed in the first region of the semiconductor layer above the buried layer. A second dopant zone with a doping of a second conductivity type is formed in a second region of the semiconductor layer. An electrical insulation is formed between the first region and the second region of the semiconductor layer. A common connection device is formed for the first dopant zone and the second dopant zone.

Abstract: In one embodiment, an edge seal region of a semiconductor die is formed by forming a first dielectric layer on a surface of a semiconductor substrate near an edge of the semiconductor die and extending across into a scribe grid region of the semiconductor substrate. Another dielectric layer is formed overlying the first dielectric layer. An opening is formed through the first and second dielectric layers. The second dielectric layer is used as a mask for forming a doped region on the semiconductor substrate through the opening. A metal is formed that electrically contacts the doped region and an exterior edge of the first dielectric layer within the opening.