Abstract: A method of forming a semiconductor thin film includes the steps of: forming an amorphous semiconductor thin film on a substrate; partially forming a crystalline semiconductor thin film for each element region by irradiating laser light to the amorphous semiconductor thin film to selectively perform a heating treatment on the amorphous semiconductor thin film, and crystallizing an amorphous semiconductor thin film corresponding to an irradiation region; and inspecting crystallinity of the crystalline semiconductor thin film. The inspection step includes the steps of obtaining an optical step based on an optical phase difference between a crystallized region and an uncrystallized region by irradiating light to the crystalline semiconductor thin film and the amorphous semiconductor thin film, and evaluating one or both of sorting of the crystalline semiconductor thin film and control of crystallinity of the crystalline semiconductor thin film, based on the obtained optical step.

Abstract: In an apparatus and method for monitoring defects in wafers, a monitoring circuit is fabricated on an area of each one of the wafers. The monitoring circuit includes representative devices that replicate similar devices located in a die area of the wafers. Defects if present in the representative devices contribute to a generation of a noise, thereby causing an imbalance in a differential signal measurable across selected ones of the representative devices. A digitizing circuit that uses a common mode voltage as a reference to measure the imbalance digitizes the differential signal to a digital signal, the digital signal being indicative of the noise generated by the defects. The digital signal is stored over a configurable time interval to form a digital bit stream. The digital bit stream is compared to a reference to determine whether the defeats are within an allowable range.

Abstract: A quantitative evaluation device and method of an atomic vacancy, which are capable of efficiently and quantitatively evaluating an atomic vacancy existing in a silicon wafer. A quantitative evaluation device 1 is equipped with a detector 5 including an ultrasonic generator 27 and an ultrasonic receiver 28, a silicon sample 6 formed with the ultrasonic generator 27 and the ultrasonic receiver 28 on a silicon wafer 26 comprising perfect crystal silicon, a magnetic force generator 4 for applying an external magnetic field to the silicon sample 6, and a cooler 3 capable of cooling and controlling the silicon sample 6 to a range of temperatures lower than or equal to 50K.

Abstract: A laser scribing device is provided which comprises at least a laser light source. The laser light source may generate a laser beam for scribing cell lines to form a patterned solar cell module. Furthermore, the laser may emit a light beam for generating a light spot on the surface of the solar cell module. The light beam may be modulated compared with the light beam used for the scribing process. By means of the light spot a particular region of the active area of the solar cell module may be illuminated, and the voltage VOC (L) may be measured at a voltage measurement device. The voltage measurement device is connected between the negative contact area and the positive contact area of the solar cell module. The measured voltage VOC (L) depends on the location of the laser spot on the solar cell module and the intensity of the laser spot.

Abstract: A method of automatically reducing stacked vias while minimizing voltage drop in a power network of an integrated circuit (IC) is provided. In this method, any feasible (i.e. other than connectivity-necessary and uncongested stacked vias) stacked vias of the power network can be virtually removed. If a target voltage drop of the power network is exceeded, then a measurement of the severity of at least a maximum voltage drop on the IC can be updated. After this updating, a set of voltage drop improvement stacked vias can be virtually returned to the power network. The steps of determining whether the target voltage drop is exceeded, updating the severity of the voltage drop at one or more hot spots, and virtually returning the set of additional stacked vias can be repeated until the target voltage drop is not exceeded.

Abstract: By providing test features of increased thickness in a test structure for performing an x-ray diffraction measurement for evaluating the crystalline characteristics, such as the contents of germanium, an increased accuracy may be achieved, since the patterned SOI layer may be used as an efficient reference for the required data analysis.

Abstract: Methods for measuring thickness of an epitaxial layer of a wafer. An example method applies photoresist over the epitaxial layer, and then portions of the photoresist within a sacrificial region of the wafer are removed. Next, the epitaxial layer is isotropically etched through the removed portions of the photoresist until a portion of the silicon handle layer is exposed. The remaining photoresist layer is removed. Then, the silicon handle layer is anisotropically etched to form a well. Profile information of the epitaxial layer and the etched handle layer generated. Next, the thickness of the epitaxial layer is determined based on the profile information. The acceptability of the epitaxial layer may be determined based on the determined thickness of the epitaxial layer. If the epi layer is acceptable, then the geometry of devices that are to be etched into the epitaxial layer are determined based on the determined thickness.

Abstract: A method for patterning a substrate includes forming a material layer on the substrate; performing a first etching on the material layer to form a pattern; measuring the pattern of the material layer using an optical spectrum metrology tool; determining whether the measuring indicates that the etching step achieved a predefined result; and producing an etching recipe and performing a second etching of the material layer using the etching recipe if the predefined result was not achieved.

Abstract: A plasma of a gas containing an impurity is produced through a discharge in a vacuum chamber, and a plurality of substrates are successively doped with the impurity by using the plasma, wherein a plasma doping condition of a subject substrate is adjusted based on an accumulated discharge time until the subject substrate is placed in the vacuum chamber.

Abstract: A method of monitoring and testing electro-migration and time dependent dielectric breakdown includes forming an addressable wiring test array, which includes a plurality or horizontally disposed metal wiring and a plurality of segmented, vertically disposed probing wiring, performing a single row continuity/resistance check to determine which row of said metal wiring is open, performing a full serpentine continuity/resistance check, and determining a position of short defects.

Abstract: A low-temperature poly-crystalline thin film transistor in which amorphous silicon is crystallized using a laser crystallization method or a metal induced lateral crystallization method shows an unstable electrical property since crystallization is accomplished at a low temperature. When an electrical stress is applied to the low-temperature poly-crystalline thin film transistor and a lower substrate for a display device including the same, an electrical feature thereof is enhanced. To apply an electrical stress to the low-temperature poly-crystalline thin film transistor, the source of a thin film transistor is grounded, and a critical voltage which is determined according to a gate voltage applied between the drain and the source of the thin film transistor, at a state where any gate voltage has been applied between the gate and the source of the thin film transistor.

Abstract: A method and apparatus for applying a test signal to a node of a signal path of an integrated circuit using a parasitic capacitance of the integrated circuit associated with the node. For example, a parasitic capacitance associated with a bond pad may be used to apply a test signal to a signal path. Alternatively, a parasitic capacitance associated with a shielding element may be used to apply a test signal to the signal path.

Abstract: A method of measuring temperature across wafers during semiconductor processing includes the step of providing a correlation between a peak wafer temperature during a processing step and a change in wafer surface charge or surface potential following the processing step. A first wafer to be characterized for its peak temperature spatial distribution during the processing step is processed through the processing step. The wafer surface charge or surface potential at a plurality of locations on the first wafer are measured following the processing step. A peak temperature spatial distribution for the first wafer is then determined based on the correlation and the wafer surface charge or surface potential measured in the measuring step.

Abstract: A thin film panel is provided, which includes a first signal line and a second signal line crossing the first signal line and formed on a different layer from the first signal line. The second signal line includes an expansion having an enlarged area and at least one cutout, and is disposed adjacent to a crossing region where the second signal line crosses the first signal line.

Abstract: A testing method for a silicon interposer employs a test probe and an electrically conductive glass handler. The silicon interposer includes multiple interconnects that extend between the opposed major surfaces of the interposer, namely from a test side of the interposer to a conductive glass handler side of the interposer. On the glass handler side, the interposer includes a layer of patterned insulative resist with open regions at some interconnects on the glass handler side and remaining resist regions at other interconnects on the glass handler side. The interposer may include a conductive adhesive layer that couples together interconnects at the open regions on the glass handler side. In this manner, a probe may send a test signal from a first interconnect at one location on the test side of the interposer, through the first interconnect, through the conductive adhesive, through a second interconnect to another probe on the test side of the interposer.

Abstract: A light-emitting diode (LED) module and an LED packaging method. As the LED module is packaged under the consideration of candela distribution, each of the lead frames of the LED chips packaged in the LED module is bended for tilting the LED chips by different angles to exhibit various lighting effects. Meanwhile, in the LED packaging method, a plurality of LED chips can be loaded on board rapidly and aligned by one operation to result in less deviation in the candela distribution curve.

Abstract: A solution to an interference effect problem associated with laser processing of target structures entails adjusting laser pulse energy or other laser beam parameter, such as laser pulse temporal shape, based on light reflection information of the target structure and passivation layers stacked across a wafer surface or among multiple wafers in a group of wafers. Laser beam reflection measurements on a target link measurement structure and in a neighboring passivation layer area unoccupied by a link enable calculation of the laser pulse energy adjustment for a more consistent processing result without causing damage to the wafer. For thin film trimming on a wafer, similar reflection measurement information of the laser beam incident on the thin film structure and the passivation layer structure with no thin film present can also deliver the needed information for laser parameter selection to ensure better processing quality.

Abstract: A test structure and a method for fabricating the same are disclosed. The test structure includes a plurality of sampling lines over a substrate located between a plurality of a first grounding lines and a plurality of a second grounding lines. The sampling lines are selectively electrically coupled to the first grounding line or the second grounding line and include at least one programmed defect. A double-patterning fabricating approach is utilized to produce such test structure which may be applied to a charged particle beam such as an electron-beam defect inspection system.

Abstract: A method of manufacturing a semiconductor device includes placing a sample of a liquid chemical containing a contaminant on a substantially impurity-free surface of a substrate. The liquid chemical is evaporated, leaving the contaminant on the surface. The contaminant is concentrated in a scanning solution, which is then evaporated to form a residue. A concentration of the contaminant in the residue is determined.

Abstract: A method for screening silicon-based wafers used in the photovoltaic industry is provided herewith.

Abstract: A semiconductor manufacturing apparatus and substrate processing method includes a step of acquiring a measurement value based on a first detecting and a second detecting section and determining a first difference of measurement values between the first detecting section and the second detecting section, comparing between a previously stored second difference between measurement values concerning the first detecting section and the second detecting section, calculating a correction value for a pressure in a cooling-gas passage provided between a process chamber and a heating device depending upon the first difference when the first difference is different from the second difference, and correcting the pressure value based on the pressure correction value, and a step of processing the substrate by flowing a cooling gas through the cooling-gas passage while heating the process chamber, and placing the heating device and the cooling device under a control section depending upon a pressure value corrected.

Abstract: A system is provided for using test structures to evaluate a fabrication of a wafer. The test structures include a combination of device and interconnect elements that are provided on an active region of a die, on the wafer prior to the fabrication of the wafer being completed. The combination of device and interconnect elements include one or more circuits that are activatable to produce an output corresponding to measurable electrical and/or optical characteristics. A power receiving element that is configured to receive activation energy sufficient to cause the output on a contactless medium, so that the activation energy is received without affecting a usability of the die or wafer. The one or more circuits are structured to generate a variation in either the output or in a parameter determined from output, as a result of a process variation in a specific fabrication step that provided elements for forming the one or more circuits.

Abstract: An apparatus for monitoring the thickness of a conductive layer on a substrate includes a support to hold a substrate having a conductive layer, an eddy current monitoring system including a first plurality of core portions, and a motor to cause relative motion between the support and the eddy current monitoring system such that the substrate moves across the first plurality of core portions in a direction that defines a first axis. At least one core portion is positioned further from a second axis than at least two other core portions. The second axis is orthogonal to the first axis.

Abstract: A semiconductor device includes: a semiconductor chip; a package for accommodating the chip, wherein the package has a box shape with an opening and a bottom; and a cover for sealing the opening of the package. The semiconductor chip is disposed on the bottom of the package. The cover has a plate shape. The cover includes a protrusion, which is disposed at a center of the plate shape. The protrusion protrudes toward an outside of the package.

Abstract: It is an object of the present invention to provide a doping apparatus, a doping method, and a method for fabricating a thin film transistor that can carry out doping to the carrier concentration which is optimum for obtaining the desired electric characteristic non-destructively and in an easy manner. In accordance with the present invention, an electric characteristic of a semiconductor element (threshold voltage in a transistor and the like) is correctly and precisely monitored by using a contact angle, and is controlled by controlling a doping method. In addition, the present invention can be momentarily acquired information by in-situ monitoring the characteristic and can be fed back without a time lag.

Abstract: Test methods and components are disclosed for testing the quality of lift-off processes in wafer fabrication. A wafer is populated with one or more test components along with the functional components. These test components are fabricated with holes in an insulation layer that is deposited between conductive layers, where the holes were created by the same or similar lift-off process that is used to fabricate the functional components on the wafer. The test components may then be measured in order to determine the quality of the holes created by the lift-off process. The quality of the lift-off process used to fabricate the functional components may then be determined based on the quality of the holes in the test components.

Abstract: A method for forming a contact hole in a semiconductor device and related computer-readable storage medium are provided, the method and program steps of the medium including measuring a percentage of oxygen in an etching chamber, and controlling the percentage of oxygen in the etching chamber to enlarge a temporary inner diameter near a top of the contact hole.

Abstract: Inspection methods. A method includes adhering an optical blocking layer directly onto and in direct mechanical contact with a semiconductor process wafer, the blocking layer being substantially opaque to a range of wavelengths of light; applying at least one layer over the blocking layer; and inspecting optically at least one wavelength at least one inspection area, the blocking layer extending substantially throughout the inspection area. An inspection method including adhering an optical absorbing layer to a semiconductor process wafer, where the absorbing layer is configured to substantially absorb a range of wavelengths of light; applying at least one layer over the absorbing layer; and inspecting optically at least one wavelength at least one inspection area of the process wafer. A manufacturing method including ascertaining if a defect is present within a photoresist layer, and changing a semiconductor manufacturing process to prevent the defect, if the defect is present.

Abstract: Digital trimming logic is included in a microelectronic device of a type that produces an output signal in response to an input signal and a threshold signal. Trimming logic values are produced in response to a clock signal that is applied to the device in a trimming mode. The clock signal can be applied to a device pin that is used in normal operation to provide an output signal, thus allowing the pin to serve a dual function. The trimming logic changes the trimming logic value in response to the clock signal until the trimming logic value reaches a trim value at which the threshold signal is substantially equal to the input signal. The trimming logic then stores the trim value in a non-volatile memory and enters a locked mode in which further trimming is prevented and the device is ready for normal operation.

Abstract: A method for manufacturing an optical device, the method includes the steps of: forming a multilayer film, including forming a first mirror above a substrate, forming an active layer above the first mirror, forming a second mirror above the active layer, forming a semiconductor layer on the second mirror, and forming a sacrificial layer on the semiconductor layer; conducting a reflection coefficient examination on the multilayer film; patterning the multilayer film to form a surface-emitting laser section having the first mirror, the active layer and the second mirror, and a diode section having the semiconductor layer; and removing at least a portion of the sacrificial layer to expose at least a portion of an upper surface of the semiconductor layer, wherein an optical film thickness of the semiconductor layer is formed to be an odd multiple or an even multiple of ?/4, where ? is a design wavelength of light emitted by the surface-emitting laser section, and an optical film thickness of the sacrificial layer

Abstract: The semiconductor device according to an aspect of the invention includes: an internal circuit area having an internal circuit; an I/O circuit area positioned outside the internal circuit area; and an electrode pad placed across an outer edge of the I/O circuit area. In the electrode pad, an area outside the outer edge of the I/O circuit area is a bonding area, and an area inside the outer edge is a probe area.

Abstract: Methods of conducting wafer level burn-in (WLBI) of semiconductor devices are presented wherein systems are provided having at least two electrodes (210, 215). Electrical bias (920) and/or thermal power (925) is applied on each side of a wafer (100) having back and front electrical contacts for semiconductor devices borne by the wafer. A pliable conductive layer (910) is described for supplying pins on the device side of a wafer with electrical contact and/or also for providing protection to the wafer from mechanical pressure being applied to its surfaces. Use of a cooling system (950) is also described for enabling the application of a uniform temperature to a wafer undergoing burn-in.

Abstract: Disclosed are embodiments of a wafer that incorporates fill structures with varying configurations to provide uniform reflectance. Uniform reflectance is achieved by distributing across the wafer fill structures having different semiconductor materials such that approximately the same ratio and density between the different semiconductor materials is achieved within each region and, optimally, each sub-region. Alternatively, it is achieved by distributing across the wafer fill structures, including one or more hybrid fill structure containing varying proportions of different semiconductor materials, such that approximately the same ratio between the different semiconductor materials is achieved within each region and, optimally, each sub-region.

Abstract: There is provided a method for dimension profiling of a semiconductor device. The method involves incorporating a feature comprising a detectable element into the device, and thereafter detecting the detectable element to determine a dimension of the feature. This information can be used for the determination of a dimension of buried channels, and also for end-point detection of CMP processes.

Abstract: A structure and a method for operating the same. The method includes providing a detecting structure which includes N detectors. N is a positive integer. A fabrication step is simultaneously performed on the detecting structure and M product structures in a fabrication tool resulting in a particle-emitting layer on the detecting structure. The detecting structure is different than the M product structures. The M product structures are identical. M is a positive integer. An impact of emitting particles from the particle-emitting layer on the detecting structure is analyzed after said performing is performed.

Abstract: An encapsulated calorimetric flow meter according to the present invention comprises an integrated circuit (104) mounted on a lead frame (102). The integrated circuit has a channel (105) provided in its lower face, the channel being aligned with two holes (103) provided in the lead frame, the holes coinciding with the ends of the channel (105). There are further slots (111) in the lead frame (102) alongside the integrated circuit to thermally isolate it from the rest of the lead frame (102), which acts as a heat sink to keep the entry and exit fluid at ambient temperature. The flow meter is manufactured by mounting the integrated circuit (104) on to a suitable lead frame (102). The assembly of integrated circuit (104) and lead frame (102) is then inverted and blobs of gel (112, 114) are then deposited onto the lead frame (102) covering the holes (103). The assembly is then inserted into a mould (100) and encapsulated within a suitable mould compound.

Abstract: Exemplary embodiments provide methods and systems for assembling electronic devices, such as integrated circuit (IC) chips, using a release member having a phase change material. Specifically, IC elements/components can be selectively received, stored, inspected, repaired, and/or released in a scalable manner during the assembly of IC chips by inducing phase change of the phase change material. The release member can be flexible or rigid. In some embodiments, the release member can be used for a low cost placement of the IC elements in combination with an SOI (silicon on insulator) wafer and/or an intermediate transfer member. In other embodiments, the release member can be used for a low cost placement of the IC elements in combination with a release wafer.

Abstract: A structure is disclosed for measuring body pinch resistance Rp of trench MOSFET arrays on a wafer. The trench MOSFET array has a common drain layer of first conductivity type and a 2D-trench MOSFET array atop the common drain layer. The 2D-trench MOSFET array has an interdigitated array of source-body columns and gate trench columns. Each source-body column has a bottom body region of second conductivity type with up-extending finger structures. Each source-body column has top source regions of first conductivity type bridging the finger structures. The structure includes: a) A source-body column wherein each finger structure of the bottom body region has a formed top contact electrode. b) Two gate trench columns flank the source-body column and both have a formed top common gate contact electrode. Upon connection of the structure to external voltage/current measurement devices, Rp can be measured while mimicking the parasitic effect of neighboring trench MOSFETs.

Abstract: One embodiment of the present invention is directed to an under bump metallurgy material. The under bump metallurgy material of this embodiment includes an adhesion layer and a conduction layer formed on top of the adhesion layer. The under bump metallurgy material of this embodiment also includes a barrier layer plated on top of the conduction layer and a sacrificial layer plated on top of the barrier layer. The conduction layer of this embodiment includes a trench formed therein, the trench contacting a portion of the barrier layer and blocking a path of intermetallic formation between the conduction layer and the sacrificial layer.

Abstract: A method for manufacturing a capacitive semiconductor sensor includes: forming a plurality of circuit chips in a wafer, wherein each circuit chip includes a pad for testing a sensor chip; bonding the sensor chip on each circuit chip with a bump so that the sensor chip is electrically coupled with the circuit chip, wherein each sensor chip is made of semiconductor and has a capacitance changing portion, which is disposed on one side of the sensor chip and has a variable capacitance, wherein the circuit chip detects a capacitance change of the sensor chip, and wherein the one side of the sensor chip faces the circuit chip; testing each sensor chip through the pad; and cutting the wafer into individual circuit chips so that the circuit chip and the sensor chip provide the capacitive semiconductor sensor.

Abstract: A semiconductor chip and methods for forming the same. The semiconductor chip includes M regular solder bump structures and N monitor solder bump structures, M and N being positive integers. If a flip chip process is performed for the semiconductor chip, then the N monitor solder bump structures are more sensitive to a cool-down stress than the M regular solder bump structures. The cool-down stress results from a cool-down step of the flip chip process. Each of the M regular solder bump structures is electrically connected to either a power supply or a device of the semiconductor chip. Each of the N monitor solder bump structures is not electrically connected to a power supply or a device of the semiconductor chip.

Abstract: A robust, stand-alone load cell comprises a block of aligned carbon nanotubes with parallel electrodes on opposing sides of the block and an electrical circuit connected between the electrodes for measuring the electrical resistance of the block. The nanotubes are preferably aligned perpendicular to the electrodes. Carbon nanotube-based load cells may be incorporated into a wafer asssembly for characterizing semiconductor processing equipment. Such a wafer assembly includes two parallel wafers with a plurality of carbon nanotube load cells positioned between and attached to both wafers. The load cells are independently electrically connected to a device which monitors and records the resistivity of the load cell.

Abstract: A substrate processing apparatus for executing a predetermined process on a substrate loaded into a process chamber by running a recipe containing a plurality of steps is provided. The recipe includes a process step of processing the substrate, and a leak check step executed before the process step to check whether a leak occurs inside the process chamber, and the substrate processing apparatus includes a main control unit configured to execute the process step while keeping an error that occurs in the leak check step.

Abstract: A method for manufacturing a semiconductor device, includes: preparing a semiconductor module including: a semiconductor substrate having an electrode; a test pad electrically connected to the electrode; a land electrically connected to the test pad; and an external terminal provided on the land; and testing an electrical characteristic by bringing a probe into contact with the test pad.

Abstract: A substrate inspection method allowing inspection of all a plurality of substrates each provided at its surface with a plurality of layers by determining quality of the plurality of layers as well as methods of manufacturing the substrate and an element using the substrate inspection method are provided. The substrate inspection method includes a step of preparing the substrate provided at its main surface with the plurality of layers, a film forming step, a local etching step, and an inspection step or a composition analysis step. In the step, a concavity is formed in a region provided with an epitaxial layer of the main surface of the substrate by removing at least partially the epitaxial layer. In the inspection step, the inspection is performed on the layer exposed in the concavity.

Abstract: The present invention relates to a method of manufacturing a carbon nanotube transistor in which a carbon nanotube channel is formed between a source electrode and a drain electrode and a gate electrode is formed at one side of the carbon nanotube channel, the method comprising the steps of: (a) forming the carbon nanotube channel on a substrate; (b) electrically connecting the source electrode and the drain electrode to both ends of the carbon nanotube channel, respectively; and (c) applying a stress voltage across the source electrode and the drain electrode to remove metallicity of the carbon nanotube channel. According to the method of manufacturing a carbon nanotube transistor of the present invention, a metallic part can be selectively removed from a carbon nanotube which is used as a channel of a transistor and has metallic properties and semiconductor properties mixed with each other.

Abstract: An integrated circuit (IC) includes at least a first complementary MOS (CMOS) circuit, the first CMOS circuit comprising one or more first n-channel MOS (NMOS) transistors and one or more first p-channel MOS (PMOS) transistors, where the first NMOS transistors and the first PMOS transistors are arranged in the first CMOS circuit to drive at least a first common node of the first CMOS circuit. An average of the effective gate channel lengths of the first NMOS transistors (first NMOS average length) is at least 2% greater than an average of the effective gate channel lengths of the first PMOS transistors (first PMOS average length).

Abstract: A burn-in input signal input to a burn-in circuit is delivered to an internal circuit through a selector. In response to a control signal from the burn-in circuit, the selector selects either the burn-in input signal or an input signal for operating the internal circuit. In the burn-in test process, a portion of an output signal is monitored to determine the degree of degradation of the internal circuit.

Abstract: The invention provides a plasma processing method capable of reducing the damage applied to the low-k film or the underlayer.

Abstract: In a method for producing semiconductor components, in which chips are structured, tested, and isolated into dies on a wafer, in the event of a wafer being broken during the method, undamaged chips of a fragment of the wafer delimited by at least one edge section and at least one fracture contour are processed further as usual. The method has the result that the yield of usable chips is significantly increased in relation to the discarding and disposal of broken wafers provided in the prior art. The average production costs of electronic components and the loss of valuable semiconductor materials and the costs for the disposal of the fragments viewed as discards up to this point are thus significantly reduced.