Abstract: Various embodiments include apparatus and method having a heat source, a thermal management device, and an interface disposed between the thermal management device and the heat source. The interface includes nanostructures to facilitate heat transfer and adhesion between the heat source and the thermal management device.

Abstract: A device and method are provided for detecting stress migration properties of a semiconductor module mounted in a housing. A stress migration test (SMT) structure is formed in the semiconductor module. An integrated heating (IH) device is formed within or in direct proximity to the SMT structure. The SMT structure includes a first interconnect region in a first interconnect layer, a second interconnect region in a second interconnect layer, and a connecting region electrically connecting the interconnect regions through a first insulating layer. The IH device includes a heating interconnect region through which a heating current flows. The heating interconnect region is within or outside the first or second interconnect region or connecting region. When the heating current is applied, a measurement voltage is applied to the SMT structure, and a current through the SMT structure is measured to detect stress migration properties of the semiconductor module.

Abstract: A non-volatile memory is provided. The non-volatile memory comprises at least a silicon-on-insulator transistor including a substrate; an insulating layer disposed on the substrate; an active region disposed on the insulating layer; and an energy barrier device disposed in the active region and outputting a relatively small current when the non-volatile memory is read.

Abstract: A substrate processing apparatus, a method of manufacturing a semiconductor device, and a method of confirming an operation of a liquid flowrate control device are provided. The substrate processing apparatus comprises: a process chamber accommodating a substrate; a liquid source supply system supplying a liquid source into the process chamber; a solvent supply system supplying a solvent having a vapor pressure greater than that of the liquid source into the process chamber; a liquid flowrate control device controlling flowrates of the liquid source and the solvent; and a controller controlling the liquid source supply system, the solvent supply system, and the liquid flowrate control device so that the solvent is supplied into the liquid flowrate control device than the solvent supply system to confirm an operation of the liquid flowrate control device before the liquid source supply system supplies the liquid source into the process chamber.

Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; a plurality of material layers formed on the semiconductor substrate, each of the material layers including a circuit pattern therein; and a plurality of diffraction-based periodic marks formed in the plurality of material layers and stacked in a same region. One of the diffraction-based periodic marks is different from at least one other of the diffraction-based periodic marks in pitch.

Abstract: In the resin film evaluation method and method for manufacturing a semiconductor device applying the resin film evaluation method of the present invention, first, a substrate having a resin film formed on an insulating film with an opening in which the surface of the insulating film is exposed is irradiated with charged energetic particles. Then, the surface potentials of the substrate surface irradiated with charged energetic particles are measured. Based on the measurements, the difference in surface potential between the resin film and the insulating film exposed in the opening is obtained. Based on the difference in surface potential, a physical quantity such as the resin film residue count obtained after a given treatment is predicted. In this way, the degenerated layer formed on the surface of a resin film due to charged energetic particles such as implantation ions can be evaluated in a simple and highly accurate manner.

Abstract: Aspects of the present invention relate to the arrangement of points of interconnection of integrated circuit die to the package in which they are enclosed. More specifically, aspects of the present invention pertain to an arrangement of bond pads over the active circuitry of an integrated circuit die, in order to permit a reduction in size of the die. An embodiment of the present invention may place a first bond pad over the active area of an integrated circuit, wherein the first bond pad is electrically coupled to a second bond pad outside of the active area of the integrated circuit. Production and delivery of the integrated circuit may proceed using the second bond pad during packaging, in parallel with the testing of packaging using the first bond pad. When processes related to the use of the first bond pad have been proven successful and sustainable, the second bond pad may be eliminated, resulting in a reduction of the size of the integrated circuit device.

Abstract: A rubbing system for an alignment layer of a liquid crystal display (LCD) device, comprises: a rubbing table on which a substrate having an alignment layer thereon is positioned; a rubbing roll on which a rubbing material is wound, substantially positioned on the rubbing table thus to substantially contact the alignment layer, for rubbing the alignment layer by rotation of the rubbing roll; and a controlling unit for controlling the alignment layer to be rubbed by substantially contacting the rubbing roll onto the alignment layer by simultaneously lifting and lowering a rubbing table and the rubbing roll according to an alignment controlling force to be applied to the alignment layer.

Abstract: A semiconductor die includes proximity connectors proximate to a surface of the semiconductor die. This semiconductor die is configured to communicate signals with another semiconductor die via proximity communication through one or more of the proximity connectors. In particular, the proximity connectors include a first group of proximity connectors that is configured to facilitate determining a first separation between the semiconductor die and the other semiconductor die by comparing coupling capacitances between the semiconductor die and the other semiconductor die. Note that the first group of proximity connectors includes a first proximity connector and a second proximity connector, and the second proximity connector at least partially encloses an in-plane outer edge of the first proximity connector.

Abstract: In step S103, a gallium nitride semiconductor layer 13 is grown on an n-type GaN substrate 11. In step S104, a PL spectrum for the gallium nitride based semiconductor layer in a wavelength region including the yellow band of wavelength and the band edge wavelength of the gallium nitride based semiconductor is measured at room temperature. In step S106, a screened epitaxial substrate E1 is prepared through selection based on comparison of the photoluminescence spectrum intensity in the yellow band of wavelength and the band edge wavelength with a reference value. In step S107, an electrode 15 for an electron device is formed on the screened epitaxial substrate 13.

Abstract: Structures and methods are disclosed for evaluating the effect of a process environment variation. A structure and related method are disclosed including a plurality of electrical structures arranged in a non-collinear fashion for determining a magnitude and direction of a process environment variation in the vicinity of the plurality of electrical structures. The plurality of structures may include a first polarity FET coupled to a second polarity FET, each of the first polarity FET and the second polarity FET are coupled to a first pad and a second pad such that the structure allows independent measurement of the first polarity FET and the second polarity FET using only the first and second pads. Alternatively, the electrical structures may include resistors, diodes or ring oscillators. Appropriate measurements of each electrical structure allow a gradient field including a magnitude and direction of the effect of a process environment variation to be determined.

Abstract: The invention provides a method for manufacturing an integrated circuit. The method, in one embodiment, includes inspecting a semiconductor wafer including a plurality of die for a defect, the inspecting providing an image of the semiconductor wafer including the defect. The method further includes identifying an area of the semiconductor wafer from the image, wherein the identified area encompasses at least those die including any portion of the defect, and dicing the semiconductor wafer into individual die. The die defined by the identified area, in this embodiment, are then discarded.

Abstract: The present disclosure provides a semiconductor manufacturing method. The method includes performing a first process to a wafer; measuring the wafer for wafer data after the first process; securing the wafer on an E-chuck in a processing chamber; collecting sensor data from a sensor embedded in the E-chuck; adjusting clamping forces to the E-chuck based on the wafer data and the sensor data; and thereafter performing a second process to the wafer secured on the E-chuck in the processing chamber.

Abstract: A test element group for monitoring leakage current in a semiconductor device and a method of manufacturing the same are disclosed. The test element group for monitoring leakage current in a semiconductor device includes device isolation layers formed over a first conductivity type semiconductor substrate. A second conductivity type well may be formed over the first conductivity type semiconductor substrate. First conductivity type impurity regions may be formed in first active areas between the device isolation layers in the second conductivity type well. Monitoring contacts may be formed within the first active areas to monitor leakage current, using layout data such that a distance from each of the monitoring contacts to a border of each of the first active areas is set to have an allowable minimum value under a predetermined design rule.

Abstract: Semiconductor device test structures and methods are disclosed. In a preferred embodiment, a test structure includes a feed line, a stress line disposed proximate the feed line, and a conductive feature disposed between the stress line and the feed line. The test structure includes a temperature adjuster proximate at least the conductive feature, and at least one feedback device coupled to the temperature adjuster and at least the conductive feature.

Abstract: Rotating contact elements and methods of fabrication are provided herein. In one embodiment, a rotating contact element includes a tip having a first side configured to contact a device to be tested and an opposing second side; and a plurality of deformed members extending from the second side of the tip and arranged about a central axis thereof, wherein the tip rotates substantially about the central axis upon compression of the plurality of deformed members.

Abstract: Provided is a defect correcting device for an electronic circuit pattern, which is capable of making a defect seed obvious, and normalizing a pixel or forming a pixel into a semi-black spot. A defect correcting device for an electronic circuit pattern includes: an imaging unit for irradiating a defective portion of the electronic circuit pattern with irradiation light having a wavelength of a visible light region and a wavelength of an infrared light region, and receiving reflected light having the wavelength of the visible light region and the wavelength of the infrared light region from the electronic circuit pattern; a signal processing unit for extracting the defective portion from a picked-up image, and determining a correcting method; a laser irradiating unit for irradiating the defective portion with laser light; and a correction determining unit for determining success or failure of defect correction before and after laser irradiation.

Abstract: The total film thickness T1N of silicon oxynitride film and silicon oxide film remaining as its underlying layer is measured. A measurement target substrate is re-oxidized, and, after the re-oxidization, the total film thickness (T2N) of the silicon oxynitride film, silicon oxide film and silicon oxide film resulting from the re-oxidization on the target substrate is measured. Separately, a reference substrate provided with silicon oxide film is re-oxidized, and, after the re-oxidization, the total film thickness T2 of the silicon oxide film and silicon oxide film resulting from the re-oxidization on the reference substrate is measured. Re-oxidization rate reduction ratio RORR of the measurement target substrate is calculated by the following formula (1) from the values of total film thicknesses T1N, T2N and T2. The nitrogen concentration of the silicon oxynitride film of the target substrate is determined from the calculated re-oxidization rate reduction ratio RORR. RORR (%)={(T2?T2N)/(T2?T1N)}×100 (1).

Abstract: A device and method for configuring a semiconductor circuit having at least two identical or similar functional units, the faulty unit being identified and deactivated if an error occurs in at least one of the identical or similar functional units.

Abstract: A semi-adaptive voltage scaling method and device for determining minimal supply voltages for digital electronic semiconductor circuitry, e.g., microprocessors, of electronic devices under production testing and “real” operating conditions. The SAVS operates in a closed-loop during a production test phase of the circuitry and in an open-loop mode in an application (operation) phase of the semiconductor circuitry. During production testing, a lowermost level of the supply voltage for the semiconductor circuitry is determined at one single defined temperature at which operating specifications of the circuit are met. The lowermost level is stored in a dedicated electronic memory of the circuitry together with temperature dependent parameters. Afterwards, when the digital electronic circuitry is operated in a “real” application, e.g.

Abstract: A semiconductor device includes at least one first type of pad and at least one second type of pad having a different area from the first type of pad. A pad connection unit electrically couples the at least one second type of pad to an integrated circuit of the semiconductor device during a test mode, and disconnects the at least one second type of pad from the integrated circuit during a normal operating mode.

Abstract: A semiconductor manufacturing apparatus includes a processing unit for processing at least one wafer; a loading/unloading unit for loading/unloading at least wafer; an input/output chamber for taking in a processed wafer from the processing unit and taking out the processed wafer to the loading/unloading unit, and taking in a unprocessed wafer from the loading/unloading unit and taking out the unprocessed wafer to the reaction unit; and a wafer inspection device for inspecting the processed wafer through a light transmittable top portion of the input/output chamber, through which light is transmittable, while the processed wafer is temporarily placed in the input/output chamber.

Abstract: A semiconductor structure including a substrate, a gate dielectric layer, a gate, a source region and a drain region is provided. The gate dielectric layer is disposed on the substrate. At least one recess is disposed in the substrate. The gate is disposed on the gate dielectric layer and in the recess. The source and drain regions are respectively disposed in the substrate beside the gate.

Abstract: The present invention relates to a monitor cell (200) for monitoring local variations in a process parameter of an integrated circuit. The monitor cell (200) comprises a first delay path (220) located in a first area (100, 110, 120) of the integrated circuit and a second delay path (230) located in a second area (100, 110, 120) of the integrated circuit. The first delay path (220) is faster than the second delay path (230) when the difference in the respective process parameter values of the first area and the second area is smaller than a predefined threshold. In contrast, the second delay path (230) is faster than the first delay path (220) when said difference is larger than the predefined threshold. The monitor cell further comprises an input (210) arranged to provide the first delay path (220) and the second delay path (230) with a test signal (260) and a signal detector (240) for detecting the order in which the delay paths (210; 220) output the test signal (260).

Abstract: Provided is a normally-off field effect transistor using a III-nitride semiconductor. The transistor is provided with a III-nitride semiconductor layer grown on a substrate by including an acceptor and a donor; a gate insulating film which is formed on the III-nitride semiconductor layer to have a thickness to be at a prescribed threshold voltage based on the concentration of the acceptor and that of the donor; a gate electrode formed on the gate insulating film; a first source/drain electrode formed on the III-nitride semiconductor layer to one side of and separate from the gate electrode, directly or via a high dopant concentration region; and a second source/drain electrode formed away from the gate electrode and the first source/drain electrode, on or under the III-nitride semiconductor layer, directly or via a high dopant concentration region.

Abstract: The present disclosure provides a method for manufacturing integrated circuit devices including an electron beam inspection. The method includes forming a silicide region on a substrate. In an embodiment, the silicide region is formed to provide contact to a device feature such as a source or drain region. An electron beam scan is then performed on the substrate. The electron beam scan includes a first scan and a second scan. The first scan includes a lower landing energy than the second scan. In an embodiment, the first scan provides a dark silicide image analysis and a bright image analysis. In an embodiment, the second scan provides a dark silicide image analysis. The method continues to form a conductive plug after performing the electron beam scan.

Abstract: A method of manufacturing a substrate formed with a plurality of wiring patterns on a base, includes: a first inspection step of identifying a faulty wiring pattern having electric short circuit or disconnection by performing an electric inspection respectively for the plurality of wiring patterns; a second inspection step of examining a relative position of a defect on the base and at least one of a type and a size of the defect by an optical inspection; a matching step of matching a result of the first inspection step with a result of the second inspection step, and identifying a critical defect having electric short circuit or disconnection; and a third inspection step of examining a relative position in a pixel and an effective range of the critical defect by an optical inspection.

Abstract: A process is provided for determining the effects of scattering from the edge of a resist during a doping process. Edges of a resist which has been patterned to create an n-well are simulated and individually stepped across a predetermined region in predetermined step sizes. The step sizes may vary from step to step after each step, the scattering effects due to the resist edge at its particular location is determined. A resist of virtually any shape may be divided into its component edges and each edge may be individually stepped during the process.

Abstract: A burn-in method includes applying a stress current for applying thermal stress to a surface-emitting semiconductor laser, measuring an operation characteristic of the surface-emitting semiconductor laser to which the stress current is applied, and making a pass/fail decision on the surface-emitting semiconductor laser on the basis of the operation characteristic measured.

Abstract: An integrated circuit device is disclosed that includes a dual stress liner NMOS device having a tensile stress layer that overlies a NMOS gate film stack, a dual stress liner PMOS device having a compressive stress layer that overlies a PMOS gate film stack, a reduced-stress dual stress liner NMOS device having a stress reduction layer that extends between the tensile stress layer and the NMOS gate film stack, and a reduced-stress dual stress liner PMOS device having a stress reduction layer that extends between the compressive stress layer and the PMOS gate film stack. In embodiments of the invention additional reduced-stress dual stress liner NMOS devices and reduced-stress PMOS devices are formed by altering the thickness and/or the material properties of the stress reduction layer.

Abstract: A method of manufacturing a reference sample substrate for analyzing a metal contamination level includes coating an organic silica solution including metal impurities on a semiconductor substrate and forming an oxide layer on the semiconductor substrate by thermally treating the semiconductor substrate having the coated organic silica solution. The metal impurities are substantially uniformly distributed in the oxide layer and the metal impurities are positioned at predetermined portions of the oxide layer.

Abstract: A system for testing and a method for making a semiconductor device is disclosed. A preferred embodiment includes a conductor overlying a dielectric layer. The conductor is coupled to a first test pad via a first conducting line and to a second test pad via a second conducting line.

Abstract: When scribing a substrate, the precise location of the outer peripheral edge of the substrate on a stage is determined and movement of a scribe tool is controlled to first bring the scribe tool into engagement with the substrate at a location inwardly of the outer peripheral edge of the substrate. After a downwardly directed force of predetermined magnitude exerted by the scribe tool has been attained and stabilized, the scribe tool is moved along the substrate to form a scribe line.

Abstract: A method for protecting a semiconductor device is disclosed that can improve reliability of a performance test for the semiconductor device and prevent damage to the semiconductor device during transportation or packaging for shipment. An IC cover is attached to the semiconductor device, which has height unevenness because it includes semiconductor chips and electric parts having different heights. The IC cover includes projecting portions and a base portion. After being attached to the semiconductor device, the projecting portions stand in a free area in the semiconductor device, and the base portion is supported by the projections to be separated from the semiconductor chips and electric parts in the semiconductor device. The IC cover is detachably attached to the semiconductor device.

Abstract: Testing a non volatile memory by exposing the non volatile memory to particle radiation (e.g. xenon ions) to emulate memory cell damage due to data state changing events of a non volatile memory cell. After the exposing, the memory cells are subjected to tests and the results of the tests are used to develop reliability indications of the non volatile memory. Integrated circuits with non volatile memories of the same design are provided. Reliability representations of the integrated circuits can be made with respect to a number of data state charging events based on the exposure and subsequent tests.

Abstract: The present invention is directed to permitting a wiring material to be reused in a repair work so as to achieve productivity improvement and cost reduction.

Abstract: An integrated component includes a semiconductor substrate; at least one interconnect applied on the semiconductor substrate; an insulating layer applied on the at least one interconnect; and at least one opening through the insulating layer which interrupts the at least one interconnect into a first section and a second section.

Abstract: Disclosed herein are mono-functional silylating compounds that may exhibit enhanced silylating capabilities. Also disclosed are method of synthesizing and using these compounds. Finally methods to determine effective silylation are also disclosed.

Abstract: Spin-transfer torque memory having a compensation element is disclosed. A spin-transfer torque memory unit includes a free magnetic layer having a magnetic easy axis and a magnetization orientation that can change direction due to spin-torque transfer when a write current passes through the spin-transfer torque memory unit; a reference magnetic element having a magnetization orientation that is pinned in a reference direction; an electrically insulating and non-magnetic tunneling barrier layer separating the free magnetic layer from the magnetic reference element; and a compensation element adjacent to the free magnetic layer. The compensation element applies a bias field on the magnetization orientation of the free magnetic layer. The bias field is formed of a first vector component parallel to the easy axis of the free magnetic layer and a second vector component orthogonal to the easy axis of the free magnetic layer.

Abstract: A sensor for selectively determining the presence and measuring the amount of hydrogen in the vicinity of the sensor. The sensor comprises a MEMS device coated with a nanostructured thin film of indium oxide doped tin oxide with an over layer of nanostructured barium cerate with platinum catalyst nanoparticles. Initial exposure to a UV light source, at room temperature, causes burning of organic residues present on the sensor surface and provides a clean surface for sensing hydrogen at room temperature. A giant room temperature hydrogen sensitivity is observed after making the UV source off. The hydrogen sensor of the invention can be usefully employed for the detection of hydrogen in an environment susceptible to the incursion or generation of hydrogen and may be conveniently used at room temperature.

Abstract: Methods and apparatus may operate to position a sample, including an imager lens surface, within a processing chamber. Further activities may include creating a layer of reactive material in proximity with the imager lens surface, and exciting a portion of the layer of reactive material in proximity with the imager lens surface to form chemical radicals. Additional activities may include removing a portion of the material in proximity to the excited portion of the imager lens surface to a predetermined level, and continuing the creating, exciting and removing actions until at least one of a plurality of stop criteria occurs.

Abstract: A semiconductor process test structure comprises an electrode, a charge-trapping layer, and a diffusion region. The test structure is a capacitor-like structure in which the charge-trapping layer will trap charges during various processing steps. Gate-induced drain leakage (GIDL) measurement techniques can then be used to characterize the charging status of the test structure.

Abstract: The present invention relates to dielectric actuators or sensors of the kind wherein electrostatic attraction between two electrodes located on an elastomeric body leads to a compression of the body in a first direction and a corresponding extension of the body in a second direction. The dielectric actuator/sensor structure comprises a first sheet of elastomeric material having at least one smooth surface and a second surface and a second sheet of elastomeric material having at least one smooth surface and a second surface. The sheets are laminated together with their second surfaces exposed, and there is provided a first electrode on the second surface of the first sheet and second electrode on the second surface of the second sheet.

Abstract: A test circuit for, and method of, determining electrical properties of an underlying interconnect layer and an overlying interconnect layer of an integrated circuit (IC) and an IC incorporating the test circuit or the method. In one embodiment, the test circuit includes a gate chain having a ring path and a stage. In one embodiment, the stage includes: (1) a underlying test segment in the underlying interconnect layer, (2) a overlying test segment in the overlying interconnect layer and (3) logic circuitry activatible after formation of the underlying interconnect layer and before formation of the overlying interconnect layer to place the underlying test segment in the ring path and further activatible after the formation of the overlying interconnect layer to substitute the overlying test segment for the underlying test segment in the ring path.

Abstract: A test structure which can be used to detect residual conductive material such as polysilicon which can result from an under etch comprises a PMOS transistor and an OTP EPROM floating gate device. By testing the devices using different testing parameters, it can be determined whether residual conductive material remains subsequent to an etch, and where the residual conductive material is located on the device. A method for testing a semiconductor device using the test structure is also described.

Abstract: Semiconductor process evaluation methods perform multiple scans of a test semiconductor substrate (e.g., test wafer) using ion beams under different ion implanting conditions. Parameters of the test semiconductor substrate that was scanned using the ion beams under different ion implanting conditions are then measured to conduct the semiconductor process evaluation.

Abstract: A method of manufacturing a semiconductor module is provided. A semiconductor package is formed, having one or more plate units which are bent by heat. The semiconductor package is aligned on a module substrate, and connection members are disposed between the semiconductor package and the module substrate. Heat is applied to the plate units and the connection members to extend a distance between the module substrate and the semiconductor package, and connection patterns are formed. The height of the connection patterns is larger than that of the connection members.

Abstract: The present invention provides a method for manufacturing a semiconductor device. The method for manufacturing the semiconductor device, without limitation, may include providing a substrate having a sub-surface feature and a surface feature, and determining a location of the sub-surface feature relative to the surface feature using a scatterometer.

Abstract: A method for manufacturing a semiconductor device includes: (a) performing an inspection using an evaluation element formed on a scribe line of a semiconductor wafer; (b) marking a character on the semiconductor wafer, the character representing information based on a result obtained in step (a); and (c) performing a step subsequent to step (b) while using the information represented by the character marked in step (b).

Abstract: A decapsulation apparatus 100 has a laser 8 that removes plastic encapsulant from a device 24. Chamber 20 is sealed. Exhaust port 9 removes debris and fumes. The device 24 is positioned and scanned using an X, Y table 2. A hinged end 4 rotates the device to an acute angle of incidence with respect to a laser 8. Endpoint detector 10 senses the exposed integrated circuit and moves or shuts down the laser 8.