Abstract: A method of fabricating a semiconductor-on-insulator semiconductor wafer is described that includes providing first and second semiconductor substrates. A first insulating layer is formed on the first substrate with a first predetermined stress and a second insulating layer is formed on the second substrate with a second predetermined stress different than the first predetermined stress. The first insulating layer is bonded to the second insulating layer to form a composite insulating layer bonding the first substrate to the second substrate and a portion of the one substrate is removed to form a thin crystalline active layer on the composite insulating layer. The first and second insulating layers are formed with different stresses to provide a desired composite stress, which can be any stress from compressive to unstressed to tensile, depending upon the desired application.

Abstract: The invention provides methods for applying high temperature treatments to semiconductor wafers that limit surface tearing-off defects and surface particle contamination. In preferred embodiments, the high temperature treatments begin at boat-in temperatures of less than about 550° C. and include a first temperature ramp-up to the HT treatment temperatures at rates of 6° C./min or less. These methods are advantageously applied to semiconductor wafers comprising layers of different thermal properties, and in particular to semiconductor wafers comprising silicon-on-insulator structures.

Abstract: A patterned anti-reflective coating may be used as a selective implant-blocking layer during fabrication of an integrated circuit transistor. In particular, the anti-reflective coating may be used as a gate sidewall spacer to block at least some dopants from an integrated circuit substrate beneath the gate sidewall spacer. Moreover, a single mask may be used when fabricating source and drain extension regions and source and drain regions of an integrated circuit transistor.

Abstract: A method of forming an electronic device on a substrate 10, comprising: embossing the substrate 10, surface treating the substrate so that unindented portions 11 repel a solution of a first material 60, and depositing a solution of the first material 60 in indentations 12 on the substrate 10 formed by the embossing. The substrate is then annealed so that level of the first material is the same as the surface of the substrate. The first material 60 in the indentations can then, for example, be used as the source and drain in the subsequent formation of a TFT.

Abstract: There is provided a method of forming a semiconductor device having stacked transistors. When forming a contact hole for connecting the stacked transistors to each other, ohmic layers on the bottom and the sidewall of the common contact hole are separately formed. As a result, the respective ohmic layers are optimally formed to meet requirements or conditions. Accordingly, the contact resistance of the common contact may be minimized so that it is possible to enhance the speed of the semiconductor device.

Abstract: Highly reliable single crystal semiconductor layers and semiconductor devices can be obtained through a fewer manufacturing steps. A method for manufacturing a semiconductor device is proposed.

Abstract: A method of fabricating a hybrid substrate by direct bonding of donor and receiver substrates where each substrate has a respective front face and surface, with the front face of the receiver substrate having a semiconductor material near the surface, and the donor substrate including a zone of weakness that defines a layer to be transferred. The method includes preparing the substrate surfaces by exposing the surface of the receiver substrate to a temperature from about 900° C. to about 1200° C. in an inert atmosphere for at least 30 sec; directly bonding together the front faces of the prepared substrates to form a composite substrate; heat treating the composite substrate to increase bonding strength between the front surfaces of the donor and receiver substrates; and transferring the layer from the donor substrate by detaching the remainder of the donor substrate at the zone of weakness.

Abstract: A semiconductor substrate and a base substrate made from an insulator are prepared; an oxide film containing a chlorine atom is formed over the semiconductor substrate; the semiconductor substrate is irradiated with accelerated ions through the oxide film to form an embrittled region at a predetermined depth from a surface of the semiconductor substrate; plasma treatment of the oxide film is performed by applying a bias voltage; a surface of the semiconductor substrate and a surface of the base substrate are disposed opposite to each other to bond a surface of the oxide film and the surface of the base substrate to each other; and heat treatment is performed to cause separation along the embrittled region after bonding the surface of the oxide film and the surface of the base substrate to each other, thereby forming a semiconductor film over the base substrate with the oxide film interposed therebetween.

Abstract: A MEMS microphone has an SOI wafer, a backplate formed in a portion of the SOI wafer, and a diaphragm adjacent to and movable relative to the backplate. The backplate has at least one trench that substantially circumscribes a central portion of the backplate.

Abstract: A laser mask includes a mask pattern with edges having inverted shapes to alleviate the effects of diffraction of laser beams to reduce overlap regions such that crystallization characteristics are improved. The laser mask includes a mask pattern that includes transmitting regions and a blocking region. The edges of the mask have shapes inverted to the shapes of the edges of a silicon thin film crystallized by the pattern.

Abstract: An aggregation of crystals extending long in the scanning direction (a long crystal grain region) is formed when a continuous wave laser oscillator (a CW laser oscillator) is employed for annealing the semiconductor film in the manufacturing process of a semiconductor device. The long crystal grain region has a characteristic similar to that of single crystal in the scanning direction, but there is restriction for high integration because of the small output of the CW laser oscillator. In order to solve the problem, a pulsed laser beam 1 having a wavelength absorbed sufficiently in the semiconductor film is used in combination with a laser beam 2 having a high output and having a wavelength absorbed sufficiently in the melted semiconductor film. After irradiating the laser beam 1 to melt the semiconductor widely, the laser beam 2 is irradiated to the melted region.

Abstract: A method of manufacturing a semiconductor device, comprises the steps of: forming an amorphous silicon film on a substrate having an insulating surface; processing said amorphous silicon film by plasma of a gas that mainly contains hydrogen or helium; and giving an energy to said amorphous silicon film.

Abstract: The present invention provides a semiconductor substrate, which comprises a singlecrystalline Si substrate which includes an active layer having a channel region, a source region, and a drain region, the singlecrystalline Si substrate including at least a part of a device structure not containing a well-structure or a channel stop region; a gate insulating film formed on the singlecrystalline Si substrate; a gate electrode formed on the gate insulating film; a LOCOS oxide film whose thickness is more than a thickness of the gate insulating film, the LOCOS oxide film being formed on the singlecrystalline Si substrate by surrounding the active layer; and an insulating film formed over the gate electrode and the LOCOS oxide film.

Abstract: In a method of forming a single crystalline semiconductor layer, an amorphous layer may be formed on a seed layer that includes a single crystalline material. The single crystalline layer may be formed from the amorphous layer by irradiating a laser beam onto the amorphous layer using the seed layer as a seed for a phase change of the amorphous layer. The laser beam may have an energy for melting the amorphous layer, and the laser beam may be irradiated onto the amorphous layer without generating a superimposedly irradiated region of the amorphous layer. The single crystalline layer may include a high density of large-sized grains without generating a protrusion thereon through a simple process so that a semiconductor device including the single crystalline layer may have a high degree of integration and improved electrical characteristics.

Abstract: Embodiments of the present invention relate to the fabrication of a buried bi-layer insulator of silicon oxide and silicon nitride in a microelectronic substrate, and to the buried silicon oxide/silicon nitride bi-layer insulator itself. The buried silicon oxide/silicon nitride bi-layer insulator may be formed by implanting oxygen ions and nitrogen ions into the silicon-containing microelectronic substrate and then annealing the silicon-containing microelectronic substrate to form silicon oxide and silicon nitride layers therein.

Abstract: A diode 10 comprises an SOI substrate in which are stacked a semiconductor substrate 20, an insulator film 30, and a semiconductor layer 40. A bottom semiconductor region 60, an intermediate semiconductor region 53, and a surface semiconductor region 54 are formed in the semiconductor layer 40. The bottom semiconductor region 60 includes a high concentration of n-type impurity. The intermediate semiconductor region 53 includes a low concentration of n-type impurity. The surface semiconductor region 54 includes p-type impurity.

Abstract: A semiconductor film formed over a substrate is irradiated by a first laser beam which is incident on a bottom surface of the substrate at an angle and by a second laser beam which is incident on the bottom surface of the substrate at an angle opposite that of the first laser beam and oscillated by an oscillator differing from that of the first laser beam; whereby, part of the semiconductor film is melted, and a portion of the semiconductor film being melted is moved while the positions of irradiation of the first and the second laser beams and are being scanned approximately along the direction of slant for the first laser beam or the second laser beam.

Abstract: A method for fabrication of a monolithically integrated SOI substrate capacitor has the steps of: forming an insulating trench, which reaches down to the insulator and surrounds a region of the monocrystalline silicon of a SOI structure, doping the monocrystalline silicon region, forming an insulating, which can be nitride, layer region on a portion of the monocrystalline silicon region, forming a doped silicon layer region on the insulating layer region, and forming an insulating outside sidewall spacer on the monocrystalline silicon region, where the outside sidewall spacer surrounds the doped silicon layer region to provide an isolation between the doped silicon layer region and exposed portions of the monocrystalline silicon region. The monocrystalline silicon region, the insulating layer region, and the doped silicon layer region constitute a lower electrode, a dielectric, and an upper electrode of the capacitor.

Abstract: A method of fabricating a semiconductor device includes forming an insulation layer structure on a single-crystalline silicon substrate, forming a first insulation layer structure pattern comprising a first opening by etching a portion of the insulation layer structure, filling the first opening with a non-single-crystalline silicon layer, and forming a single-crystalline silicon pattern by irradiating a first laser beam onto the non-single-crystalline silicon layer. The method also includes forming a second insulation layer structure pattern comprising a second opening by etching a portion of the first insulation layer structure, filling the second opening with a non-single-crystalline silicon-germanium layer, and forming a single-crystalline silicon-germanium pattern by irradiating a second laser beam onto the non-single-crystalline silicon-germanium layer.

Abstract: An electronic device can have an insulating layer lying between a first semiconductor layer and a base layer. A second semiconductor layer, having a different composition and stress as compared to the first semiconductor layer, can overlie at least a portion of the first semiconductor layer. In one embodiment, a first electronic component can include a first active region that includes a first portion of the first and the second semiconductor layers. A second electronic component can include a second active region that can include a second portion of the first semiconductor layer. Different processes can be used to form the electronic device. In another embodiment, annealing a workpiece can be performed and the stress of at least one of the semiconductor layers can be changed. In a different embodiment, annealing the workpiece can be performed either before or after the formation of the second semiconductor layer.

Abstract: A process for producing an image display device using a thin film semiconductor device is provided which includes forming a polycrystalline semiconductor thin film on a substrate. A substantially belt-shaped crystal is formed which is crystallized so as to grow crystal grains in a direction substantially parallel to a scanning direction of a CW laser beam by scanning the CW laser beam along the substrate, thereby irradiating the CW laser beam on portions of the polycrystalline semiconductor thin film formed onto the substrate.

Abstract: A method is provided for making a semiconductor device, comprising (a) providing a semiconductor stack comprising a first semiconductor layer (407) having a <110> crystallographic orientation and a second semiconductor layer (405) having a <100> crystallographic orientation; (b) defining an oxide mask (415) in the first semiconductor layer; and (c) utilizing the oxide mask to pattern the second semiconductor layer.

Abstract: The sizes of crystal masses are made to be a uniform in a crystalline silicon film obtained by a thermal crystallization method in which a metal element is used. An amorphous silicon film to be crystallized is doped with a metal element that accelerates crystallization, and then irradiated with laser light (with an energy which is not large enough to melt the film and which is large enough to allow the metal element to diffuse in the solid silicon film) from the back side of a light-transmissive substrate. Thereafter, heat treatment is performed to obtain a crystalline silicon film. Thus crystal masses in the crystalline silicon film can have a uniform size and the problem of fluctuation between TFTs can be solved.

Abstract: A single crystal semiconductor substrate and a base substrate are prepared; a first insulating film is formed over the single crystal semiconductor substrate; a separation layer is formed by introducing ions at a predetermined depth through a surface of the single crystal semiconductor substrate; plasma treatment is performed on the base substrate so as to planarize a surface of the base substrate; a second insulating film is formed over the planarized base substrate; a surface of the first insulating film is bonded to a surface of the second insulating film by making the surface of the single crystal semiconductor substrate and the surface of the base substrate face each other; and a single crystal semiconductor film is provided over the base substrate with the second insulating film and the first insulating film interposed therebetween by performing separation at the separation layer.

Abstract: A SIMOX wafer is produced by implanting an oxygen ions into a surface of a Si substrate and then conducting a high-temperature annealing, in which an atmosphere in at least an end stage of the high-temperature annealing treatment is an Ar or N2 atmosphere containing an oxygen of more than 3 volume % but not more than 10 volume %.

Abstract: A method for forming CMOS integrated circuits. The method forms a blanket layer of silicon dioxide overlying an entirety of the surface region of a first well region and a second well region provided on a semiconductor substrate. The blanket layer of silicon dioxide is overlying the hard mask on the first gate structure and the second gate structure. The blanket layer of silicon dioxide is also overlying a region to be protected. Depending upon the embodiment, the region can be a sidewall spacer structure and portion of an MOS device on a peripheral region of the substrate. Of course, there can be other variations, modifications, and alternatives. The method protects the region to be protected using a masking layer, while the surface region of the first well region and the second well region being exposed.

Abstract: Since a supporting wafer contains nitrogen of 1×1014 atmos/cm3 and interstitial oxygen atom concentration, Oi, (old ASTM) of 13×1017 atoms/cm3, therefore a part of the metal impurities in an active layer wafer and the metal impurities in a bonded wafer can be captured by the BMD and the OSF in the wafer during the heat treatment after the bonding. Consequently, the contamination from the metal impurities in the active layer can be reduced.

Abstract: A thin film transistor device according to an embodiment of the invention includes: a thin film transistor having a silicon layer including a source region, a drain region, and a channel region, a gate insulating layer, and a gate electrode formed on an insulating substrate; an interlayer insulating layer covering the thin film transistor; a line electrically connected with the source region, the drain region, and the gate electrode through a contact hole formed in the interlayer insulating layer; a first upper insulating layer covering the line and the interlayer insulating layer and smoothing out stepped portions of the line and irregularities of a surface of the interlayer insulating layer; and a second upper insulating layer covering the first upper insulating layer, the second upper insulating layer having a hydrogen diffusion coefficient smaller than a hydrogen diffusion coefficient of the first upper insulating layer.

Abstract: Thin film devices and methods for forming the same are disclosed herein. A method for forming a thin film device includes forming a first at least semi-conductive strip located at a first height relative to a surface of a substrate, and forming a second at least semi-conductive strip adjacent to the first at least semi-conductive strip. The second strip is located at a second height relative to the substrate surface, and the second height is different than the first height. A nano-gap is formed between the first and second at least semi-conductive strips.

Abstract: The present invention is generally directed to a method of forming a pseudo SOI substrate and semiconductor devices. In one illustrative embodiment, the method comprises forming a plurality of trenches in a semiconducting substrate comprised of silicon, each of the trenches having a depth, forming a layer of insulating material within each of the plurality of trenches, the layer of insulating material having a thickness that is less than the depth of the trenches, and performing an anneal process on the substrate in a hydrogen environment to cause the silicon substrate material to merge above the layer of insulating material within the plurality of trenches to thereby define a pseudo SOI substrate.

Abstract: Disclosed is a structure and method for producing a fin-type field effect transistor (FinFET) that has a buried oxide layer over a substrate, at least one first fin structure and at least one second fin structure positioned on the buried oxide layer. First spacers are adjacent the first fin structure and second spacers are adjacent the second fin structure. The first spacers cover a larger portion of the first fin structure when compared to the portion of the second fin structure covered by the second spacers. Those fins that have larger spacers will receive a smaller area of semiconductor doping and those fins that have smaller spacers will receive a larger area of semiconductor doping. Therefore, there is a difference in doping between the first fins and the second fins that is caused by the differently sized spacers. The difference in doping between the first fins and the second fins changes an effective width of the second fins when compared to the first fins.

Abstract: A process of forming an electronic device can include patterning a semiconductor layer to define an opening extending to an insulating layer, wherein the insulating layer lies between a substrate and the semiconductor layer. After patterning the semiconductor layer, the opening can have a bottom, and the semiconductor layer can have a sidewall and a surface. The surface can be spaced apart from the insulating layer, and the sidewall can extend from the surface towards the insulating layer. The process can also include depositing a nitride layer within the opening, wherein depositing is performed using a PECVD technique. The process can further include densifying the nitride layer. The process can still further include removing a part of the nitride layer, wherein a remaining portion of the nitride layer can lie within the opening and be spaced apart from the surface.

Abstract: An apparatus and a method for forming the apparatus include a semiconductor layer on an insulating substrate, where the substrate is a different material than the semiconductor layer, and has a coefficient of thermal expansion substantially equal to that of the semiconductor layer. The semiconductor layer can also be formed having a thickness such that it does not yield due to temperature-induced strain at device processing temperatures. A silicon layer bonded to a silicon oxycarbide glass substrate provides a silicon on insulator wafer in which circuitry for electronic devices is fabricated.

Abstract: A method for manufacturing a semiconductor substrate includes forming a first semiconductor layer on a predetermined region of a semiconductor base, forming a second semiconductor layer whose etching selective ratio is smaller than that of the first semiconductor layer on the first semiconductor layer, forming a support member to support the second semiconductor layer on the semiconductor base so as to cover the second semiconductor layer, forming an opening face in the support member to expose a portion of an edge of the first semiconductor layer, etching the first semiconductor layer through the opening face so as to form a cavity between the second semiconductor layer and the semiconductor base, cleaning between the second semiconductor layer and the semiconductor base through the opening face in a condition to remove a residue of the first semiconductor layer, and forming an insulating film in the cavity after cleaned.

Abstract: A method of manufacturing a semiconductor device substrate includes forming a mask layer pattern on a semiconductor layer insulated from a surface of a semiconductor substrate by an electrically insulating layer, etching the semiconductor layer according to the pattern of the mask layer to form a trench leading to the insulating layer, etching a protective layer on the semiconductor substrate having a thickness less than the thickness of the insulating layer to form a sidewall protective film which covers a side surface of the trench, etching the insulating layer from a bottom surface of the trench to the semiconductor substrate; and growing a single-crystalline layer from the surface of the semiconductor substrate exposed as a result of etching the insulating layer.

Abstract: An integrated circuit of a semiconductor device has a line type of pattern that is not prone to serious RC delays. The integrated circuit has a line formed of at least a layer of polycrystalline silicon, a layer of metal having a low sheet resistance, and a layer of a barrier metal interposed between the polycrystalline silicon and the metal having a low sheet resistance, and first spacers disposed on the sides of the line, respectively, and is characterized in that the line has recesses at the sides of the barrier layer and the first spacers fill the recesses. The integrated circuit may constitute a gate line of a semiconductor device. The integrated circuit is formed by forming layers of polycrystalline silicon, metal having a low sheet resistance, and a barrier metal one atop the other, patterning the layers into a line, etching the same to form the recesses, and then forming the first spacers.

Abstract: A method of manufacturing thin film field effect transistors is described. The channel region of the transistors is formed by depositing an amorphous semiconductor film in a first sputtering apparatus followed by thermal treatment for converting the amorphous phase to a polycrystalline phase. The gate insulating film is formed by depositing an oxide film in a second sputtering apparatus connected to the first apparatus through a gate valve. The sputtering for the deposition of the amorphous semiconductor film is carried out in an atmosphere comprising hydrogen in order to introduce hydrogen into the amorphous semiconductor film. On the other hand the gate insulating oxide film is deposited by sputtering in an atmosphere comprising oxygen.

Abstract: A support member for semiconductor device elements includes a conductive layer separated from the semiconductor elements by an insulative layer. A protective potential lower than any operating potential applied to the semiconductor device elements is applied to the conductive layer. The relatively negative potential on the conductive layer forms an electric field for gettering mobile ions from layers of the support member both above and below the conductive layer. Additionally, the conductive layer within the support member serves as a second plate in construction of capacitors and as a wiring layer for use with the semiconductor device elements. Also, due to the reflective properties of the conductive layer, it may function as a light shield or reflector in the construction of optic devices.

Abstract: An object of the present invention is to provide a method for manufacturing a semiconductor device in which, after crystallizing by using an element that promotes crystallization, holes are prevented from being generated in a crystalline semiconductor film with a concentration of the element in the crystalline semiconductor film decreased by performing gettering. To solve the problem, as a feature of the structure of the invention, in the case of removing a silicon oxide film formed over the semiconductor film, an etchant made of a solution containing fluorine and a substance having surface activity is used.

Abstract: A heterostructure is provided which includes a substantially relaxed SiGe layer present atop an insulating region that is located on a substrate. The substantially relaxed SiGe layer has a thickness of from about 2000 nm or less, a measured lattice relaxation of from about 50 to about 80% and a defect density of less than about 108 defects/cm2. A strained epitaxial Si layer is located atop the substantially relaxed SiGe layer and at least one alternating stack including a bottom relaxed SiGe layer and an top strained Si layer located on the strained epitaxial Si layer.

Abstract: A thin film transistor including a gate, a gate insulator layer, a channel layer, a source, a drain, and an ohmic contact layer is provided. The gate insulator layer covers the gate; the channel layer is disposed on the gate insulator layer above the gate; the source and the drain are disposed on the channel layer; the ohmic contact layer is disposed between the channel layer and the source and drain. The ohmic contact layer is constituted of a plurality of film layers. As mentioned above, the thin film transistor has an ohmic contact layer constituted by a plurality of film layers. When the thin film transistor is turned off, the current leakage thereof is lowered than that of conventional thin film transistor.

Abstract: A method of forming a substantially relaxed, high-quality SiGe-on-insulator substrate material using SIMOX and Ge interdiffusion is provided. The method includes first implanting ions into a Si-containing substrate to form an implant rich region in the Si-containing substrate. The implant rich region has a sufficient ion concentration such that during a subsequent anneal at high temperatures a barrier layer that is resistant to Ge diffusion is formed. Next, a Ge-containing layer is formed on a surface of the Si-containing substrate, and thereafter a heating step is performed at a temperature which permits formation of the barrier layer and interdiffusion of Ge thereby forming a substantially relaxed, single crystal SiGe layer atop the barrier layer.

Abstract: A SIMOX wafer manufacturing method which is capable of providing etching conditions to prevent surface defects (divots) from being spread. The method includes an oxygen implantation process and a high temperature annealing step for forming a BOX layer, a front surface oxide film etching process to treat a front surface of the wafer at an area in which oxygen is implanted, and a rear surface oxide film etching process to treat a rear surface of the wafer, and oxide film etching conditions in the front and rear oxide film etching processes are controlled differently.

Abstract: In this semiconductor memory device, a potential clamping region having no insulation layer formed therein is provided in an insulation layer. More specifically, the potential clamping region is formed under a body portion at a position near a first impurity region, and extends to a first semiconductor layer. A body fixing portion is formed in a boundary region between the body portion and the potential clamping region. This structure enables improvement in operation performance without increasing the layout area in the case where a DRAM cell is formed in a SOI (Silicon On Insulator) structure.

Abstract: The invention encompasses a method of forming a semiconductor-on-insulator construction. A substrate is provided. The substrate includes a semiconductor-containing layer over an insulative mass. The insulative mass comprises silicon dioxide. A band of material is formed within the insulative mass. The material comprises one or more of nitrogen argon, fluorine, bromine, chlorine, iodine and germanium.

Abstract: A method for manufacturing a thin film transistor substrate using a maskless exposing device includes forming a data metal layer on a substrate having a gate pattern and common electrodes along with gate insulation layers, active layers, and ohmic contact layers for a thin film transistors; forming a photoresist on the data metal layer; exposing a first amount of light onto the photoresist at first regions, excluding a second region where data lines and thin film transistors are to be formed, by using a maskless exposing device; exposing a second amount of light onto the photoresist at third regions, where channels of the thin film transistors are to be formed, wherein the second amount of light is smaller than the first amount of light; and developing the first, second and third regions of the photoresist.

Abstract: A semiconductor device includes a gate electrode formed on a semiconductor layer, source and drain layers formed in the semiconductor layer and disposed on both sides of the gate electrode, and a field plate disposed at the back of the semiconductor layer with an insulating layer provided therebetween.

Abstract: A method of making at least one marker (MX) for double gate SOI processing on a SOI wafer is disclosed. The marker has a diffracting structure in a first direction and the diffracting structure is configured to generate an asymmetrical diffraction pattern during use in an alignment and overlay detection system for detection in the first direction.

Abstract: A strained (tensile or compressive) semiconductor-on-insulator material is provided in which a single semiconductor wafer and a separation by ion implantation of oxygen process are used. The separation by ion implantation of oxygen process, which includes oxygen ion implantation and annealing creates, a buried oxide layer within the material that is located beneath the strained semiconductor layer. In some embodiments, a graded semiconductor buffer layer is located beneath the buried oxide layer, while in other a doped semiconductor layer including Si doped with at least one of B or C is located beneath the buried oxide layer.

Abstract: A method for fabricating a hybrid orientation substrate provides for: (1) a horizontal epitaxial augmentation of a masked surface semiconductor layer that leaves exposed a portion of a base semiconductor substrate; and (2) a vertical epitaxial augmentation of the exposed portion of the base semiconductor substrate. The resulting surface semiconductor layer and epitaxial surface semiconductor layer adjoin with an interface that is not perpendicular to the base semiconductor substrate. The method also includes implanting through the surface semiconductor layer and the epitaxial surface semiconductor layer a dielectric forming ion to provide a buried dielectric layer that separates the surface semiconductor layer and the epitaxial surface semiconductor layer from the base semiconductor substrate.