Abstract: Methods for creating at least one micro-electromechanical (MEMS) structure in a silicon-on-insulator (SOI) wafer. The SOI wafer with an extra layer of oxide is etched according to a predefined pattern. A layer of oxide is deposited over exposed surfaces. An etchant selectively removes the oxide to expose the SOI wafer substrate. A portion of the SOI substrate under at least one MEMS structure is removed, thereby releasing the MEMS structure to be used in the formation of an accelerometer.

Abstract: A space is provided under part of a semiconductor layer. Specifically, a structure in which an eaves portion (a projecting portion, an overhang portion) is formed in the semiconductor layer. The eaves portion is formed as follows: a stacked-layer structure in which a conductive layer, an insulating layer, and a semiconductor layer are stacked in this order is etched collectively to determine a pattern of a gate electrode; and a pattern of the semiconductor layer is formed while side-etching is performed.

Abstract: The invention relates to a method for forming microcavities (118) of different depths in a layer (102) based on at least an amorphous or monocrystalline material, comprising at least the following steps in which: at least one shaft and/or trench is formed in the layer (102) so as to extend through one face (101) thereof, such that two sections of the shaft and/or the trench, in two different planes parallel to the face (101), are aligned in relation to one another along an alignment axis forming a non-zero angle with a normal to the plane of said face (101); and the layer (102) is annealed in a hydrogenated atmosphere so as to transform the shaft and/or trench into at least two microcavities (118).

Abstract: An effect of metal contamination caused in manufacturing an SOI substrate can is suppressed. A damaged region is formed by irradiating a semiconductor substrate with hydrogen ions, and then, a base substrate and the semiconductor substrate are bonded to each other. Heat treatment is performed thereon to cleave the semiconductor substrate, so that an SOI substrate is manufactured. A gettering site layer is formed of a semiconductor containing a Group 18 element such as Ar, over a semiconductor layer of the SOI substrate. Heat treatment is performed thereon to perform gettering of a metal element in the semiconductor layer with the gettering site layer. By removing the gettering site layer by etching, thinning of the semiconductor layer can be performed.

Abstract: There is provided a method for suppressing the occurrence of defects such as voids or blisters even in the laminated wafer having an oxide film of a thickness thinner than the conventional one, wherein hydrogen ions are implanted into a wafer for active layer having an oxide film of not more than 50 nm in thickness to form a hydrogen ion implanted layer, and ions other than hydrogen are implanted up to a position that a depth from the surface side the hydrogen ion implantation is shallower than the hydrogen ion implanted layer, and the wafer for active layer is laminated onto a wafer for support substrate through the oxide film, and then the wafer for active layer is exfoliated at the hydrogen ion implanted layer.

Abstract: A manufacturing method of an SOI substrate and a manufacturing method of a semiconductor device are provided. When a large-area single crystalline semiconductor film is formed over an enlarged substrate having an insulating surface, e.g., a glass substrate by an SOI technique, the large-area single crystalline semiconductor film is formed without any gap between plural single crystalline semiconductor films, even when plural silicon wafers are used. An aspect of the manufacturing method includes the steps of disposing a first seed substrate over a fixing substrate; tightly arranging a plurality of single crystalline semiconductor substrates over the first seed substrate to form a second seed substrate; forming a large-area continuous single crystalline semiconductor film by an ion implantation separation method and an epitaxial growth method; forming a large-area single crystalline semiconductor film without any gap over a large glass substrate by an ion implantation separation method again.

Abstract: A double-gate FinFET and methods for its manufacture are provided. The FinFET includes first and second gates (72, 74) adjacent respective sides of the fin (20), with at least a portion of the first gate facing the fin being formed of polycrystalline silicon, and at least a portion of the second gate facing the fin being formed of a metal silicide compound. The different compositions of the two gates provide different respective work functions to reduce short channel effects.

Abstract: A semiconductor device includes a semiconductor material having two crystal orientations. The semiconductor material forms an active area of the device. A device channel is formed on the two crystal orientations, which include a first region formed in a first crystal orientation surface of the semiconductor material, and a second region formed in a second crystal orientation surface of the semiconductor material wherein the first crystal orientation surface forms an angle with the second crystal orientation surface and the device channel covers at least an intersection of the angle.

Abstract: In a method of manufacturing a thin film transistor substrate, a gate line and a gate electrode are formed on a substrate. A gate insulating layer is formed to cover the gate line and the gate electrode. A semiconductor layer is formed on the gate insulating layer to overlap with the gate electrode. A data line, a source electrode, and a drain electrode are formed on the gate insulating layer and the semiconductor layer. A photoresist layer is formed on the data line, the source electrode, and the drain electrode. The photoresist layer is patterned, and an organic layer is formed on the substrate having the photoresist layer pattern. Then, the photoresist layer pattern is removed.

Abstract: Methods and apparatus for producing a semiconductor on glass (SiOG) structure include: subjecting an implantation surface of a donor semiconductor wafer to an ion implantation process to create an exfoliation layer in the donor semiconductor wafer; bonding the implantation surface of the exfoliation layer to a glass substrate using electrolysis; separating the exfoliation layer from the donor semiconductor wafer, thereby exposing at least one cleaved surface; and subjecting the at least one cleaved surface to a wet etching process.

Abstract: A strain-inducing semiconductor alloy may be formed on the basis of cavities that may extend deeply below the gate electrode structure, which may be accomplished by using a sequence of two etch processes. In a first etch process, the cavity may be formed on the basis of a well-defined lateral offset to ensure integrity of the gate electrode structure and, in a subsequent etch process, the cavity may be increased in a lateral direction while nevertheless reliably preserving a portion of the channel region. Consequently, the strain-inducing efficiency may be increased by appropriately positioning the strain-inducing material immediately below the channel region without compromising integrity of the gate electrode structure.

Abstract: Semiconductor devices with low junction capacitances and methods of fabrication thereof are described. In one embodiment, a method of forming a semiconductor device includes forming isolation regions in a substrate to form active areas. The sidewalls of the active areas are enclosed by the isolation regions. The isolation regions are recessed to expose first parts of the sidewalls of the active areas. The first parts of the sidewalls of the active areas are covered with spacers. The isolation regions are etched to expose second parts of the sidewalls of the active area, the second parts being disposed below the first parts. The active areas are etched through the exposed second parts of the sidewalls to form lateral openings. The lateral openings are filled with a spin on dielectric.

Abstract: This invention describes implementation of medium/high voltage semiconductor devices with a better voltage-blocking capability versus specific on-resistan?e trade off. This approach can be implemented in baseline and submicron CMOS without any additional process steps. Said devices comprise dielectric regions and semiconductor regions formed between them. Conductive extentions are formed on the dielectric regions, said extentions interacting capacitively with the semiconducter regions.

Abstract: To prevent bubbles from occurring along a transfer interface, the present method includes the steps of: forming a peeled layer 10 in a transferred member 6 by implanting a peeled-layer forming substance into the transferred member 6; forming a planar surface in the transferred member 6 by planarizing a surface of the transferred member 6; forming a composite including the transferred member 6 and a glass substrate 2 by directly combining the transferred member 6 via the planar surface with a surface of the glass substrate 2; and peeling a part of the transferred member 6 from the composite along the peeled layer 10 serving as an interface by heat-treating the composite.

Abstract: A method for making a semiconductor on insulator (SeOI) type substrate that includes an integrated ground plane under the insulating layer wherein the substrate is intended to be used in making electronic components. This method includes implanting atoms or ions of a metal in at least one portion of a semiconducting receiver substrate, carrying out a heat treatment of the receiver substrate in order to obtain an integrated ground plane on or in at least one portion of that receiver substrate, transferring an active layer stemming from a semiconducting donor substrate onto the receiver substrate, with an insulating layer being inserted in between the donor and receiver substrates to obtain the substrate with an integrated ground plane.

Abstract: A memory circuit having dual-gate memory cells and a method for fabricating such a memory circuit are disclosed. The dual-gate memory cells each include a memory device and an access device sharing a semiconductor layer, with their respective channel regions provided on different surfaces of the semiconductor layer. The semiconductor layer has a thickness such that a sensitivity parameter relating an electrical interaction between the gate electrodes of the access device and the memory device is less than a predetermined value. The dual-gate memory cells can be used as building blocks for a non-volatile memory array, such as a memory array formed by NAND-strings.

Abstract: A semiconductor device includes a semiconductor material having two crystal orientations. The semiconductor material forms an active area of the device. A device channel is formed on the two crystal orientations, which include a first region formed in a first crystal orientation surface of the semiconductor material, and a second region formed in a second crystal orientation surface of the semiconductor material wherein the first crystal orientation surface forms an angle with the second crystal orientation surface and the device channel covers at least an intersection of the angle.

Abstract: A semiconductor-on-insulator substrate and a related semiconductor structure, as well as a method for fabricating the semiconductor-on-insulator substrate and the related semiconductor structure, provide for a multiple order radio frequency harmonic suppressing region located and formed within a base semiconductor substrate at a location beneath an interface of a buried dielectric layer with the base semiconductor substrate within the semiconductor-on-insulator substrate. The multiple order radio frequency harmonic suppressing region may comprise an ion implanted atom, such as but not limited to a noble gas atom, to provide a suppressed multiple order radio frequency harmonic when powering a radio frequency device, such as but not limited to a radio frequency complementary metal oxide semiconductor device (or alternatively a passive device), located and formed within and upon a surface semiconductor layer within the semiconductor structure.

Abstract: A highly responsive semiconductor device in which the subthreshold swing (S value) is small and reduction in on-current is suppressed is manufactured. A semiconductor layer in which a thickness of a source region or a drain region is larger than that of a channel formation region is formed. A semiconductor layer having a concavo-convex shape which is included in the semiconductor device is formed by the steps of forming a first semiconductor layer over a substrate; forming a first insulating layer and a conductive layer over the first semiconductor layer; forming a second insulating layer over a side surface of the conductive layer; forming a second semiconductor layer over the first insulating layer, the conductive layer and the second insulating layer; etching the second semiconductor layer using a resist formed partially as a mask; and performing heat treatment to the first semiconductor layer and the second semiconductor layer.

Abstract: A semiconductor circuit in a semiconductor body and a wafer bonding method for connecting the semiconductor circuit to another substrate, in which a diode is realized in a laminar structure. The semiconductor circuit is connected to the terminals of the diode by means of that extend through the semiconductor body.

Abstract: A method and resulting structure for fabricating a FET transistor for an integrated circuit on a silicon oxide (SOI) substrate comprising the steps of forming recesses in a substrate on both sides of a gate on the substrate, implanting oxygen ions into the recesses, and annealing the substrate to convert the oxygen ions into a SOI layer below each recess.

Abstract: Methods of manufacturing an oxide semiconductor thin film transistor are provided. The methods include forming a gate on a substrate, and a gate insulating layer on the substrate to cover the gate. A channel layer, which is formed of an oxide semiconductor, may be formed on the gate insulating layer. Source and drain electrodes may be formed on opposing sides of the channel layer. The method includes forming supplying oxygen to the channel layer, forming a passivation layer to cover the source and drain electrodes and the channel layer, and performing an annealing process after forming the passivation layer.

Abstract: A semiconductor wafer structure for manufacturing integrated circuit devices includes a bulk substrate; a lower insulating layer formed on the bulk substrate, the lower insulating layer formed from a pair of separate insulation layers having a bonding interface therebetween; an electrically conductive layer formed on the lower insulating layer, the electrically conductive layer further having one or more shallow trench isolation (STI) regions formed therein; an etch stop layer formed on the electrically conductive layer and the one or more STI regions; an upper insulating layer formed on the etch stop layer; and a semiconductor layer formed on the upper insulating layer. A subsequent active area level STI scheme, in conjunction with front gate formation over the semiconductor layer, is also disclosed.

Abstract: A semiconductor device includes an NMISFET region. The NMISFET region includes a Ge nano wire having a triangular cross section along a direction perpendicular to a channel current direction, wherein two of surfaces that define the triangular cross section of the Ge nano wire are (111) planes, and the other surface that define the triangular cross section of the Ge nano wire is a (100) plane; and an Si layer or an Si1-xGex layer (0<x<0.5) on the (100) plane of the Ge nano wire.

Abstract: A semiconductor wafer structure for manufacturing integrated circuit devices includes a bulk substrate; a lower insulating layer formed on the bulk substrate, the lower insulating layer formed from a pair of separate insulation layers having a bonding interface therebetween; an electrically conductive layer formed on the lower insulating layer, the electrically conductive layer further having one or more shallow trench isolation (STI) regions formed therein; an etch stop layer formed on the electrically conductive layer and the one or more STI regions; an upper insulating layer formed on the etch stop layer; and a semiconductor layer formed on the upper insulating layer. A subsequent active area level STI scheme, in conjunction with front gate formation over the semiconductor layer, is also disclosed.

Abstract: A method of fabricating a nanoscale cantilever probe. In one embodiment, the method includes the steps of forming a cantilever having a tip vertically extending from an end portion of the cantilever, where the tip has an apex portion having a size in a range of about 1-1000 nm, and selectively doping the cantilever with a dopant to define a first doping region in the tip and a second doping region in the rest of the cantilever, where the dopant concentration of the first doping region is substantially lower than that of the second doping region.

Abstract: There is provided a semiconductor device including: convex semiconductor layers formed on a semiconductor substrate via an insulating film; gate electrodes formed on a pair of facing sides of the semiconductor layers via a gate insulating film; a channel region formed of silicon between the gate electrodes in the semiconductor layers; a source extension region and a drain extension region formed of silicon germanium or silicon carbon on both sides of the channel region in the semiconductor layers; and a source region formed of silicon so as to adjoin to the opposite side of the channel region in the source extension region, and a drain region formed of silicon so as to adjoin to the opposite side of the channel region in the drain extension region in the semiconductor layers.

Abstract: A method of producing a transistor having parallel semiconductor nanofingers. The method includes: forming a monocrystalline layer of a semiconductor material on a layer of a subjacent material which can be selectively etched in relation to the monocrystalline layer; etching parallel partitions in the monocrystalline layer and in the subjacent layer and continuing said etching operation in order to hollow out part of the subjacent layer of material; filling the gap between the partitions and the hollowed-out part with a first insulating material; defining a central part of the partitions and removing the first insulating material from around the central part of the monocrystalline layer, thereby forming a finger of semiconductor material; and filling and coating the central part with a conductor material.

Abstract: In one embodiment of the present invention, a method for manufacturing a semiconductor device includes: forming a to-be-removed layer on a semiconductor substrate; forming a semiconductor layer on the to-be-removed layer; forming a trench that passes through the semiconductor layer to the to-be-removed layer in an SOI region; removing the to-be-removed layer by using the trench and creating a cavity; and forming an insulating film in the cavity.

Abstract: Briefly, in accordance with one or more embodiments, a detector panel of an imaging system may be produced from a photodiode array integrated with a thin-film transistor array. The thin film transistor array may have one or more vias formed for increasing the adhesion of the photodiode array to the thin-film transistor array. The vias may comprise sidewalls having stepped structures. The thin-film transistor array may comprise a first metallization layer and a second metallization layer. A third metallization layer may be added to the thin film transistor array wherein diodes of the photodiode array may contact the third metallization layer. Diodes of the photodiode array may contact the first metallization layer and/or the second metallization layer via the third metallization layer without directly contacting the first metallization layer or the second metallization layer.

Abstract: In a laser irradiation apparatus having low running costs as compared with a conventional apparatus and a laser beam irradiation method using the same, a crystalline semiconductor film having a crystal grain of a grain size equivalent to or larger than a conventional one is formed, and a TFT is manufactured by using the crystalline semiconductor film, so that the TFT enabling a high speed operation is realized. In a case where a laser beam of a short output time from a solid laser as a light source is irradiated to a semiconductor film, another laser beam is delayed from one laser beam, and the laser beams are synthesized to be irradiated to the semiconductor film, so that a cooling speed of the semiconductor film is made gentle, and it becomes possible to form the crystalline semiconductor film having the crystal grain of the grain size equivalent to or larger than that in a case where a laser beam having a long output time is irradiated to the semiconductor film.

Abstract: A SOI device features a conductive pathway between active SOI devices and a bulk SOI substrate. The conductive pathway provides the ability to sink plasma-induced process charges into a bulk substrate in the event of process charging, such as interlayer dielectric deposition in a plasma environment, plasma etch deposition, or other fabrication provides. A method is also disclosed which includes dissipating electrostatic and process charges from a top of a SOI device to the bottom of the device. The top and bottom of the SOI device may characterize a region of active devices and a semiconductor method respectively. The method further includes a single masking step to create seed regions for an epitaxial-silicon pathway.

Abstract: Shrinking the dimensions of PMOS or NMOS thin film transistors is limited by dopant diffusion. In these devices an undoped or lightly doped channel region is interposed between heavily doped source and drain regions. When the device is built with very short gate length, source and drain dopants will diffuse into the channel, potentially shorting it and ruining the device. A suite of innovations is described which may be used in various combinations to minimize dopant diffusion during fabrication of a PMOS or NMOS polycrystalline thin film transistor, resulting in a highly scalable thin film transistor. This transistor is particularly suitable for use in a monolithic three dimensional array of stacked device levels.

Abstract: A semiconductor structure is described. The structure includes a trench opening formed in a semiconductor substrate having a semiconductor-on-insulator (SOI) layer and a buried insulating (BOX) layer; and a filling material formed in the trench opening, the filling material forming a “V” shape within the trench memory cell, wherein the “V” shape includes a top portion substantially adjacent to a top surface of the BOX layer. A method of fabricating the semiconductor structure is also described. The method includes forming a trench opening in a semiconductor substrate having an SOI layer and a BOX layer; laterally etching the BOX layer such that a portion of the trench opening associated with the BOX layer is substantially greater than a portion of the trench opening associated with the SOI layer; filling the trench opening with a filling material; and recessing the filling material.

Abstract: Provided is a method for producing an SOI substrate comprising a transparent insulating substrate and a silicon film formed on a first major surface of the insulating substrate wherein a second major surface of the insulating substrate which is opposite to the major surface is roughened, the method suppressing the generation of metal impurities and particles in a simple and easy way.

Abstract: In SOI devices, the PN junction of circuit elements, such as substrate diodes, is formed in the substrate material on the basis of the buried insulating material that provides increased etch resistivity during wet chemical cleaning and etch processes. Consequently, undue exposure of the PN junction formed in the vicinity of the sidewalls of the buried insulating material may be avoided, which may cause reliability concerns in conventional SOI devices comprising a silicon dioxide material as the buried insulating layer.

Abstract: The disclosure provides a method for fabricating a semiconductor substrate comprising the steps of: providing a semiconductor on insulator type substrate, providing a diffusion barrier layer and providing a second semiconductor layer. By providing the diffusion barrier layer, it becomes possible to suppress diffusion from the highly doped first semiconductor layer into the second semiconductor layer. The invention also relates to a corresponding semiconductor substrate and opto-electronic devices comprising such a substrate.

Abstract: The present disclosure relates to methods and apparatuses for fracturing or breaking a buried porous semiconductor layer to separate a 3-D thin-film semiconductor semiconductor (TFSS) substrate from a 3-D crystalline semiconductor template. The method involves forming a sacrificial porous semiconductor layer on the 3-D features of the template. A variety of techniques may be used to fracture and release the mechanically weak porous semiconductor layer without damaging the TFSS substrate layer or the template layer such as pressure variations, thermal stress generation, and mechanical bending. The methods also allow for processing three dimensional features not possible with current separation processes. Optional cleaning and final lift-off steps may be performed as part of the release step or after the release step.

Abstract: Formation of LDD structures and GOLD structures in a semiconductor device is conventionally performed in a self aligning manner with gate electrodes as masks, but there are many cases in which the gate electrodes have two layer structures, and film formation processes and etching processes become complex. Further, in order to perform formation of LDD structures and GOLD structures only by processes such as dry etching, the transistor structures all have the same structure, and it is difficult to form LDD structures, GOLD structures, and single drain structures separately for different circuits.

Abstract: A field effect transistor including: a support layer, a plurality of active zones based on a semiconductor, each active zone configured to form a channel and arranged between two gates adjacent to each other and consecutive, the active zones and the gates being arranged on the support layer, each gate including a first face on the side of the support layer and a second face opposite the first face. The second face of a first of the two gates is electrically connected to a first electrical contact made on the second face of the first of the two gates, and the first face of a second of the two gates is electrically connected to a second electrical contact passing through the support layer. The gates of the transistor are not electrically connected to each other.

Abstract: A method of the present invention includes a first planarization film formation step of forming, in at least part of a flat portion of the second regions, a first planarization film so as to have a uniform thickness; a second planarization film formation step of forming a second planarization film between the first planarization films to be coplanar with a surface of the first planarization film; a peeling layer formation step of forming a peeling layer by ion implantation of a peeling material into the base layer via the first planarization film or the second planarization film; and a separation step of separating part of the base layer along the peeling layer.

Abstract: A semiconductor device includes a tube-type channel formed over a semiconductor substrate. The tube-type channel is connected to first and second conductive lines. A bias electrode is formed in the tube-type channel. The bias electrode is connected to the semiconductor substrate. An insulating film is disposed between the tube-type channel and the bias electrode. A surrounding gate electrode is formed over the tube-type channel.

Abstract: When the single crystal semiconductor layer is melted, the outward diffusion of oxygen is promoted. Specifically, an SOI substrate is formed in such a manner that an SOI structure having a bonding layer including oxygen provided over a base substrate and a single crystal semiconductor layer provided over the bonding layer including oxygen is formed, and part of the single crystal semiconductor layer is melted by irradiation with a laser beam in a state that the base substrate is heated at a temperature of higher than or equal to 500° C. and lower than a melting point of the base substrate.

Abstract: An electronic device can include a first semiconductor portion and a second semiconductor portion, wherein the compositions of the first and second semiconductor portions are different from each other. In one embodiment, the first and second semiconductor portions can have different stresses compared to each other. In one embodiment, the electronic device may be formed by forming an oxidation mask over the first semiconductor portion. A second semiconductor layer can be formed over the second semiconductor portion of the first semiconductor layer and have a different composition compared to the first semiconductor layer. An oxidation can be performed, and a concentration of a semiconductor element (e.g., germanium) within the second portion of the first semiconductor layer can be increased. In another embodiment, a selective condensation may be performed, and a field isolation region can be formed between the first and second portions of the first semiconductor layer.

Abstract: The invention relates to a method for manufacturing compound material wafers, in particular, silicon on insulator type wafers, by providing an initial donor substrate, forming an insulating layer over the initial donor substrate, forming a predetermined splitting area in the initial donor substrate, attaching the initial donor substrate onto a handle substrate and detaching the donor substrate at the predetermined splitting area, thereby transferring a layer of the initial donor substrate onto the handle substrate to form a compound material wafer. In order to be able to reuse the donor substrate more often, the invention proposes to carry out the thermal treatment step to form the insulating layer at a temperature of less than 950° C., in particular, less than 900° C., and preferably at 850° C. The invention also relates to a silicon on insulator type wafer manufactured according to the inventive method.

Abstract: A catalyst element remaining in a first semiconductor film subjected to a first heat treatment (crystallization) is moved and concentrated/collected by subjecting a second semiconductor film which is formed on the first semiconductor film and contains a rare gas element to a second heat treatment. That is, the rare gas element is incorporated into the second semiconductor film to generate a strain field as a gettering site.

Abstract: Methods for fabricating nanoscale features are disclosed. One technique involves depositing onto a substrate, where the first layer may be a silicon layer and may subsequently be etched. A second layer and third layer may be deposited on the etch first layer, followed by the deposition of a silicon cap. The second and third layer may be etched, exposing edges of the second and third layers. The cap and first layer may be removed and either the second or third layer may be etched, creating a nanoscale pattern.

Abstract: A bonded wafer is produced by a step of forming an oxygen ion implanted layer, a step of forming a wafer composite, a step of exposing the oxygen ion implanted layer, and a step of obtaining an active layer, wherein the exposed oxygen ion implanted layer is removed by sequentially subjecting to a first HF treatment, a given oxidation heat treatment, and then a second HF treatment.

Abstract: A flat panel display device (FPD) and fabricating method thereof are disclosed, which reduce the number of masks during fabrication and prevent electro-chemical corrosion problems. In the FPD, a cell area and a pad area are defined on a substrate. A storage electrode traverses an active layer in parallel to a gate line. Source and drain regions of the active layer in the vicinity of both sides of a gate electrode are not formed below the storage electrode. An insulating interlayer over the substrate has first and second contact holes on the source and drain regions, respectively. A source electrode contacts the source region via a first contact hole and a drain electrode contacts the drain region via a second contact hole to directly contact a pixel electrode. A protective layer is disposed over the substrate including the pixel electrode.

Abstract: Semiconductor devices and semiconductor device manufacturing methods. The semiconductor device manufacturing methods may form a memory cell having a silicon on insulator (SOI) structure only in one or more localized regions of a bulk semiconductor substrate by use selective etching. Accordingly, a different bias voltage may be applied to a peripheral device than to a memory cell having the SOI structure.