Abstract: The invention provides a heat radiating structure which reduces a mechanical stress applied to an electronic part mounted on a printed circuit board including a semiconductor package. The heat radiating structure is constructed by a semiconductor package mounted on a printed circuit board, a thermal conduction sheet arranged on an upper surface of the semiconductor package, and a metal case provided with a heat radiating fin for receiving a heat transmitted form the thermal conduction sheet so as to discharge to an atmospheric air, and the metal case is provided with a concavo-convex structure in a contact portion with the thermal conduction sheet.

Abstract: Semiconductor die packages and methods of making them are disclosed. An exemplary package comprises a leadframe having a source lead and a gate lead, and a semiconductor die coupled to the source and gate leads at a first surface of the leadframe. The source lead has a protruding region at a second surface of the leadframe. A molding material is disposed around the semiconductor die, the gate lead, and the source lead such that a surface of the die and a surface of the protruding region are left exposed by the molding material. An exemplary method comprises obtaining the semiconductor die and leadframe, and forming a molding material around at least a portion of the leadframe and die such that a surface of the protruding region is exposed through the molding material.

Abstract: Provided is a semiconductor module wherein a stress relaxing layer is arranged between a ceramic substrate, upon which semiconductor elements are mounted, and a cooling device on the rear side of the ceramic substrate; and the ceramic substrate, the cooling device and the stress relaxing layer are integrally formed. Furthermore, the stress relaxing layer is separated into a plurality of separated sections by two slits. Furthermore, the slits are positioned between the semiconductor elements when viewed from the thickness direction of the stress relaxing layer and not in a projection region of the semiconductor element.

Abstract: A semiconductor die package including at least two heat sinks. The semiconductor die package includes a first heat sink, a second heat sink coupled to the first heat sink, and a semiconductor die between the first heat sink and the second heat sink. The semiconductor die is electrically coupled to the first heat sink and the second heat sink. The semiconductor die may also be attached to a lead.

Abstract: A method of manufacture an integrated circuit packaging system includes: providing a substrate; attaching a first integrated circuit to the substrate by interconnects only along opposite sides of the first integrated circuit; and attaching a heat spreader to the substrate, the heat spreader extending over the first integrated circuit and between the opposite sides of the first integrated circuit.

Abstract: The invention relates to a power semiconductor module comprising at least one power semiconductor chip, and comprising a pressure apparatus which exerts a pressure on the top side of the power semiconductor chip when the power semiconductor module is fixed to a heat sink. In addition, a bonding wire which is arranged distant from the pressure element, is bonded to the top side. The invention also relates to methods for fabricating a power semiconductor module, and for fabricating a power semiconductor arrangement comprising a power semiconductor module and a heat sink.

Abstract: A method and apparatus are provided for manufacturing a lead frame based, over-molded semiconductor package (7) with an exposed pad or power die flag (70) having multiple integrated THT heat spreader pins (71) configured for insertion into one or more vias (77) formed in a printed circuit board (78). The through hole heat spreader pins (71) may be formed as an integral part of the exposed pad (52) or may be solidly connected with the exposed pad (62).

Abstract: A manufacturing method of a semiconductor package structure includes the following steps. Firstly, a carrier having an adhesion tape is provided. Next, a plurality of chips are disposed on the adhesion tape. Then, a molding compound is dispensed on the adhesion tape, so that the molding compound covers the chips. Afterwards, a heat spreader is disposed on a plurality of chips. Then, the molding compound is solidified as an encapsulant to fix the heat spreader on the chips. After that, the carrier and the adhesion tape are removed to expose the active surfaces of the chips. Then, a redistribution layer is formed adjacent to the active surfaces of the chips. Next, a plurality of solder balls are disposed on the redistribution layer. Lastly, a plurality of packages are formed by cutting the redistribution layer, the encapsulant and the heat spreader according to the positions of the chip.

Abstract: An electronic package includes a die including a thermal interface material through which a primary heat flux path is enabled for conducting heat from the die, an organic substrate, and a thermal interposer provided between the organic substrate and the die, the thermal interposer having an area extending beyond a footprint of the die, the area including the thermal interface material, the thermal interposer conducting heat generated by the die through the thermal interface material such that an auxiliary heat flux path for conducting heat generated in the die is enabled.

Abstract: Provided is a semiconductor device including: a base plate; a thermally conductive resin layer formed on an upper surface of the base plate; an integrated layer which is formed on an upper surface of the thermally conductive resin layer, and includes an electrode and an insulating resin layer covering all side surfaces of the electrode; and a semiconductor element formed on an upper surface of the electrode, in which the integrated layer is thermocompression bonded to the base plate through the thermally conductive resin layer. This semiconductor device excels in insulating properties and reliability.

Abstract: A method of forming a package structure includes providing a plurality of dies; attaching the plurality of dies onto a heat-dissipating plate; and sawing the heat-dissipating plate into a plurality of packages, each including one of the plurality of dies and a piece of the heat-dissipating plate.

Abstract: A novel semiconductor device high in both heat dissipating property and connection reliability in mounting is to be provided. The semiconductor device comprises a semiconductor chip, a resin sealing member for sealing the semiconductor chip, a first conductive member connected to a first electrode formed on a first main surface of the semiconductor chip, and a second conductive member connected to a second electrode formed on a second main surface opposite to the first main surface of the semiconductor chip, the first conductive member being exposed from a first main surface of the resin sealing member, and the second conductive member being exposed from a second main surface opposite to the first main surface of the resin sealing member and also from side faces of the resin sealing member.

Abstract: The present invention provides a heat spreader 1 which includes a substrate 7 composed of a metal-containing material and in which a second-component connection surface 6 of the substrate 7 is provided with wettability with a solder and a solder block layer 14 is formed in at least one of respective regions, adjacent to each other, of the second-component connection surface 6 and a side surface 13.

Abstract: A circuit device including a multilayer wiring structure having an improved heat radiation performance, and a manufacturing method thereof is provided. A circuit device of the invention includes a first wiring layer and a second wiring layer laminated while interposing a first insulating layer. The first wiring layer is connected to the second wiring layer in a desired position through a connecting portion formed so as to penetrate the first insulating layer. The connecting portion includes a first connecting portion protruding in a thickness direction from the first wiring layer, and a second connecting portion protruding in the thickness direction from the second wiring layer. The first connecting portion and the second connecting portion contact each other at an intermediate portion in the thickness direction of the insulating layer.

Abstract: A three dimensional (3D) stacked chip structure with chips having on-chip heat spreader and method of forming are described. A 3D stacked chip structure comprises a first die having a first substrate with a dielectric layer formed on a front surface. One or more bonding pads and a heat spreader may be simultaneously formed in the dielectric layer. The first die is bonded with corresponding bond pads on a surface of a second die to form a stacked chip structure. Heat generated in the stacked chip structure may be diffused to the edges of the stacked chip structure through the heat spreader.

Abstract: The invention comprises a 3D chip stack with an intervening thermoelectric coupling (TEC) plate. Through silicon vias in the 3D chip stack transfer electronic signals among the chips in the 3D stack, power the TEC plate, as well as distribute heat in the stack from hotter chips to cooler chips.

Abstract: A metal thermal interface structure for dissipating heat from electronic components comprised a heat spreader lid, metal alloy that is liquid over the operating temperature range of the electronic component, and design features to promote long-term reliability and high thermal performance.

Abstract: By providing heat dissipation elements or heat pipes in temperature critical areas of a semiconductor device, enhanced performance, reliability and packing density may be achieved. The heat dissipation elements may be formed on the basis of standard manufacturing techniques and may be positioned in close proximity to individual transistor elements and/or may be used for shielding particular circuit portions.

Abstract: A semiconductor device package includes a substrate with one or more pads and at least one semiconductor device that has one or more of its electrodes electrically connected to the substrate pads. The package also includes one or more terminals in electrical connection with the substrate pads and that provide for external connection to the device.

Abstract: A semiconductor light-emitting element assembly, comprising a composite substrate, a circuit layout carrier, a connecting structure, a recess, and a semiconductor light-emitting element, is disclosed. The connecting structure is used for bonding the composite substrate with the circuit layout carrier. The recess is formed by the circuit layout carrier and extends toward the composite substrate. The semiconductor light-emitting element is deposited in the recess and electrically connected to the circuit layout carrier.

Abstract: A semiconductor device having a higher thermal dissipation efficiency includes a thermally conducting structure attached to a surface of the semiconductor device via soldering. The thermally conducting structure is essentially formed of a thermally conducting material and comprises an array of freestanding fins, studs or frames, or a grid of connected fins. A process for fabricating such a semiconductor device includes forming a thermally conducting structure on a carrier and attaching the thermally conducting structure formed on the carrier to a surface of the semiconductor device via soldering.

Abstract: A flexible electronic device excellent in heat liberation characteristics and toughness and a production method for actualizing thereof in low cost and with satisfactory reproducibility are provided. A protection film is adhered onto the surface of a substrate on which surface a thin film device is formed. Successively, the substrate is soaked in an etching solution to be etched from the back surface thereof so as for the residual thickness of the substrate to fall within the range larger than 0 ?m and not larger than 200 ?m. Then, a flexible film is adhered onto the etched surface of the substrate, and thereafter the protection film is peeled to produce a flexible electronic device.

Abstract: Flexible circuitry is populated with integrated circuitry (ICs), and contacts are distributed along the flexible circuitry to provide connection to an application environment. The flexible circuitry is disposed about a rigid substrate, placing the ICs on one or both sides of the substrate with one or more layers of integrated circuitry on one or both sides of the substrate. The substrate is preferably devised from thermally-conductive materials and one or more thermal spreaders are in thermal contact with at least some of the ICs. Optionally, as an additional thermal management feature, the module may include a high thermal conductivity thermal sink or area that is disposed proximal to higher thermal energy IC devices. In preferred embodiments, extensions from the substrate body or substrate core encourage reduced thermal variations amongst the ICs of the module while providing an enlarged surface for shedding thermal energy from the module.

Abstract: This disclosure concerns a procedure for bulk scale preparation of high aspect ratio, 2-dimensional nano platelets comprised of a few graphene layers, Gn. n may, for example, vary between about 2 to 10. Use of these nano platelets in applications such as thermal interface materials, advanced composites, and thin film coatings provide material systems with superior mechanical, electrical, optical, thermal, and antifriction characteristics.

Abstract: An enhanced heat transposer comprised is of a vapor chamber. The surface of the vapor chamber that holds the fluid comprises an array of carbon nanotubes (CNTs) that are grown in a way that enables the fluid to come into maximum contact with the CNTs. The fluid evaporates in the sealed vapor chamber when it is in touch with a hot surface. The vapor comes in contact with a hollow pin-fin structure that provides additional surface area for vapor cooling and heat transfer. The condensed vapor then drops back into the fluid container, and the cycle continues.

Abstract: To solve the problems caused by accumulation of heat generated from an integrated circuit. The integrated circuit device of the invention includes a substrate over one surface of which an integrated circuit is formed. The other surface of the substrate (a surface over which the integrated circuit is not formed) includes a depressed portion and has a larger surface area than the one surface. The depressed portion formed on the other surface of the substrate is filled with a heat sink material, or a film containing a heat sink material is formed at least over the surface of the depressed portion. Such integrated circuit devices may be provided in a multilayer structure.

Abstract: A process includes mating a first heat spreader and a second heat spreader, such that the first heat spreader at a mating surface and second heat spreader at a mating surface become parallel and adjacent. The process includes placing a first die in a first die recess of the first heat spreader, and placing a second die in a second die recess in the second heat spreader. The process includes reflowing thermal interface material between each die and respective heat spreader. Thereafter, the process includes separating the first heat spreader and the second heat spreader. A package is achieved by the process, with reduced thicknesses. The package can be disposed onto a mounting substrate. The package can be assembled into a computing system.

Abstract: A layered chip package includes: a plurality of layer portions stacked, each of the layer portions including a semiconductor chip; and a heat sink. Each of the plurality of layer portions has a top surface, a bottom surface, and four side surfaces. The heat sink has at least one first portion, and a second portion coupled to the at least one first portion. The at least one first portion is adjacent to the top surface or the bottom surface of at least one of the layer portions. The second portion is adjacent to one of the side surfaces of each of at least two of the plurality of layer portions.

Abstract: Discontinuous diamond particulate containing metal matrix composites of high thermal conductivity and methods for producing these composites are provided. The manufacturing method includes producing a thin reaction formed and diffusion bonded functionally graded interactive SiC surface layer on diamond particles. The interactive surface converted SiC coated diamond particles are then disposed into a mold and between the particles and permitted to rapidly solidify under pressure. The surface conversion interactive SiC coating on the diamond particles achieves minimal interface thermal resistance with the metal matrix which translates into good mechanical strength and stiffness of the composites and facilitates near theoretical thermal conductivity levels to be attained in the composite. Secondary working of the diamond metal composite can be performed for producing thin sheet product.

Abstract: A high power surface mount package including a thick bond line of solder interposed between the die and a heatsink, and between the die and a lead frame, wherein the lead frame has the same coefficient of thermal expansion as the heatsink. In one preferred embodiment, the heatsink and the lead frame are comprised of the same material. The package can be assembled using standard automated equipment, and does not require a weight or clip to force the parts close together, which force typically reduces the solder bond line thickness. Advantageously, the thermal stresses on each side of the die are effectively balanced, allowing for a large surface area die to be packaged with conventional and less expensive materials. One type of die that benefits from the present invention can include a transient voltage suppressor, but could include other dies generating a significant amount of heat, such as those in excess of 0.200 inches square.

Abstract: An LED package is improved in heat radiating performance. The LED package includes a package substrate having heat radiating means; a heat radiating layer arranged on the package substrate with an area at least larger than a mounting area of a light emitting diode chip to provide a horizontal heat radiating path; and an electrically-connecting structure including first and second conductive leads arranged on the heat radiating layer. The light emitting diode chip is mounted on the heat radiating layer or the first conductive lead by a heat conductive adhesive layer.

Abstract: A heat spreader is presented which can provide effective thermal management in a cost effective manner. The heat spreader includes a plurality of diamond particles arranged in a single layer surrounded by a metallic mass. The metallic mass cements the diamond particles together. The layer of diamond particles is a single particle thick. Besides the single layer of diamond particles, the metallic mass has substantially no other diamond particles therein. A thermal management system including a heat source and a heat spreader is also presented, along with methods for making and methods for use of such heat spreaders.

Abstract: A Peltier element is provided so that an electrically conductive plate forming a heat absorbing portion is in close proximity to an insulating layer and an electrically conductive plate forming a heat radiating portion is provided in close proximity to an insulating layer. The Peltier element has one end connected to a branch line branched from a power line, and has the other end electrically connected to an electrode plate. Further, the Peltier element receives from the branch line a portion of electric power supplied to a power transistor, and outputs it to the electrode plate. In other words, the Peltier element uses the portion of the electric power supplied to the power transistor, to absorb heat generated by the power transistor and radiate it toward a heat radiating plate.

Abstract: An example of a high-frequency semiconductor device includes two unit semiconductor devices. Each of the two unit semiconductor devices has a ground substrate, a high-frequency semiconductor element, an input-side matching circuit, an output-side matching circuit, a side wall member, an input terminal, and an output terminal. The ground substrate has heat-radiating property. The high-frequency semiconductor element is provided on the ground substrate. The input-side matching circuit is connected to the high-frequency semiconductor element. The output-side matching circuit is connected to the high-frequency semiconductor element. The side wall member surrounds at least the high-frequency semiconductor element. The input terminal is connected to the input-side matching circuit. The output terminal is connected to the output-side matching circuit. The two unit semiconductor devices are coupled to each other at upper edges of the side wall members.

Abstract: A cooling apparatus for a circuit module having a substrate extending axially with an IC chip of a first type and IC chips of a second type mounted thereon, comprising: a first heat spreading element disposed to form a heat conduction path with the IC chip of the first type; and a second heat spreading element disposed to form a heat conduction path with the IC chips of the second type, wherein there is at least one IC chip of the second type mounted axially away from opposite sides of the IC chip of the first type, wherein the first type of IC chip is capable of generating a larger amount of heat than the second type of IC chips, and the first heat spreading element has a higher thermal conductivity than the second heat spreading element.

Abstract: According to one aspect of the invention, a method of constructing an electronic assembly is provided. A layer of metal is formed on a backside of a semiconductor wafer having integrated formed thereon. Then, a porous layer is formed on the metal layer. A barrier layer of the porous layer at the bottom of the pores is thinned down. Then, a catalyst is deposited at the bottom of the pores. Carbon nanotubes are then grown in the pores. Another layer of metal is then formed over the porous layer and the carbon nanotubes. The semiconductor wafer is then separated into microelectronic dies. The dies are bonded to a semiconductor substrate, a heat spreader is placed on top of the die, and a semiconductor package resulting from such assembly is sealed. A thermal interface is formed on the top of the heat spreader. Then a heat sink is placed on top of the thermal interface.

Abstract: A high-speed I/O trace is part of an I/O package architecture for an integrated circuit package substrate. The integrated circuit package substrate includes an integrated heat spreader footprint on a die-side and the I/O trace to couple with an IC device to be disposed inside the IHS footprint. The I/O trace includes a pin-out terminal outside the IHS footprint to couple to an IC device to be disposed outside the IHS footprint. The high-speed I/O trace can sustain a data flow rate from a processor in a range from 5 gigabits per second (Gb/s) to 40 Gb/s.

Abstract: A composite of two or more thermal interface materials (“TIMs”) is placed between a die and a heat spreader to improve cooling of the die in an integrated circuit package. The two or more TIMs vary in heat-dissipation capability depending upon the locations of die hot spots. In an embodiment, a more thermally conductive material may be positioned over one or more die hot spots, and a less thermally conductive material may be positioned abutting and/or surrounding the more thermally conductive material. The two or more TIMs may comprise a solder and a polymer. The composite TIM may be preformed as one unit or as a plurality of units. Methods of fabrication, as well as application of the package to an electronic assembly and to an electronic system, are also described.

Abstract: A compound semiconductor device package module structure includes a heat dissipation film, a dielectric layer, a plurality of compound semiconductor dies, means for mounting the compound semiconductor dies on the heat dissipation film, and a transparent encapsulation material. The dielectric layer includes a plurality of openings formed on the heat dissipation film. The compound semiconductor dies are placed on the heat dissipation film in the openings, and adjacent two compound semiconductor dies are separated by the dielectric layer. The transparent encapsulation material covers the compound semiconductor dies.

Abstract: A high-speed I/O trace is part of an I/O package architecture for an integrated circuit package substrate. The integrated circuit package substrate includes an integrated heat spreader footprint on a die-side and the I/O trace to couple with an IC device to be disposed inside the IHS footprint. The I/O trace includes a pin-out terminal outside the IHS footprint to couple to an IC device to be disposed outside the IHS footprint. The high-speed I/O trace can sustain a data flow rate from a processor in a range from 5 gigabits per second (Gb/s) to 40 Gb/s.

Abstract: A semiconductor device includes: a substrate; a semiconductor chip with a surface facing down mounted on the substrate; a reinforcement material provided on the substrate in a peripheral region of a region on which the semiconductor chip is mounted; and a heat sink coupled to the semiconductor chip via a highly thermally conductive material. The heat sink is disposed on the semiconductor chip and the reinforcement material by being coupled to the reinforcement material via an adhesive material, and is provided with an uneven area on a side coupled to the reinforcement material.

Abstract: The present invention is directed to improving the efficiency of removing heat from semiconductor devices. In addition, the method of manufacturing the improved devices has the potential of eliminating a key step in the traditional production process where the chips are highly susceptible to mechanical damage. A semiconductor element includes a semiconductor substrate having a heat removal side and a heat producing region, and at least one superstrate semiconductor layer defining the heat producing region. The heat removal side of the semiconductor substrate includes at least one recess region which extends closer to the heat-generating region than the remainder of the heat removal surface.

Abstract: A microelectronic package is provided. The microelectronic package includes a semiconductor substrate and a die having a top surface and a bottom surface, wherein the bottom surface of the die is coupled to the semiconductor substrate. The microelectronic package also includes a nanomaterial layer disposed on the top surface of the die.

Abstract: Electrode plates acting as a heat sink are arranged to sandwich a power transistor and a diode. Electrode plates at their surfaces opposite cooling elements at a portion opposite power transistor and diode are formed to be smaller in thickness at a portion adjacent to power transistor and diode substantially at the center than at a periphery. Cooling elements are disposed geometrically along electrode plates to sandwich electrode plates.

Abstract: Embodiments of the present invention describe a bare die package and its methods of fabrication The bare die package comprises a die electrically coupled to a package substrate, and a displacement constraint. In an embodiment of the present invention, the displacement constraint is a plurality of members fixedly attached onto the package substrate and surrounds the die. When the bare die package is secured between a socket and a heat sink, the plurality of members provide structural support to the package substrate and prevent excessive substrate warpage.

Abstract: A method of making a semiconductor chip assembly includes providing a post and a base, mounting an adhesive on the base including inserting the post into an opening in the adhesive, mounting a conductive layer on the adhesive including aligning the post with an aperture in the conductive layer, then flowing the adhesive into and upward in a gap located in the aperture between the post and the conductive layer, solidifying the adhesive, then providing a conductive trace that includes a pad, a terminal and a selected portion of the conductive layer, providing a cap on the post, mounting a semiconductor device on a heat spreader that includes the post, the base and the cap, electrically connecting the semiconductor device to the conductive trace and thermally connecting the semiconductor device to the heat spreader.

Abstract: A package-on-package system includes: providing a base substrate; mounting an integrated circuit on the base substrate; positioning a stacking interposer over the integrated circuit; and forming a heat spreader base around the integrated circuit by coupling the base substrate and the stacking interposer to the heat spreader base.

Abstract: Provided is a method of manufacturing a semiconductor laser device having a light shield film comprising: forming a light emission structure by depositing a first clad layer, an active layer and a second clad layer on a substrate; depositing a light shield film and a protection film on the light emission face of the light emission structure; removing the light shield film corresponding to an area of the light emission face of the light emission structure including and above the first clad layer; and removing the protection layer.

Abstract: A chip scale package has a semiconductor MOSFET die which has a top electrode surface covered with a layer of a photosensitive liquid epoxy which is photolithographically patterned to expose portions of the electrode surface and to act as a passivation layer and as a solder mask. A solderable contact layer is then formed over the passivation layer. The individual die are mounted drain side down in a metal clip or can with the drain electrode disposed coplanar with a flange extending from the can bottom. The metal clip or drain clip has a plurality, a parallel spaced fins extending from its outwardly facing surface.

Abstract: In the semiconductor device, a control power MOSFET chip 2 is disposed on the input-side plate-like lead 5, and the drain terminal DT1 is formed on the rear surface of the chip 2, and the source terminal ST1 and gate terminal GT1 are formed on the principal surface of the chip 2, and the source terminal ST1 is connected to the plate-like lead for source 12. Furthermore, a synchronous power MOSFET chip 3 is disposed on the output-side plate-like lead 6, and the drain terminal DT2 is formed on the rear surface of the chip 3 and the output-side plate-like lead 6 is connected to the drain terminal DT2. Furthermore, source terminal ST2 and gate terminal GT2 are formed on the principal surface of the synchronous power MOSFET chip 3, and the source terminal ST2 is connected to the plate-like lead for source 13. The plate-like leads for source 12 and 13 are exposed, and therefore, it is possible to increase the heat dissipation capability of the MCM 1.