Selection Of Materials, Or Shaping, To Facilitate Cooling Or Heating, E.g., Heat Sinks (epo) Patents (Class 257/E23.101)
  • Patent number: 8188594
    Abstract: A high-speed I/O trace is part of an I/O package architecture for an integrated circuit package substrate. The integrated circuit package substrate includes an integrated heat spreader footprint on a die-side and the I/O trace to couple with an IC device to be disposed inside the IHS footprint. The I/O trace includes a pin-out terminal outside the IHS footprint to couple to an IC device to be disposed outside the IHS footprint. The high-speed I/O trace can sustain a data flow rate from a processor in a range from 5 gigabits per second (Gb/s) to 40 Gb/s.
    Type: Grant
    Filed: October 1, 2009
    Date of Patent: May 29, 2012
    Assignee: Intel Corporation
    Inventors: Sanka Ganesan, Kemal Aygun, Chandrashekhar Ramaswamy, Eric Palmer, Henning Braunisch
  • Publication number: 20120119347
    Abstract: A semiconductor device comprises at least a semiconductor module including a semiconductor chip, a heat sink thermally connected to the semiconductor chip and a seal member for covering and sealing the semiconductor chip and the heat sink in such a manner as to expose the heat radiation surface of the heat sink. The radiation surface is cooled by a refrigerant. An opening is formed in a part of the seal member as a refrigerant path through which the refrigerant flows.
    Type: Application
    Filed: January 25, 2012
    Publication date: May 17, 2012
    Applicant: DENSO CORPORATION
    Inventors: Kuniaki MAMITSU, Takanori Teshima
  • Patent number: 8174124
    Abstract: A device includes a semiconductor substrate including a front side and a backside. A through-substrate via (TSV) penetrates the semiconductor substrate. A dummy metal line is formed on the backside of the semiconductor substrate, and may be connected to the dummy TSV.
    Type: Grant
    Filed: April 8, 2010
    Date of Patent: May 8, 2012
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Yen Chiu, Hsien-Wei Chen, Ming-Fa Chen, Shin-Puu Jeng
  • Patent number: 8174113
    Abstract: Methods and associated structures of forming an indium containing solder material directly on an active region of a copper IHS is enabled. A copper indium containing solder intermetallic is formed on the active region of the IHS. The solder intermetallic improves the solder-TIM integration process for microelectronic packaging applications.
    Type: Grant
    Filed: September 17, 2008
    Date of Patent: May 8, 2012
    Assignee: Intel Corporation
    Inventors: Abhishek Gupta, Mike Boyd, Carl Deppisch, Jinlin Wang, Daewoong Suh, Brad Drew
  • Publication number: 20120098116
    Abstract: A multi-chip module (MCM) includes chip sub-modules that are fabricated as self-contained testable entities. The chip sub-modules plug into respective sockets in a frame of the MCM. Each chip sub-module may be tested before being plugged into the MCM. A chip sub-module may include an IC chip, such as a processor, mounted to an sub-module organic substrate that provides interconnects to the chip. The frame into which each chip sub-module plugs sits on a mini-card organic substrate that interconnects the chip sub-modules together. The MCM may include a downstop between the mini-card organic substrate and a system board to limit or prevent solder creep of solder connections between the mini-card organic substrate and the system board.
    Type: Application
    Filed: October 22, 2010
    Publication date: April 26, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jon Alfred Casey, John Lee Colbert, Paul Marlan Harvey, Mark Kenneth Hoffmeyer, Charles L. Reynolds
  • Patent number: 8164182
    Abstract: A semiconductor package system is provided including mounting a semiconductor chip to a substrate having a substrate opening. A first heat slug is attached to a first surface of the semiconductor chip at least partially encapsulating the semiconductor chip. A second heat slug is attached to the second surface of the semiconductor chip through the substrate opening.
    Type: Grant
    Filed: November 14, 2005
    Date of Patent: April 24, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: You Yang Ong, Zurina binti Zukiffly, Saat Shukri bin Embong
  • Patent number: 8164169
    Abstract: An embodiment of the present invention is a technique to fabricate a cover assembly. A cover has a base plate and sidewalls attached to perimeter of the base plate. The sidewalls have a height. A plurality of devices is attached to underside of the base plate. The devices have length corresponding to the height such that the devices are sealed within the cover when the cover is attached to a surface.
    Type: Grant
    Filed: November 1, 2010
    Date of Patent: April 24, 2012
    Assignee: Intel Corporation
    Inventors: Gregory M. Chrysler, Tony A. Opheim
  • Patent number: 8159066
    Abstract: A semiconductor package having a heat dissipation member capable of efficiently conveying excess heat away from semiconductor chips is presented. The semiconductor package includes a semiconductor chip, through-electrodes, and a heat dissipation member. The semiconductor chip has a first surface, a second surface facing away from the first surface, and bonding pads which are disposed on the first surface. The through-electrodes are electrically connected with the bonding pads and passing through the first and second surfaces of the semiconductor chip, and protrude outward from the second surface. The heat dissipation member faces the second surface of the semiconductor chip and is coupled to the through-electrodes.
    Type: Grant
    Filed: December 16, 2009
    Date of Patent: April 17, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Seung Taek Yang
  • Publication number: 20120086117
    Abstract: A package embedded with a chip and a method of fabricating the package of embedded chip. The package of embedded chip includes a dielectric layer having a first surface and a second surface opposing the first surface; a plurality of conductive pillars formed in the dielectric layer and exposed from the second surface of the dielectric layer; a chip embedded in the dielectric layer; a circuit layer formed on the first surface of the dielectric layer; a plurality of conductive blind vias formed in the dielectric layer, allowing the circuit layer to be electrically connected via the conductive blind vias to the chip and each of the conductive pillars; and a first solder mask layer formed on the first surface of the dielectric layer and the circuit layer, thereby using conductive pillars to externally connect with other electronic devices as required to form a stacked structure. Therefore, the manufacturing process can be effectively simplified.
    Type: Application
    Filed: December 10, 2010
    Publication date: April 12, 2012
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chiang-Cheng Chang, Hsin-Yi Liao, Shih-Kuang Chiu
  • Publication number: 20120080785
    Abstract: In some embodiments, a semiconductor cooling apparatus includes a monolithic array of cooling elements. Each cooling element of the monolithic array of cooling elements is configured to thermally couple to a respective semiconductor element of an array of semiconductor elements. At least two of the semiconductor elements have a different height and each cooling element independently flexes to conform to the height of the respective semiconductor element.
    Type: Application
    Filed: October 1, 2010
    Publication date: April 5, 2012
    Inventors: Scott T. Johnson, Shadi S. Merhi
  • Publication number: 20120075807
    Abstract: A method of manufacturing is provided that includes placing a thermal management device in thermal contact with a first semiconductor chip of a semiconductor chip device. The semiconductor chip device includes a first substrate coupled to the first semiconductor chip. The first substrate has a first aperture. At least one of the first semiconductor chip and the thermal management device is at least partially positioned in the first aperture.
    Type: Application
    Filed: September 24, 2010
    Publication date: March 29, 2012
    Inventors: Gamal Refai-Ahmed, Bryan Black, Michael Z. Su
  • Patent number: 8138105
    Abstract: A method that is performed for heat treating a semiconductor wafer in a process chamber, as an intermediate part of an overall multi-step technique for processing the wafer, includes applying an energy transfer layer to at least a portion of the wafer, and exposing the wafer to an energy source in the process chamber in a way which subjects the wafer to a thermal profile such that the energy transfer layer influences at least one part of the thermal profile. The thermal profile has at least a first elevated temperature event. The method further includes, in time relation to the thermal profile, removing the energy transfer layer in the process chamber at least sufficiently for subjecting the wafer to a subsequent step. An associated intermediate condition of the wafer is described.
    Type: Grant
    Filed: December 5, 2009
    Date of Patent: March 20, 2012
    Assignee: Mattson Technology, Inc.
    Inventor: Paul J. Timans
  • Patent number: 8138597
    Abstract: A semiconductor assembly includes a first subassembly comprising a heat sink and a first patterned polymer layer disposed on a surface of the heat sink to define an exposed portion of the first surface. The exposed portion of the first surface extends radially inward along the heat sink surface from the first layer. The subassembly also includes a second patterned polymer layer disposed on a radially outer portion of the first patterned polymer layer. The first and second layers define a cell for accommodating a power semiconductor die. Solder material is disposed on the exposed portion of the heat sink surface and in the cell. A power semiconductor die is located within the cell on a radially inward portion of the first layer and thermally coupled to the heat sink by the solder material.
    Type: Grant
    Filed: November 4, 2010
    Date of Patent: March 20, 2012
    Assignee: Vishay General Semiconductor LLC
    Inventors: Wan-Lan Chiang, Kuang Hann Lin, Chih-Ping Peng
  • Patent number: 8138529
    Abstract: An electronic component includes a high voltage switching transistor encased in a package. The high voltage switching transistor comprises a source electrode, a gate electrode, and a drain electrode all on a first side of the high voltage switching transistor. The source electrode is electrically connected to a conducting structural portion of the package. Assemblies using the abovementioned transistor with another transistor can be formed, where the source of one transistor can be electrically connected to a conducting structural portion of a package containing the transistor and a drain of the second transistor is electrically connected to the second conductive structural portion of a package that houses the second transistor. Alternatively, the source of the second transistor is electrically isolated from its conductive structural portion, and the drain of the second transistor is electrically isolated from its conductive structural portion.
    Type: Grant
    Filed: November 2, 2009
    Date of Patent: March 20, 2012
    Assignee: Transphorm Inc.
    Inventor: Yifeng Wu
  • Publication number: 20120049339
    Abstract: A semiconductor package structure including a substrate, a first chip, a second chip, and an interposer is provided. The substrate has a carrying surface and an opposite bottom surface. The first chip disposed on the carrying surface has a first surface and an opposite second surface. The second surface faces the substrate. The first chip has a plurality of through silicon vias (TSVs) and a plurality of first pads and second pads on the first surface. The first pads are electrically connected to the corresponding TSVs. The TSVs are electrically connected to the substrate. The second chip disposed above the first chip exposes a portion of the first surface. The second chip is electrically connected to the corresponding TSVs. The interposer is disposed on the first surface. Top surfaces of the interposer and the second chip are substantially aligned with each other. The interposer is bonded to the second pads.
    Type: Application
    Filed: October 19, 2010
    Publication date: March 1, 2012
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Meng-Jen Wang
  • Patent number: 8125077
    Abstract: A semiconductor package includes an encapsulant, a semiconductor device within the encapsulant, and one or more terminals for electrically coupling the semiconductor device to a node exterior to the package. The package further includes bonding means coupling the semiconductor device to the one or more terminals. The semiconductor package is configured to dissipate heat through a top surface of the package. To directly dissipate heat via the top surface of the package, a thermally conductive layer is coupled to the semiconductor device, and the layer is exposed at a surface of the package.
    Type: Grant
    Filed: August 25, 2010
    Date of Patent: February 28, 2012
    Assignee: Utac Thai Limited
    Inventors: Saravuth Sirinorakul, Somchai Nondhasitthichai
  • Patent number: 8125076
    Abstract: A semiconductor package system is provided including: providing a substrate having substrate wiring and a cavity provided therein with a heat sink foil closing off the cavity; attaching a semiconductor die in the cavity to the heat sink foil; and bonding the semiconductor die to the substrate wiring.
    Type: Grant
    Filed: November 10, 2005
    Date of Patent: February 28, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Gwang Kim, Koo Hong Lee
  • Patent number: 8120164
    Abstract: A semiconductor chip package and printed circuit board assembly including the same which have a variable mounting orientation include a semiconductor chip disposed on a first surface of an insulating substrate, connectors symmetrically disposed at respective first and opposite second sides of the insulating substrate, a plurality of input/output connecting leads and power connecting leads electrically connected by connecting members to a plurality of internal circuits of the semiconductor chip, at least two internal circuits of the plurality of internal circuits being substantially similar circuits, and a radiating pad disposed on a second opposite surface of the insulating substrate and which is electrically connected to the semiconductor chip.
    Type: Grant
    Filed: November 30, 2007
    Date of Patent: February 21, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eun-woo Jeong, Yong-gwang Won
  • Patent number: 8120123
    Abstract: A semiconductor device, and a method of forming the same, includes forming a cell bit line pattern and a peripheral gate pattern on a semiconductor substrate. The cell bit line pattern may be formed on an inactive region adjacent to a cell active region of the semiconductor substrate. The peripheral gate pattern may be disposed on a peripheral active region of the semiconductor substrate. A cell contact plug may be formed between the cell bit line pattern and the cell active region. A peripheral contact plug may be formed on the peripheral active region on a side of the peripheral gate pattern. An insulating layer may be formed to expose top surfaces of the cell bit line pattern, the peripheral gate pattern, and the cell and peripheral contact plugs at substantially the same level.
    Type: Grant
    Filed: April 1, 2010
    Date of Patent: February 21, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Makoto Yoshida, Hyeong-Sun Hong, Kye-Hee Yeom, Dae-Ik Kim, Yong-Il Kim
  • Patent number: 8115301
    Abstract: Methods for fabricating flip-chips are disclosed. In an exemplary method, a flip-chip is mounted, active-surface downward, onto a substrate such that a back-side of the flip-chip is facing upward and electrical connections are made between the chip and an upward-facing surface of the substrate. An adhesive is applied to selected regions not occupied by the flip-chip. A heat-spreader is applied to contact the applied adhesive without contacting the back-side of the flip-chip, leaving a gap between the heat-spreader and the back-side of the flip-chip. The heat-spreader defines at least one through-hole that, when the heat-spreader is placed, is within a perimeter of the flip-chip. The adhesive is cured, and a thermal-insulating material (TIM) is applied through the at least one through-hole so as to fill the gap with the TIM. The methods substantially reduce the probability of die damage that otherwise occurs during attachment of heat-spreaders.
    Type: Grant
    Filed: November 17, 2006
    Date of Patent: February 14, 2012
    Assignee: STATS ChipPAC, Inc.
    Inventors: KyungOe Kim, YoungJoon Kim, HyunSoo Shin
  • Patent number: 8106501
    Abstract: A semiconductor die package. The semiconductor die package comprises a semiconductor die and a molded clip structure comprising a clip structure and a first molding material covering at least a portion of the clip structure. The first molding material exposes an outer surface of the clip structure. The clip structure is electrically coupled to the semiconductor die. The semiconductor die package further comprises a leadframe structure comprising a die attach pad and a plurality of leads extending from the die attach pad. The semiconductor die is on the die attach pad of the leadframe structure. A second molding material covers at least a portion of the semiconductor die and the leadframe structure. The semiconductor die package also includes a heat slug and a thermally conductive material coupling the heat slug to the exposed surface of the clip structure.
    Type: Grant
    Filed: December 12, 2008
    Date of Patent: January 31, 2012
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Maria Clemens Y. Quinones, Maria Cristina B. Estacio
  • Patent number: 8093715
    Abstract: A method of forming a well-anchored carbon nanotube (CNT) array, as well as thermal interfaces that make use of CNT arrays to provide very high thermal contact conductance. A thermal interface is formed between two bodies by depositing a continuous array of carbon nanotubes on a first of the bodies so that, on mating the bodies, the continuous array is between surface portions of the first and second bodies. The thermal interface preferably includes a multilayer anchoring structure that promotes anchoring of the continuous array of carbon nanotubes to the first body. The anchoring structure includes a titanium bond layer contacting the surface portion of the first body, and an outermost layer with nickel or iron catalytic particles from which the continuous array of carbon nanotubes are nucleated and grown. Additional thermal interface materials (TIM's) can be used in combination with the continuous array of carbon nanotubes.
    Type: Grant
    Filed: August 4, 2006
    Date of Patent: January 10, 2012
    Assignee: Purdue Research Foundation
    Inventors: Jun Xu, Timothy S. Fisher
  • Patent number: 8093714
    Abstract: A chip assembly may comprise a substrate having a top surface and a bottom surface. The chip assembly may comprise a first die having a circuit surface and a connecting surface, the circuit surface comprising one or more integrated circuits. The chip assembly may comprise a chip-scale frame having an inside surface, an outside surface, and a well region, the well region having an opening within the inside surface, the well region having a wall, the well region housing the first die, the first die attached to the wall by a first coupling mechanism, the inside surface coupled to the top surface of the substrate by a second coupling mechanism. The chip assembly may comprise a heat sink coupled to the outside surface of the chip-scale frame using a third coupling mechanism.
    Type: Grant
    Filed: December 10, 2009
    Date of Patent: January 10, 2012
    Assignee: Semtech Corporation
    Inventors: Andrew J. Bonthron, Darren Jay Walworth
  • Publication number: 20120001316
    Abstract: A semiconductor device package is formed of DBC in which thinned MOSgated and/or diode die are soldered to the bottom of an etched depression in the upper conductive layer. A via in the insulation layer of the DBC is filled with a conductive material to form a resistive shunt. Plural packages may be formed in a DBC card and may be separated individually or in clusters. The individual packages are mounted in various arrays on a support DBC board and heat sink. Integrated circuits may be mounted on the assembly and connected to the die for control of the die conduction.
    Type: Application
    Filed: September 9, 2011
    Publication date: January 5, 2012
    Inventor: Henning M. Hauenstein
  • Patent number: 8089085
    Abstract: An LED assembly can include a heat sink base, at least one LED die attached to the heat sink base, and a lens. One or more layers of phosphor can be formed upon the lens. A heat sink, such as a finned heat sink, can attach the heat sink base to the lens. Heat from the LED die can flow through the heat sink base to the heat sink, from which the heat can be dissipated. Similarly, heat from phosphors can flow through the lens to the heat sink, from which the heat can be dissipated. By removing heat from the LED die, more current can be used to drive the LED die, thus providing brighter light. By removing heat from the phosphors, desired colors can be more reliably provided.
    Type: Grant
    Filed: February 26, 2009
    Date of Patent: January 3, 2012
    Assignee: Bridgelux, Inc.
    Inventor: Wei Shi
  • Patent number: 8089086
    Abstract: Light sources are disclosed herein. An embodiment of a light sources comprises a substrate having a first surface and a second surface located opposite the first surface. At least one first electrically conductive layer is affixed to the first surface of the substrate and partially covering the first surface of the substrate. At least one second electrically conductive layer is affixed to the first surface of the substrate and partially covering the first surface of the substrate. A light emitter is affixed to the first surface of the substrate in an area not covered by either of the at least one first electrically conductive layer or the at least one second electrically conductive layer.
    Type: Grant
    Filed: October 19, 2009
    Date of Patent: January 3, 2012
    Assignee: Avago Technologies ECBU IP (Singapore) Pte. Ltd.
    Inventors: Siang Ling Oon, Chin Nyap Tan, Kee Yean Ng
  • Publication number: 20110316144
    Abstract: A heat sink includes a first adhesive layer, and a heat dissipation layer disposed on the first adhesive layer, and has ventilation ports that extend therethrough including through the first adhesive layer and the heat dissipation layer. The heat sink forms an outermost part of a semiconductor package. Thus, when the heat sink is bonded via its adhesive layer to underlying structure during a manufacturing process, the ventilation ports allow air to pass therethrough. As a result, air is not trapped in the form of bubbles between the heat sink and the underlying structure.
    Type: Application
    Filed: June 13, 2011
    Publication date: December 29, 2011
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-Wook Yoo, Kyoung-Sei Choi, Eun-Seok Cho, Mi-Na Choi, Hee-Jung Hwang, Se-Ran Bae
  • Patent number: 8080871
    Abstract: One aspect of the invention includes a copper substrate; a catalyst on top of the copper substrate surface; and a thermal interface material that comprises a layer containing carbon nanotubes that contacts the catalyst. The carbon nanotubes are oriented substantially perpendicular to the surface of the copper substrate. A Raman spectrum of the layer containing carbon nanotubes has a D peak at ˜1350 cm?1 with an intensity ID, a G peak at ˜1585 cm?1 with an intensity IG, and an intensity ratio ID/IG of less than 0.7 at a laser excitation wavelength of 514 nm. The thermal interface material has: a bulk thermal resistance, a contact resistance at an interface between the thermal interface material and the copper substrate, and a contact resistance at an interface between the thermal interface material and a solid-state device. A summation of these resistances has a value of 0.06 cm2K/W or less.
    Type: Grant
    Filed: July 22, 2008
    Date of Patent: December 20, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Carlos Dangelo, Ephraim Suhir, Subrata Dey, Barbara Wacker, Yuan Xu, Arthur Boren, Darin Olsen, Yi Zhang, Peter Schwartz, Bala Padmakumar
  • Patent number: 8076771
    Abstract: In order to reduce a thermal stress applied by a metal cap to a semiconductor chip: a semiconductor chip (2) is bonded to a flat portion (11) of a metal cap (1); side wall portions of the metal cap (1) serve as external connection terminals (13); and a slit (7) is formed in the metal cap (1) so as to cross the semiconductor chip (2), so a bonding region between the semiconductor chip (2) and the metal cap (1) is divided into small bonding regions to reduce thermal stresses applied to the respective bonding regions. Therefore, peeling can be prevented in respective bonding regions, whereby a small-size semiconductor device in which the semiconductor chip is bonded to the metal cap with improved bonding reliability is obtained.
    Type: Grant
    Filed: June 26, 2008
    Date of Patent: December 13, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Hideko Ando
  • Patent number: 8076772
    Abstract: A printed circuit board, a memory module having the same, and a fabrication method thereof. The printed circuit board includes an interconnection substrate on which electronic components are mounted and in which a plurality of signal lines are arranged. The signal lines are electrically coupled to the electronic components. A heat sink is disposed on one surface of the interconnection substrate to dissipate heat of the electronic components, and in which no signal lines are arranged. The printed circuit board includes a bending substrate coupling the interconnection substrate to the heat sink, and formed of a flexible material configured to be bent.
    Type: Grant
    Filed: June 25, 2008
    Date of Patent: December 13, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyung-Mo Hwang, Yong-Hyun Kim, Jung-Chan Cho, Hyun-Seok Choi
  • Publication number: 20110298110
    Abstract: A semiconductor device has a thermally conductive layer with a plurality of openings formed over a temporary carrier. The thermally conductive layer includes electrically non-conductive material. A semiconductor die has a plurality of bumps formed over contact pads on the die. The semiconductor die is mounted over the thermally conductive layer so that the bumps are disposed at least partially within the openings in the thermally conductive layer. An encapsulant is deposited over the die and thermally conductive layer. The temporary carrier is removed to expose the bumps. A first interconnect structure is formed over the encapsulant, semiconductor die, and bumps. The bumps are electrically connected to the first interconnect structure. A heat sink or shielding layer can be formed over the semiconductor die. A second interconnect structure can be formed over the encapsulant and electrically connected to the first interconnect structure through conductive vias formed in the encapsulant.
    Type: Application
    Filed: June 4, 2010
    Publication date: December 8, 2011
    Applicant: STATS CHIPPAC, LTD.
    Inventors: Reza A. Pagaila, Yaojian Lin, Jun Mo Koo
  • Patent number: 8067834
    Abstract: In various embodiments, semiconductor components and methods to manufacture these components are disclosed. In one embodiment, a method to manufacture a semiconductor component is disclosed. The semiconductor includes a heat sink and a semiconductor die that has a first terminal on a top surface of the semiconductor die, a second terminal on the top surface of the die, and a third terminal on the bottom surface of the die. The method includes attaching a first portion of a leadframe structure to the first terminal of the semiconductor die. The method further includes attaching the second terminal of the semiconductor die to the heat sink after the attaching of the first portion of the leadframe structure to the first terminal of the semiconductor die, wherein the leadframe structure is spaced apart from the heat sink and is electrically isolated from the heat sink. Other embodiments are described and claimed.
    Type: Grant
    Filed: August 21, 2007
    Date of Patent: November 29, 2011
    Assignee: HVVi Semiconductors, Inc.
    Inventor: Daniel D. Moline
  • Publication number: 20110285007
    Abstract: A semiconductor device has a first semiconductor die stacked over a second semiconductor die which is mounted to a temporary carrier. A plurality of bumps is formed over an active surface of the first semiconductor die around a perimeter of the second semiconductor die. An encapsulant is deposited over the first and second semiconductor die and carrier. A plurality of conductive vias is formed through the encapsulant around the first and second semiconductor die. A portion of the encapsulant and a portion of a back surface of the first and second semiconductor die is removed. An interconnect structure is formed over the encapsulant and the back surface of the first or second semiconductor die. The interconnect structure is electrically connected to the conductive vias. The carrier is removed. A heat sink or shielding layer can be formed over the encapsulant and first semiconductor die.
    Type: Application
    Filed: May 24, 2010
    Publication date: November 24, 2011
    Applicant: STATS CHIPPAC, LTD.
    Inventors: HeeJo Chi, NamJu Cho, JunWoo Myung
  • Publication number: 20110285010
    Abstract: An electric power converter includes: a heat sink having a heat receiving surface; a semiconductor module including a metal plate having a heat radiation surface, a switching element on the metal plate opposite to the heat radiation surface, and a resin member covering a part of the metal plate and the switching element; a heat radiation member between the heat receiving surface and the semiconductor module for transmitting heat of the switching element to the heat receiving surface via the metal plate. The heat receiving surface includes a concavity, and the heat radiation surface includes a convexity. The heat radiation member has a predetermined area sandwiched between the concavity and the convexity.
    Type: Application
    Filed: May 19, 2011
    Publication date: November 24, 2011
    Applicant: DENSO CORPORATION
    Inventor: Syuhei Miyachi
  • Patent number: 8062933
    Abstract: A heat dissipating package structure includes a chip carrier; a semiconductor chip mounted and electrically connected to the chip carrier; an encapsulant formed on the chip carrier and for encapsulating the chip, with a non-active surface of the chip being exposed from the encapsulant; and a heat spreader having a hollow portion and attached to the encapsulant, wherein the chip is received in the hollow portion and the non-active surface of the chip is completely exposed to the hollow portion, such that heat generated by the chip can be directly dissipated out of the package structure. The present invention also provides a method for fabricating the heat dissipating package structure.
    Type: Grant
    Filed: December 12, 2007
    Date of Patent: November 22, 2011
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chien-Ping Huang, Cheng-Hsu Hsiao
  • Publication number: 20110278717
    Abstract: A semiconductor device has a semiconductor die with a plurality of bumps formed over a surface of the first semiconductor die. A penetrable adhesive layer is formed over a temporary carrier. The adhesive layer can include a plurality of slots. The semiconductor die is mounted to the carrier by embedding the bumps into the penetrable adhesive layer. The semiconductor die and interconnect structure can be separated by a gap. An encapsulant is deposited over the first semiconductor die. The bumps embedded into the penetrable adhesive layer reduce shifting of the first semiconductor die while depositing the encapsulant. The carrier is removed. An interconnect structure is formed over the semiconductor die. The interconnect structure is electrically connected to the bumps. A thermally conductive bump is formed over the semiconductor die, and a heat sink is mounted to the interconnect structure and thermally connected to the thermally conductive bump.
    Type: Application
    Filed: May 13, 2010
    Publication date: November 17, 2011
    Applicant: STATS CHIPPAC, LTD.
    Inventors: Reza A. Pagaila, Yaojian Lin, Jun Mo Koo
  • Patent number: 8053888
    Abstract: A system for clamping a heat sink that prevents excessive clamping force is provided. The system may include a heat sink, a semiconductor device, a printed circuit board, and a cover. The semiconductor device may be mounted onto the circuit board and attached to the cover. The heat sink may be designed to interface with the semiconductor device to transfer heat away from the semiconductor device and dissipate the heat into the environment. Accordingly, the heat sink may be clamped into a tight mechanical connection with the semiconductor device to minimize thermal resistance between the semiconductor device and the heat sink. To prevent excessive clamping force from damaging the semiconductor device, loading columns may extend between the cover and the heat sink.
    Type: Grant
    Filed: December 1, 2006
    Date of Patent: November 8, 2011
    Assignee: Harman International Industries, Incorporated
    Inventor: Greg Mlotkowski
  • Patent number: 8049330
    Abstract: A structure of light emitting diode (LED) wafer-level chip scale packaging (WL-CSP) is disclosed. The process of making the same is also provided in this invention. The LED CSP utilizes the through hole metal filling to enhance heat conduction between the LED die and its carrier substrate. The CSP structure is achieved by bonding pre-processed through-hole-filling carrier substrate against the flip-chip LED wafer.
    Type: Grant
    Filed: November 23, 2005
    Date of Patent: November 1, 2011
    Assignee: Industrial Technology Research Institute
    Inventors: Ra-Min Tain, Wei-Chung Lo, Li-Cheng Shen
  • Publication number: 20110260303
    Abstract: A semiconductor device has a thermally-conductive frame and interconnect structure formed over the frame. The interconnect structure has an electrical conduction path and thermal conduction path. A first semiconductor die is mounted to the electrical conduction path and thermal conduction path of the interconnect structure. A portion of a back surface of the first die is removed by grinding. An EMI shielding layer can be formed over the first die. The first die can be mounted in a recess of the thermally-conductive frame. An opening is formed in the thermally-conductive frame extending to the electrical conduction path of the interconnect structure. A second semiconductor die is mounted over the thermally-conductive frame opposite the first die. The second die is electrically connected to the interconnect structure using a bump disposed in the opening of the thermally-conductive frame.
    Type: Application
    Filed: April 23, 2010
    Publication date: October 27, 2011
    Applicant: STATS CHIPPAC, LTD.
    Inventors: Reza A. Pagaila, Yaojian Lin
  • Publication number: 20110254148
    Abstract: The invention is to provide a semiconductor apparatus configured to position a semiconductor device reliably and easily without having a protruding portion formed in the bottom surface of the semiconductor device in the semiconductor apparatus. A semiconductor apparatus is fabricated by attaching a semiconductor device of a surface mount package type and a wiring member to a heat sink. A fitting portion in which the semiconductor device is fit is provided to the wiring member, so that the semiconductor device is positioned by fitting the semiconductor device into the fitting portion provided to the wiring member. According to the semiconductor apparatus of the invention, it becomes possible to position the semiconductor device at a high degree of accuracy.
    Type: Application
    Filed: October 20, 2010
    Publication date: October 20, 2011
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Masaki KATO, Masahiko FUJITA, Kazuyasu SAKAMOTO
  • Patent number: 8039942
    Abstract: A ball grid array package stacking system includes: providing a base substrate; coupling an integrated circuit to the base substrate; coupling a stacking substrate over the base substrate; mounting a heat spreader, having an access port, around the base substrate and the stacking substrate; and coupling a stacked integrated circuit to the stacking substrate through the access port.
    Type: Grant
    Filed: June 17, 2008
    Date of Patent: October 18, 2011
    Assignee: Stats Chippac Ltd.
    Inventor: Jong-Woo Ha
  • Publication number: 20110241199
    Abstract: Some embodiments of the invention provide a programmable system in package (“PSiP”). The PSiP includes a single IC housing, a substrate and several IC's that are arranged within the single IC housing. At least one of the IC's is a configurable IC. In some embodiments, the configurable IC is a reconfigurable IC that can reconfigure more than once during run time. In some of these embodiments, the reconfigurable IC can be reconfigured at a first clock rate that is faster (i.e., larger) than the clock rates of one or more of the other IC's in the PSiP. The first clock rate is faster than the clock rate of all of the other IC's in the PSiP in some embodiments.
    Type: Application
    Filed: April 1, 2011
    Publication date: October 6, 2011
    Inventor: Steven Teig
  • Patent number: 8030762
    Abstract: An LED package having an anodized insulation layer which increases heat radiation effect to prolong the lifetime LEDs and maintains high luminance and high output, and a method therefor. The LED package includes an Al substrate having a reflecting region and a light source mounted on the substrate and connected to patterned electrodes. The package also includes an anodized insulation layer formed between the patterned electrodes and the substrate and a lens covering over the light source of the substrate. The Al substrate provides superior heat radiation effect of the LED, thereby significantly increasing the lifetime and light emission efficiency of the LED.
    Type: Grant
    Filed: April 5, 2007
    Date of Patent: October 4, 2011
    Assignee: Samsung LED Co., Ltd.
    Inventors: Young Ki Lee, Seog Moon Choi, Sang Hyun Shin
  • Patent number: 8030761
    Abstract: A chip package includes a carrier having a first and a second major surface. The first major surface includes an active region surrounded by an inactive region. The chip package includes contact pads in the active region for mating with chip contacts of a chip. A support structure is disposed on the inactive region of the first major surface. The support structure forms a dam that surrounds the active region. When a chip or chip stack is mounted in the active region, spacing exists between the dam and the chip or chip stack. The spacing creates convention paths for heat dissipation.
    Type: Grant
    Filed: May 23, 2008
    Date of Patent: October 4, 2011
    Assignee: United Test and Assembly Center Ltd.
    Inventors: Ravi Kanth Kolan, Hao Liu, Chin Hock Toh
  • Patent number: 8030756
    Abstract: A plastic ball grid array semiconductor package employs a metal heat spreader having supporting arms embedded in the molding cap, in which the embedded supporting arms are not directly affixed to the substrate or in which any supporting arm that is affixed to the substrate is affixed using a resilient material such as an elastomeric adhesive. Also, a process for forming the package includes steps of placing the heat spreader in a mold cavity, placing the substrate over the mold cavity such that the die support surface of the substrate contacts the supporting arms of the heat spreader, and injecting the molding material into the cavity to form the molding cap. The substrate is positioned in register over the mold cavity such that as the molding material hardens to form the mold cap the embedded heat spreader becomes fixed in the appropriate position in relation to the substrate.
    Type: Grant
    Filed: April 6, 2007
    Date of Patent: October 4, 2011
    Assignee: Chippac, Inc.
    Inventors: Taekeun Lee, Flynn Carson, Marcos Karnezos
  • Patent number: 8030760
    Abstract: A semiconductor apparatus includes a semiconductor device, a cooler of a forced cooling type, and a heat mass. Heat generated in the semiconductor device is conducted to the cooler. The heat mass comes into junction with the semiconductor device with solder so as to be thermally combined with the semiconductor device. The heat mass functions also as an electrode.
    Type: Grant
    Filed: December 4, 2007
    Date of Patent: October 4, 2011
    Assignee: Kabushiki Kaisha Toyota Jidoshokki
    Inventors: Keiji Toh, Hidehito Kubo, Masahiko Kimbara, Haruo Takagi, Daizo Kamiyama
  • Patent number: 8030758
    Abstract: A semiconductor module (10) includes a heat sink (1), an electronic component (2), a semiconductor device (3), and a thermally-conductive sheet member (4). The thermally-conductive sheet member (4) covers a part of the semiconductor device (3) and has a lower part (4b) and a side part (4c). The lower part (4b) is in contact with a mounting face (11a) of the heat sink (1). The side part (4c) extends from the lower part (4b) and covers a first side surface (3c) of the semiconductor device (3). The electronic component (2) is disposed across the side part (4c) of the thermally-conductive sheet member (4) from the semiconductor device (3).
    Type: Grant
    Filed: September 13, 2007
    Date of Patent: October 4, 2011
    Assignee: Panasonic Corporation
    Inventor: Makoto Kitabatake
  • Patent number: 8022531
    Abstract: An integrated circuit package system includes a substrate having an integrated circuit die thereon; a heat slug having a tie bar, the tie bar having characteristics of singulation from an adjacent heat slug; and an encapsulant molded on the substrate, the heat slug, and the integrated circuit die includes the encapsulant which fills all of the space between the integrated circuit die and the heat slug.
    Type: Grant
    Filed: September 13, 2010
    Date of Patent: September 20, 2011
    Assignee: STATS ChipPAC Ltd.
    Inventors: Kyungsic Yu, Tae Keun Lee, Youngnam Choi
  • Patent number: 8022532
    Abstract: An interposer and a semiconductor device including the interposer, which can prevent thermal warpage of an insulative substrate. The interposer is provided with a semiconductor chip in a semiconductor device and may be disposed between the semiconductor chip and a mount board. The interposer includes: a substrate of an insulative resin; an island on one surface of the substrate to be bonded to a rear surface of the chip; a thermal pad on the other surface opposite the one surface opposed to the island with the intervention of the substrate; and a thermal via extending through the substrate from the one surface to the other surface to thermally connect the island to the thermal pad.
    Type: Grant
    Filed: June 2, 2006
    Date of Patent: September 20, 2011
    Assignee: Rohm Co., Ltd.
    Inventors: Yasumasa Kasuya, Sadamasa Fujii, Motoharu Haga
  • Publication number: 20110215457
    Abstract: In a stack of chips which each include active circuit regions, a plurality of through-silicon via (TSV) structures are formed for thermally conducting heat from the multi-chip stack by patterning, etching and filling with thermally conductive material a plurality of TSV openings in the multi-chip stack, including a first larger TSV opening that extends through substantially the entirety of the multi-chip stack without penetrating any active circuit region, and a second smaller TSV opening that extends down to but not through an active circuit region.
    Type: Application
    Filed: March 3, 2010
    Publication date: September 8, 2011
    Inventor: Changyok Park