Abstract: A switching element substrate for a liquid crystal display device for transmissive display includes an insulating substrate, and a plurality of switching elements formed on one of surfaces of the insulating substrate. A transmitting region is defined on an exposed part of the other surface of the insulating substrate. Each of the switching elements includes a monocrystalline silicon layer.

Abstract: A capacitor includes a lower electrode; a dielectric layer formed on a predetermined portion of the lower electrode; an upper electrode formed on the dielectric layer; a hard mask pattern formed on the upper electrode; and an isolation layer having a shape of a spacer, formed on one sidewall of the hard mask pattern, the upper electrode, and the dielectric layer.

Abstract: An integrated circuit includes a substrate including active circuitry fabricated on the substrate and a cross-point memory array formed above the substrate. The cross-point memory array can include conductive array lines arranged in different directions, and re-writable memory cells. Further, the integrated circuit can also include a memory access circuit configured to perform data operations on the cross-point memory array. The integrated circuit can include a cross-point memory array interface layer positioned between the substrate and the cross-point array and including conductive paths configured to electrically couple portions of the memory access circuit with a subset of the conductive array lines. At least one layer of cross-point memory arrays can be formed over the substrate. The memory cells can be two-terminal memory cells that store data as a plurality of conductivity profiles (e.g., resistive states) that can be non-destructively determined by applying a read voltage across the terminals.

Abstract: A microstructure includes a first structural layer and a second structural layer which faces the first structural layer with a space interposed therebetween and is partially fixed to the first structural layer. At least one of the first structural layer and the second structural layer can be displaced. Further, opposed surfaces of the first structural layer and the second structural layer are different in roughness.

Abstract: A light emitting diode is disclosed that includes an active region and a plurality of exterior surfaces. A light enhancement feature is present on at least portions of one of the exterior surfaces of the diode, with the light enhancement feature being selected from the group consisting of shaping and texturing. A light enhancement feature is present on at least portions of each of the other exterior surfaces of the diode, with these light enhancement features being selected from the group consisting of shaping, texturing, and reflectors.

Abstract: The images sensor includes a readout circuit capacitatively coupled to a memory circuit. The readout circuit includes: (i) a photon detector to receive a plurality of photons and to provide a charge signal corresponding to the received photons, (ii) a resettable integrator that is reset multiple times over a single exposure time and provides an analog representation of the incident photons during the last integration cycle, and (iii) a comparator that monitors the integrator output and generates a reset pulse when the integrator reaches a built-in threshold value. The memory circuit includes: (i) a receiver circuit that detects the output of the digital driver in the front-end readout circuit via capacitive coupling and generates a digital voltage pulse for each received signal, and (ii) a digital counting memory to count the received pulses to provide a coarse digital representation of how many times the integrator is reset.

Abstract: The present invention provides a high speed and low power consumption LSI operable in a wide temperature range in which a MOS transistor having back gates is used specifically according to operating characteristics of a circuit. In the LSI, an FD-SOI structure having an embedded oxide film layer is used and a lower semiconductor region of the embedded oxide film layer is used as a back gate. A voltage for back gates in the logic circuits having a small load in the logic circuit block is controlled in response to activation of the block from outside of the block. Transistors, in which the gate and the back gate are connected to each other, are used for the circuit generating the back gate driving signal, and logic circuits having a heavy load such as circuit block output section, and the back gates are directly controlled according to the gate input signal.

Abstract: A process for manufacturing a printing head is able to maintain an appropriate connection between a substrate and flying leads. The process includes a connecting step of connecting electric connection terminals of a substrate and flying leads provided on an electric wiring basic material and a mounting step of mounting a unit consisting of the electric wiring base material and the substrate connected together, on a printing head main body. During the connecting step, the substrate and each flying lead are electrically connected together with a predetermined distance between them. During the mounting step, the unit is fixed to the printing head main body so that the distance between each of the electric connection terminals of the substrate and the electric wiring base material is shorter than the predetermined distance. This forms a slack shape of each flying lead.

Abstract: Structures and method for reducing junction leakage in semiconductor devices. The die can include a substrate having a cut edge, a first region of first conductivity type within the substrate and a region of a second conductivity type within the substrate and in contact with the first region forming a junction. At least one semiconductor device is on the substrate. A second region of the first conductivity type is between the plurality of semiconductor devices and the cut edge within the region of the second conductivity type, and extending to the junction. The second region of the first conductivity type can isolate the at least one semiconductor device from leakage pathways created by saw damage at the junction along the cut edge.

Abstract: A method of forming air gaps within a solid structure is provided. In this method, a sacrificial material is covered by an overlayer. The sacrificial material is then removed through the overlayer to leave an air gap. Such air gaps are particularly useful as insulation between metal lines in an electronic device such as an electrical interconnect structure. Structures containing air gaps are also provided.

Abstract: A lens stack having a movable lens attached to a MEMS structure and method of fabricating the same. The method comprises attaching at least one MEMS structure to a transparent substrate. The method further comprises forming a movable lens in contact with the at least one MEMS structure.

Abstract: A photoelectric conversion device comprises a photoelectric conversion unit, a floating diffusion region, a transfer transistor, and an output unit. A control electrode of the transfer transistor includes a first portion which extends along a channel width direction and overlaps a first boundary side when seen through from a direction perpendicular to a light receiving surface of the photoelectric conversion unit, and a second portion which extends along a channel length direction from one end of the first portion and overlaps a second boundary side when seen through from the direction perpendicular to the light receiving surface, and the control electrode of the transfer transistor has an L shape when viewed from the direction perpendicular to the light receiving surface.

Abstract: The invention provides an electronic device configured to prevent or reduce electrostatic discharge from causing a pixel to malfunction. An electronic device manufactured according to the principles of the invention may include multiple conductive layers that cross but do not contact each other, wherein at least one of the conductive layers includes a width change part having a width that changes in a length direction of the at least one of the conductive layers, and a tab connected to at least one of the conductive layers at a region thereof that does not cross a neighboring conductive layer. Alternatively, the width change part may have a width that continuously varies along a length of the at least one conductive layer and may also have obtuse corner edges. The invention also provides a flat organic electroluminescent display (OELD) or LCD display device that includes such an electronic device.

Abstract: Methods of forming metal oxide structure and methods of forming metal oxide patterns on a substrate using a block copolymer system formulated for self-assembly are disclosed. The metal oxide structures and patterns may be used, for example, as a mask for sublithographic patterning during various stages of semiconductor device fabrication. A block copolymer at least within a trench in the substrate and including at least one soluble block and at least one insoluble block may be annealed to form a self-assembled pattern including a plurality of repeating units of the soluble block laterally aligned with the trench and positioned within a matrix of the insoluble block. The self-assembled pattern may be exposed to a metal oxide precursor which impregnates the soluble block. The metal oxide precursor may be oxidized to form a metal oxide. The self-assembled pattern may be removed to form a pattern of metal oxide lines on the substrate surface.

Abstract: A lithographic apparatus includes a support configured to support a patterning device, the patterning device configured to pattern a beam of radiation to form a patterned beam of radiation; a positioning device configured to move the support in a first direction; a measurement device configured to measure a relative position of the patterning device with respect to the support and to generate a measuring signal, the measurement device including a reference unit constructed and arranged to be coupled to the patterning device at a fixed relative position, and a position sensor configured to measure the position of the reference unit with respect to the support, wherein the positioning device is constructed and arranged to correct a position of the support based on the measuring signal.

Abstract: The invention provides an electronic device configured to prevent or reduce electrostatic discharge from causing a pixel to malfunction. An electronic device manufactured according to the principles of the invention may include multiple conductive layers that cross but do not contact each other, wherein at least one of the conductive layers includes a width change part having a width that changes in a length direction of the at least one of the conductive layers, and a tab connected to at least one of the conductive layers at a region thereof that does not cross a neighboring conductive layer. Alternatively, the width change part may have a width that continuously varies along a length of the at least one conductive layer and may also have obtuse corner edges. The invention also provides a flat organic electroluminescent display (OELD) or LCD display device that includes such an electronic device.

Abstract: In a fingerprint apparatus, fingerprint sensing members disposed on a silicon substrate detect skin textures of a finger placed thereon to generate electric signals. A set of integrated circuits formed on the substrate processes the electric signals. First bonding pads are disposed on the substrate and electrically connected to the set of integrated circuits. A first insulating layer is disposed below the first bonding pads. Metal plugs penetrating through the substrate are respectively electrically connected to the first bonding pads. A second insulating layer is formed on the substrate and between the metal plugs and the substrate. Second bonding pads are formed on a rear side of the second insulating layer, and are respectively electrically connected to the first bonding pads through the metal plugs. The protection layer is disposed on the substrate and covers the sensing members to form a flat touch surface to be touched by the finger.

Abstract: The present invention relates to a fuse in a semiconductor device and method for fabricating the same. An oxide film is formed on sidewalls of a barrier metal layer in a bottom portion of a fuse pattern, thereby preventing the barrier metal layer from being exposed. As a result, the oxidation of the barrier metal layer is inhibited to improve characteristics of the device.

Abstract: There is disclosed a semiconductor device and a method of fabricating the semiconductor device in which a heat treatment time required for crystal growth is shortened and a process is simplified. Two catalytic element introduction regions are arranged at both sides of one active layer and crystallization is made. A boundary portion where crystal growth from one catalytic element introduction region meets crystal growth from the other catalytic element introduction region is formed in a region which becomes a source region or drain region.

Abstract: A planar transformer structure, which can be constructed in an integrated semiconductor circuit without using traditional metallic windings. To avoid large thermal expansion of metallic spiral windings and associated mechanical stress on a metal-semiconductor interface, it is suggested that highly doped semiconductor materials with or without silicides and salicides can be used to form windings or conducting paths because their thermal expansion coefficients are similar to that of semiconductor material. The planar semiconductor transformer may find application for low-power and signal transfer that needs electrical isolation.

Abstract: An image sensing device and a packaging method thereof is disclosed. The packaging method includes the steps of providing an adhesive layer; placing a substrate, having an opening, on the adhesive layer; disposing an image sensor within the opening on the adhesive layer; adding a filler between the image sensor and the substrate; connecting the image sensor and the substrate via a plurality of bonding wires; and removing the adhesive layer.

Abstract: A semiconductor device includes a semiconductor body with a front-sided surface. An active cell region with a semiconductor device structure and an edge region surrounding the active cell region are arranged in the semiconductor body. The front-sided surface of the semiconductor body includes a passivation layer over the edge region and over the active cell region. The passivation layer includes a semiconducting insulation layer of a semiconducting material, the bandgap of which is greater than the bandgap of the material of the semiconductor body.

Abstract: The present invention provides methods for forming at least partially relaxed strained material layers on a target substrate. The methods include forming islands of the strained material layer on an intermediate substrate, at least partially relaxing the strained material islands by a first heat treatment, and transferring the at least partially relaxed strained material islands to the target substrate. The at least partial relaxation is facilitated by the presence of low-viscosity or compliant layers adjacent to the strained material layer. The invention also provides semiconductor structures having an at least partially relaxed strained material layer, and semiconductor devices fabricated using an at least partially relaxed strained material layer.

Abstract: A method for growth of an alloy for use in a nanostructure, to provide a resulting nanostructure compound including at least one of GexTey, InxSby, InxSey, SbxTey, GaxSby, GexSby,Tez, InxSbyTez, GaxSeyTez, SnxSbyTez, InxSbyGez, GewSnxSbyTez, GewSbxSeyTez, and TewGexSbySz, where w, x, y and z are numbers consistent with oxidization states (2, 3, 4, 5, 6) of the corresponding elements. The melt temperatures for some of the resulting compounds are in a range 330-420° C., or even lower with some compounds.

Abstract: Systems, methods and apparatus are provided through which in some implementations a portable wireless digital X-ray detector includes a battery electrically coupled to at least one external electrical conductor. In some implementations, the external electrical conductor is mounted flush to an outside of a housing of the portable wireless digital X-ray detector. In some implementations, the external electrical conductor plate includes only hypoallergenic materials. In some implementations, the battery is fixed mounted in the portable wireless digital X-ray detector. In some implementations docking detector receptacle at least one external electrical conductor in a pocket of the docking detector receptacle.

Abstract: The semiconductor integrated circuit has so-called SOI type first MOS transistors (MNtk, MPtk) and second MOS transistors (MNtn, MPtn). The first MOS transistors have a gate isolation film thicker than that the second MOS transistors have. The first and second MOS transistors constitute a power-supply-interruptible circuit (6) and a power-supply-uninterrupted circuit (7). The power-supply-interruptible circuit has the first MOS transistors each constituting a power switch (10) between a source line (VDD) and a ground line (VSS), and the second MOS transistors connected in series with the power switch. A gate control signal for the first MOS transistors each constituting a power switch is made larger in amplitude than that for the second MOS transistors. This enables power-source cutoff control with a high degree of flexibility commensurate with the device isolation structure, which an SOI type semiconductor integrated circuit has originally.

Abstract: A thin film transistor is disclosed, comprising a substrate, a polysilicon layer overlying the substrate, a gate insulating layer overlying the polysilicon layer, a gate electrode, a dielectric interlayer overlying the gate electrode and gate insulating layer, and a source/drain electrode overlying the dielectric interlayer. Specifically, the gate electrode comprises a first electrode layer overlying the gate insulating layer and a second electrode layer essentially overlying an upper surface of the first electrode layer. The first and second electrode layers each has substantially the same profile with a taper angle of less than about 90 degrees.

Abstract: The present invention discloses an aspherical LED angular optical lens for wide distribution patterns and an LED assembly using the same. The optical lens comprises a concave surface on a source side and a convex surface on a project side. The LED assembly comprising the optical lens can accumulate light emitted from the LED die and generate a peak intensity of the wide angular circle distribution pattern which is greater than 120° and smaller than 180°. The present invention only uses a single optical lens capable of accumulating light and forming a required distribution pattern to satisfy the requirement of a luminous flux ratio greater than 85% and the requirement of an illumination, a flash light of a cell phone or a flash light of a camera.

Abstract: A method of fabricating a shuttle wafer is provided. First, a wafer including a number of shots is provided. Each of the shots includes a number of dies. A material layer is then formed on the wafer. After that, a shuttle mask having a number of IC designs is provided. A first IC design corresponds to a first die of each of the shots. A portion of the IC designs on the shuttle mask is covered for exposing the first IC design. Thereafter, the first IC designs of the shuttle mask are transferred onto the material layer, so as to form at least an effective IC pattern on the first die of each of the shots and to form an ineffective IC pattern on each of the other dies of each of the shots.

Abstract: An ESD protection structure includes, in part, a NMOS transistor having a source and drain in a well in a substrate and a gate on the substrate with the source and drain being connected between ground and a series diode, and the gate being connected to ground. The structure further includes a diode having a cathode connected to the input pad and an anode connected to the well so that the diode is reverse-biased in the event of a positive voltage ESD event on the input pad. As a result, in a positive voltage ESD event, the avalanche effect rapidly injects current into the substrate and therefore into the base of the parasitic bipolar transistor so as to trigger the transistor into conduction and discharge the ESD pulse. Alternatively, the diode is a Zener diode and the current is generated by the Zener effect. A complementary structure provides protection against a negative ESD pulse.

Abstract: An exemplary image sensor module includes a heat pipe and an image sensor. The heat pipe includes a main body and a working fluid. The main body includes a top flat cover, an opposite bottom flat cover and a chamber cooperatively defined between the top cover and the bottom cover. The working fluid is filled in the chamber. The image sensor is in thermal contact with an evaporation end of the heat pipe.

Abstract: A light emitting device includes: a light emitting element; a first lead including a die pad portion at its one end portion, the light emitting element being bonded to the die pad portion; a second lead with its one end portion being opposed to the one end portion of the first lead; and a resin molded body including a recess with at least part of the die pad portion being exposed to the bottom thereof so that emission light from the light emitting element can be emitted upward, a lower surface with at least part of the lower surface of the first lead and at least part of the lower surface of the second lead being exposed thereto, and a lateral surface with at least part of the lateral surface of the die pad portion being exposed thereto, the resin molded body embedding the first lead and the second lead so that the other end portion of the first lead and the other end portion of the second lead are projected in directions opposite to each other.

Abstract: Application form of and demand for an IC chip formed with a silicon wafer are expected to increase, and further reduction in cost is required. An object of the invention is to provide a structure of an IC chip and a process capable of producing at a lower cost. In view of the above described object, one feature of the invention is to provide the steps of forming a separation layer over an insulating substrate and forming a thin film integrated circuit having a semiconductor film as an active region over the separation layer, wherein the thin film integrated circuit is not separated. There is less limitation on the shape of a mother substrate in the case of using the insulating substrate, when compared with the case of taking a chip out of a circular silicon wafer. Accordingly, reduction in cost of an IC chip can be achieved.

Abstract: An apparatus comprising plurality of functional integrated circuit blocks, each manufactured with different oxide thicknesses on a monolithic integrated circuit die, is described. Using different gate oxide thicknesses for different functional integrated circuit blocks provides reduced power consumption and increases performance in processing systems. Several embodiments comprising different combinations of functional integrated circuit blocks, including processor cores and memory elements, are presented.

Abstract: Disclosed are embodiments of forming an integrated circuit with a desired decoupling capacitance and with the uniform and targeted across-chip polysilicon perimeter density. The method includes laying out functional blocks to form the circuit according to the design and also laying out one or more decoupling capacitor blocks to achieve the desired decoupling capacitance. Then, local polysilicon perimeter densities of the blocks are determined and, as necessary, the decoupling capacitor blocks are reconfigured in order to adjust for differences in the local polysilicon perimeter densities. This reconfiguring is performed in a manner that essentially maintains the desired decoupling capacitance. Due to the across-chip polysilicon perimeter density uniformity, functional devices in different regions of the chip will exhibit limited performance parameter variations (e.g., limited threshold voltage variations).

Abstract: A light emitting semiconductor device comprising an LED having an emission aperture located on a surface of the LED and the emission aperture has a size that is smaller than a surface area of the LED where the emission aperture is formed. The device further includes a reflector surrounding both side walls, a bottom surface, and portions of a surface of the LED where the emission aperture is formed or surrounding the bottom surface and portions of the surface of the LED where the emission aperture is formed so that an area on the surface uncovered by the reflector is the emission aperture and is smaller than the area of the LED. Alternatively, in the light emitting semiconductor, the surface of the LED substantially aligned with the emission aperture may be roughened and the surface of the LED beyond the emission aperture may be smooth. The surface of the LED beyond the emission aperture may also be covered by a low loss reflector.

Abstract: Double patterning techniques and structures are generally described. In one example, a method includes depositing a first photoresist to a semiconductor substrate, forming a first integrated circuit (IC) pattern in the first photoresist, the first IC pattern comprising one or more trench structures, protecting the first IC pattern in the first photoresist from actions that form a second IC pattern in a second photoresist, depositing the second photoresist to the first IC pattern, and forming the second IC pattern in the second photoresist, the second IC pattern comprising one or more structures that are sufficiently close to the one or more trench structures of the first IC pattern to cause scumming of the second photoresist in the one or more trench structures of the first IC pattern.

Abstract: One embodiment of the present invention relates to method for the concurrent deposition of multiple different crystalline structures on a semiconductor body utilizing in-situ differential epitaxy. In one embodiment of the present invention a preparation surface is formed, resulting in two distinct crystalline regions, a monocrystalline silicon substrate region and an isolating layer region. A monocrystalline silicon layer and an amorphous silicon layer are concurrently formed directly onto the preparation surface in the monocrystalline silicon substrate region and the isolating layer region, respectively. Deposition comprises the formation of two or more sub-layers. The process parameters can be varied for each individual sub-layer to optimize deposition characteristics.

Abstract: A capacitor includes a bottom electrode, a dielectric layer and a top electrode over a substrate. A RuXTiYOZ film is included in at least one of the bottom and top electrodes, where x, y and z are positive real numbers. A method of fabricating the capacitor through a sequential formation of a bottom electrode, a dielectric layer and a top electrode over a substrate includes forming a RuXTiYOZ film during a formation of at least one of the bottom electrode and top electrode, where x, y and z are positive real numbers.

Abstract: A bi-directional power switch is formed as a monolithic semiconductor device. The power switch has two MOSFETs formed with separate source contacts to the external package and a common drain. The MOSFETs have first and second channel regions formed over a well region above a substrate. A first source is formed in the first channel. A first metal makes electrical contact to the first source. A first gate region is formed over the first channel. A second source region is formed in the second channel. A second metal makes electrical contact to the second source. A second gate region is formed over the second channel. A common drain region is disposed between the first and second gate regions. A local oxidation on silicon region and field implant are formed over the common drain region. The metal contacts are formed in the same plane as a single metal layer.

Abstract: The bow in a wafer that results from fabricating a large number of MEMS devices on the top surface of the passivation layer of the wafer so that a MEMS device is formed over each die region is reduced by forming a stress relief layer between the passivation layer and the MEMS devices.

Abstract: Objects are to suppress reduction in current output from a photoelectric conversion device and to prevent ESD from occurring in the photoelectric conversion device without greatly increasing the number of steps for manufacturing the photoelectric conversion device. The photoelectric conversion device includes a photodiode generating current by light irradiation; an amplifier circuit including at least one MOS transistor for amplifying the current; and at least one diode which is connected in series with the photodiode in a path of the current generated in the photodiode or a path of the current amplified by at least one MOS transistor so that a bias direction of the diode is opposite to that of the photodiode. Each of the photodiode and the diode includes a stack of a plurality of semiconductor films.

Abstract: To improve a sensor resetting method and thereby implement a high rate at which a moving image is read, the invention provides an image pickup apparatus and a radiation image pickup apparatus including: a plurality of pixels arranged on a substrate in row and column directions, each pixel having a conversion element and a transfer switching element; a drive wiring connected to a plurality of the transfer switching elements in the row direction; and a conversion element wiring connected to a plurality of the conversion elements in the row direction, wherein a reset switching element is disposed between the conversion element wiring and a reset wiring for supplying a reset voltage for resetting the conversion element, and a bias switching element is disposed between the conversion element wiring and a bias wiring for supplying a bias voltage for operating the conversion element.

Abstract: Warpage and twist of a solid-state image sensing apparatus is controlled, thereby preventing displacement occurring to the solid-state image sensing apparatus when it is mounted on a printed circuit board. The solid-state image sensing apparatus comprises a plurality of outer leads, and the outer leads each comprises a horizontal portion protruding in the horizontal direction from a side face of a package body for encasing a solid-state image sensing chip therein, an end portion extending in a direction orthogonal to the horizontal portion, and disposed directly below the horizontal portion, a mid portion positioned between the horizontal portion, and the end portion, a first bend formed between the horizontal portion, and the mid portion, and a second bend formed between the mid portion, and the end portion.

Abstract: In one embodiment, relatively thin but wide metal bus strips overlying a high power FET are formed to conduct current to the source and drain narrow metal strips. A passivation layer is formed over the surface of the FET, and the passivation layer is etched to expose almost the entire top surface of the bus strips. A copper seed layer is then formed over the surface of the wafer, and a mask is formed to expose only the seed layer over the bus strips. The seed layer over the bus strips is then copper or gold electroplated to deposit a very thick metal layer, which effectively merges with the underlaying metal layer, to reduce on-resistance. The plating metal does not need to be passivated due to its thickness and wide line/space. Other techniques may also be used for depositing a thick metal over the exposed bus strips.

Abstract: An apparatus for supplying power in a semiconductor integrated circuit includes a plurality of power lines, each supplying external power to an interior of the semiconductor integrated circuit, and at least one decoupling capacitor set connected to the plurality of power lines and having a resistance value configured to be variable according to a bias voltage.

Abstract: A method for measuring the thickness of a layer is provided, comprising (a) providing a structure (101) comprising a first layer disposed on a second layer; (b) impinging (103) the structure with a first ion beam comprising a first isotope, thereby sputtering off a portion of the first layer which contains a second isotope and exposing a portion of the second layer; and (c) determining (105) the thickness of the first layer by measuring the amount of the second isotope which is sputtered off.

Abstract: Imager wafer level modules, methods of assembly for imager wafer level modules, and systems containing imager wafer level modules. An imager die and an optic lens stack are combined to form a module assembly. The module assembly is combined with a molded plastic, laminated plastic, or metallic interposer to form an imager wafer level module capable of assembly using industry standard equipment sets for all processing, and capable of being used with various imaging systems.

Abstract: An integrated semiconductor device includes a plurality of semiconductor elements having different integrated element circuits or different sizes; an insulating material arranged between the semiconductor elements; an organic insulating film arranged entirely on the semiconductor elements and the insulating material; a fine thin-layer wiring that arranged on the organic insulating film and connects the semiconductor elements; a first input/output electrode arranged on an area of the insulating material; and a first bump electrode formed on the first input/output electrode.

Abstract: Logic LSI includes first power domains PD1 to PD4, thick-film power switches SW1 to SW4, and power switch controllers PSWC1 to PSWC4. The thick-film power switches are formed by thick-film power transistors manufactured in a process common to external input/output circuits I/O. The first power domains include second power domains SPD11 to SPD42 including logic blocks, control circuit blocks SCB1 to SCB4, and thin-film power switches SWN11 to SWN42 that are connected to the thick-film power switches via virtual ground lines VSSM1 to VSSM4, and formed by thin-film power transistors manufactured in a process common to the logic blocks. In this way, power switches having different thickness of gate insulating films from one another are vertically stacked so as to be in a hierarchical structure, and each power switch is individually controlled by a power switch controller and a control circuit block correspondingly to each mode.