Abstract: A phase change memory device with a reduced phase change volume and lower drive current and a method for forming the same are provided. The method includes forming a bottom insulating layer comprising a bottom electrode contact, forming a bottom electrode film on the bottom electrode contact, forming an anti-reflective coating (ARC) film on the bottom electrode film, patterning and etching the ARC film and the bottom electrode film to form a bottom electrode comprising a side edge, and forming a phase change material portion on the ARC film and the bottom insulating layer, wherein the phase change material portion physically contacts the side edge of the bottom electrode. The method further includes forming a top electrode on the phase change material portion, and forming a top electrode contact on the top electrode.

Abstract: Bidirectional switches are described. The bidirectional switches include first and a second III-N based high electron mobility transistor. In some embodiments, the source of the first transistor is in electrical contact with a source of the second transistor. In some embodiments, the drain of the first transistor is in electrical contact with a drain of the second transistor. In some embodiments, the two transistors share a drift region and the switch is free of a drain contact between the two transistors. Matrix converters can be formed from the bidirectional switches.

Abstract: A semiconductor device and fabrication method thereof is disclosed. The method includes the steps of providing a substrate with a trench and a stacked layer thereon, performing an epitaxy process to form an epitaxial layer in the trench, conformably depositing an oxide layer on the epitaxial layer, and removing a portion of the oxide layer and the epitaxial layer on the bottom of the trench.

Abstract: An embedded flash memory device and a method for fabricating the same which reduces the size of a memory device using logic CMOS fabricating processes and enhancing a coupling ratio of the memory device. The flash memory device includes a coupling oxide layer on an active area of a semiconductor substrate, a first control gate formed on and/or over the coupling oxide layer and a second control gate formed on and/or over and enclosing lateral sidewalls of the coupling oxide layer and the first control gate.

Abstract: A semiconductor device includes: a first MOSFET including: first source and drain regions formed at a distance from each other in a first semiconductor region; a first insulating film formed on the first semiconductor region between the first source region and the first drain region; a first gate electrode formed on the first insulating film; a first sidewall insulating film formed at side portions of the first gate electrode; a first single-crystal silicon layer formed on each of the first source and drain regions, and having at least an upper-face made of a {111} plane; a first NiSi layer formed at least on the first single-crystal silicon layer, and having a portion whose interface with the first single-crystal silicon is on the {111} plane of the first single-crystal silicon layer and a part of the portion of the first NiSi layer being in contact with the first sidewall insulating film; and a first TiN film being in contact with the portion of the first NiSi layer on the {111} plane of the first single-cr

Abstract: A transistor (1) has a FET (2) and a temperature sensing diode (4) integrated within it. Gate drive circuit (12) is arranged to switch off FET (2) and in this case biasing circuit (14) drives a constant current through the diode (4). The voltage across the diode (4) is measured by voltage sensor (15) which provides a measure of the temperature of the FET.

Abstract: A method for measuring samples includes fitting and mounting, onto a transfer stage, a chip pallet for transporting sensor chips; fitting a positioning hole of a chip package onto a positioning pin; pulling a bottom plate of the chip package off the chip package, so as to simultaneously transfer the housed sensor chips onto the transfer stage; pulling upward the chip pallet so as to simultaneously transfer, onto the chip pallet, the sensor chips on the transfer stage; and mounting the chip pallet having the sensor chips mounted thereon onto a measuring device, and measuring samples.

Abstract: An electronic circuit device comprises a silicon substrate having front and rear surfaces, a semiconductor element formed on the front surface, and at least one through-hole penetrating through the front surface and the rear surface. At least one passive element is supported by the silicon substrate. At least one connecting element is disposed in the through-hole of the silicon substrate for electrically connecting the semiconductor element to the passive element.

Abstract: An imager apparatus and associated starting material are provided. Such starting material includes a first silicon layer and an oxide layer disposed adjacent to the first silicon layer. Further included is a first doped layer disposed adjacent to the oxide layer with a first doping, and a second doped layer disposed adjacent to the first doped layer with, a second doping that is less than the first doping layer.

Abstract: Example embodiments provide a capacitorless dynamic random access memory (DRAM), and methods of manufacturing and operating the same. The capacitorless DRAM according to example embodiments may include a semiconductor layer separated from a top surface of a substrate and that contains a source region, a drain region, and a channel region, a charge reserving layer formed on the channel region, and a gate formed on the substrate to contact the channel region and the charge reserving layer.

Abstract: In the course of forming a resistor in the back end of an integrated circuit, an intermediate dielectric layer is deposited and a trench etched through it and into a lower dielectric layer by a controllable amount, so that the top of a resistor layer deposited in the trench is close in height to the top of the lower dielectric layer; the trench is filled and the resistor layer outside the trench is removed, after which a second dielectric layer is deposited. Vias passing through the second dielectric layer to contact the resistor then have the same depth as vias contacting metal interconnects in the lower dielectric layer. A tri-layer resistor structure is employed in which the resistive film is sandwiched between two protective layers that block diffusion between the resistor and BEOL ILD layers.

Abstract: A device and method of reducing residual STI corner defects in a hybrid orientation transistor comprising, forming a direct silicon bonded substrate wherein a second silicon layer with a second crystal orientation is bonded to a handle substrate with a first crystal orientation, forming a pad oxide layer on the second silicon layer, forming a nitride layer on the pad oxide layer, forming an isolation trench within the direct silicon bonded substrate through the second silicon layer and into the handle substrate, patterning a PMOS region of the direct silicon bonded substrate utilizing photoresist including a portion of the isolation trench, implanting and amorphizing an NMOS region of the direct silicon bonded substrate, removing the photoresist, performing solid phase epitaxy, performing a recrystallization anneal, forming an STI liner, completing front end processing, and performing back end processing.

Abstract: A nonvolatile semiconductor memory element includes a semiconductor substrate, a source region and a drain region which are provided separately in the semiconductor substrate, a tunnel insulating layer which is provided between the source region and the drain region on the semiconductor substrate, a charge storage layer which is provided on the tunnel insulating layer, a block insulating layer which is provided on the charge storage layer and includes a crystallized lanthanum aluminate layer, and a control gate electrode which is provided on the block insulating layer.

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a capacitor plate includes a first propeller-shaped portion and a second propeller-shaped portion. A via portion is disposed between the first propeller-shaped portion and the second propeller-shaped portion.

Abstract: A method of forming a device associated with a via includes forming an opening or via, and forming at least a pair of conducting paths within the via. Also disclosed is a via having at pair of conducting paths therein.

Abstract: An electrically programmable fuse comprising a cathode member, an anode member, and a link member, wherein the cathode member, the anode member, and the link member each comprise one of a plurality of materials operative to localize induced electromigration in the programmable fuse.

Abstract: A semiconductor component that includes a leadframe, a discrete passive circuit element, and an active circuit element. The discrete passive circuit element such as, for example, a discrete ferrite core inductor, is mounted either laterally or vertically adjacent to the leadframe. A semiconductor chip is attached to the discrete ferrite core inductor. Bond pads on the semiconductor chip may be electrically coupled to leads from the leadframe or to the discrete ferrite core inductor by wire bonds. The leadframe, discrete ferrite core inductor, semiconductor chip, and wire bonds are protected by an encapsulant such as a mold compound. Other passive circuit elements may be mounted to the discrete ferrite core inductor before encapsulation in the mold compound.

Abstract: The invention discloses a package structure for a micro-sensor including a micro-cantilever for capturing a chemical substance. The package structure, according to the invention, includes a first substrate, a second substrate, and a casing. The first substrate thereon forms a processing circuit. The micro-sensor is bonded to a first upper surface of the first substrate and is electrically connected to the processing circuit capable of outputting a signal relative to the chemical substance sensed by the micro-sensor. The second substrate has a formed-through aperture. The second substrate is bonded to the first substrate such that the micro-sensor is disposed in the formed-through aperture. The casing is bonded to the second substrate and includes a reaction chamber in which the micro-cantilever is installed and a fluid containing the chemical substance flows into.

Abstract: A method of fabricating an integrated circuit includes providing a semiconductor substrate having a doped area; generating a conductive structure towards the doped area, wherein the conductive structure includes an extending section that protrudes from the doped area; generating an electrically isolating layer at a sidewall of the extending section after generating the conductive structure.

Abstract: A micro electromechanical system and a fabrication method thereof, which has trenches formed on a substrate to prevent circuits from interfering each other, and to prevent over-etching of the substrate when releasing a microstructure.

Abstract: A memory cell includes a floating gate electrode, a first inter-electrode insulating film and a control gate electrode. A peripheral transistor includes a lower electrode, a second inter-electrode insulating film and an upper electrode. The lower electrode and the upper electrode are electrically connected via an opening provided on the second inter-electrode insulating film. The first and second inter-electrode insulating films include a high-permittivity material, the first inter-electrode insulating film has a first structure, and the second inter-electrode insulating film has a second structure different from the first structure.

Abstract: A semiconductor device including an inductor and a fabricating method thereof are provided. The semiconductor device can include a connection wiring provided on a semiconductor substrate; a metal wiring provided on an insulating layer in a spiral shape and electrically connected to the connection wiring; and holes provided in the insulating layer and between the metal wiring and the silicon substrate.

Abstract: A SIMOX wafer manufacturing method which is capable of providing etching conditions to prevent surface defects (divots) from being spread. The method includes an oxygen implantation process and a high temperature annealing step for forming a BOX layer, a front surface oxide film etching process to treat a front surface of the wafer at an area in which oxygen is implanted, and a rear surface oxide film etching process to treat a rear surface of the wafer, and oxide film etching conditions in the front and rear oxide film etching processes are controlled differently.

Abstract: The spin transistor in accordance with the present invention comprises a magnetoresistive element having a fixed layer, a free layer, and a semiconductor layer provided between the fixed layer and free layer; a source electrode layer electrically connected to one end face in a laminating direction of the magnetoresistive element; a drain electrode layer electrically connected to the other end face in the laminating direction of the magnetoresistive element; and a gate electrode layer laterally adjacent to the semiconductor layer through a gate insulating layer provided on a side face of the semiconductor layer.

Abstract: Provided are a FinFET and a method of manufacturing the same. A FinFET may include at least one active fin, at least one gate insulating layer pattern, a first electrode pattern, a second electrode pattern and at least one pair of source/drain expansion regions. The at least one active fin may be formed on a substrate. The at least one gate insulating layer pattern may be formed on the at least one active fin. The first electrode pattern may be formed on the at least one gate insulating layer pattern. Further, the first electrode pattern may be intersected with the at least one active fin. The second electrode pattern may be formed on the first electrode pattern. Further, the second electrode pattern may have a width greater than that of the first electrode pattern. The at least one pair of source/drain expansion regions may be formed on a surface of the at least one active fin on both sides of the first electrode pattern. Thus, the FinFET may have improved capacity and reduced GIDL current.

Abstract: On a surface of a semiconductor substrate, an epitaxial layer of a conductivity type opposite to a conductivity type of the semiconductor substrate is formed, trenches are formed in portions other than a portion serving as a resistor, and the trenches are filled with an insulating film to three-dimensionally form U-shaped resistors which are separated from each other.

Abstract: In some embodiments of the invention, encapsulated semiconducting nanomaterials are described. In certain embodiments the nanostructures described are semiconducting nanomaterials encapsulated with ordered carbon shells. In some aspects a method for producing encapsulated semiconducting nanomaterials is disclosed. In some embodiments applications of encapsulated semiconducting nanomaterials are described.

Abstract: A method of fabricating an inductor in a semiconductor device is disclosed. Embodiments include forming a first metal wire in a trench formed by etching a layer of a semiconductor substrate, forming an insulating layer over the substrate including the first metal wire, forming a via hole by etching the insulating layer to expose a portion of the first metal wire, forming a plated layer by electroplating to partially fill the via hole with the plated layer, and forming a second metal wire over the insulating layer including the plated layer.

Abstract: An integrated circuit is disclosed. One embodiment includes a first diode, a second diode, and a semiconductor line coupled to the first diode and the second diode. The line includes a first silicide region between the first diode and the second diode.

Abstract: A thin semiconductor layer is formed and patterned on a semiconductor substrate to form a thin semiconductor fuselink on shallow trench isolation and between an anode semiconductor region and a cathode semiconductor region. During metallization, the semiconductor fuselink is converted to a thin metal semiconductor alloy fuselink as all of the semiconductor material in the semiconductor fuselink reacts with a metal to form a metal semiconductor alloy. The inventive electrical fuse comprises the thin metal semiconductor alloy fuselink, a metal semiconductor alloy anode, and a metal semiconductor alloy cathode. The thin metal semiconductor alloy fuselink has a smaller cross-sectional area compared with prior art electrical fuses. Current density within the fuselink and the divergence of current at the interface between the fuselink and the cathode or anode comparable to prior art electrical fuses are obtained with less programming current than prior art electrical fuses.

Abstract: A method for fabricating a sensor chip having a substrate, a cover layer, a spacer layer interposed between the substrate and the cover layer, and a hollow reaction section provided in the spacer layer, the method comprising the steps of: affixing two or more adhesive or bonding tapes onto a sheet where a plurality of substrates are to be formed or onto a plurality of substrates, to thus form a spacer layer; and forming a hollow reaction section from one or a plurality of gaps between the tapes, whereby volumetric variations or positional displacements of the hollow reaction section can be reduced. A sensor chip which can be fabricated by this method.

Abstract: A method for fabricating an eFuse, the method comprising disposing a crystalline silicon eFuse on a substrate having a fuse link portion, a first contact portion, and a second contact portion, wherein the fuse link is oriented parallel to the silicon crystal {110} plane direction, etching the eFuse using crystallographic orientation dependent wet etching in the {110} plane direction such that a corner at a junction of the fuse link an a contact portion is substantially square, operative to increase current density when an electric current flows through the fuse link, and forming a silicide layer atop the eFuse.

Abstract: A switching assembly is disclosed for a high voltage aircraft ignition system. The switching assembly includes a ceramic substrate and switch die that includes an anode bonded to an electrical pad on the ceramic substrate. The switch die includes a semiconductor device having a plurality of interleaved gates and cathodes, and includes a ceramic cap having at least one gate pad connected to the gates and at least one cathode pad connected to the cathodes. The switching assembly includes leads connected to the gate pad, the cathode pad, and the electrical pad on the substrate. The switch die and a portion of the leads are potted to form the completed assembly.

Abstract: A microelectronic package and a method of forming the package. The package includes a first level package mounted to a carrier. The first level package includes a package substrate having a die side and a carrier side; and a microelectronic die mounted on the package substrate at the die side thereof. The carrier has a substrate side, and the first level package is mounted on the carrier at the substrate side thereof. A rigid body is attached to the carrier side of the substrate at an attachment location of the substrate and to the substrate side of the carrier at an attachment location of the carrier, the attachment location of the carrier being electrically unconnected, the rigid body being configured and disposed to provide structural support between the substrate and the carrier.

Abstract: A shallow trench isolation (STI) structure has a top portion tapering in width from wide to narrow in a direction from a substrate surface, from a first width at a top of the first portion to a second width at a bottom of the first portion. The STI structure also includes a bottom portion below the top portion, which expands from the bottom of the top portion to a substantially widened lateral distance having a third width. The third width is, in general, substantially larger than the second width. The inventive STI structure can provide desired isolation characteristics with a significantly reduced aspect ratio, thus suitable for device isolations in advanced processing technology.

Abstract: Provided are a diode structure and a memory device including the same. The diode structure includes: a first electrode; a p-type Cu oxide layer formed on the first electrode; an n-type InZn oxide layer formed on the p-type Cu oxide layer; and a second electrode formed on the n-type InZn oxide.

Abstract: A method of forming an isolation trench structure is disclosed, the method includes forming an isolation trench in a semiconductor body associated with an isolation region, and implanting a non-dopant atom into the isolation trench, thereby forming a region to modify the halo profile in the semiconductor body. Subsequently, the isolation trench is filled with a dielectric material.

Abstract: A fabricating method for silicon on insulator is disclosed, and the fabricating method includes stripping the oxide and the nitride on the bottom surface of each of the trenches, forming a porous silicon on portions of the substrate by an anodizing process, spin coating a dielectric material to fill up the trenches and performing a thermal process to convert the porous silicon to an insulating layer.

Abstract: The semiconductor device, which provides reduced electric current leakage and parasitic resistance to achieve stable current gain, is provided. A first polycrystalline semiconductor layer is grown on a p-type polycrystalline silicon film exposed in a lower surface of a visor section composed of a multiple-layered film containing a p-type polycrystalline silicon film and a silicon nitride film, while growing the first semiconductor layer on a n-type collector layer, and then the first polycrystalline semiconductor layer is selectively removed.

Abstract: A method of forming a semiconductor structure includes forming an opening in a dielectric layer, forming a recess in an exposed part of a substrate, and forming a lattice-mismatched crystalline semiconductor material in the recess and opening.

Abstract: A integrated semiconductor device has a first semiconductor layer of a first conductivity type, a second semiconductor layer of the first conductivity type over the first layer, a third semiconductor layer of a second conductivity type over the second layer, an isolation trench extending through the entire depth of the second and third layers into the first layer, and a first region of the second conductivity type located next to the isolation trench and extending from an interface between the second and third layers, along an interface between the second layer and the isolation trench. This first region can help reduce a concentration of field lines where the isolation trench meets the interface of the second and third layers, and hence provide a better reverse breakdown characteristic.

Abstract: The present invention relates to an isolation film in a semiconductor device and method of forming the same. An isolation film is formed in a doped region of a peripheral region, in which the doped region is isolated from a deep well region of a cell region and the isolation film is thicker than an isolation film of the cell region so that a parasitic transistor is not generated and a leakage current can be prevented.

Abstract: A method of fabricating an integrated device on a substrate with an exposed surface region is disclosed. One embodiment provides introducing a first component into the exposed surface region of the substrate. A material is provided on the exposed surface region. The material on the exposed surface region is cured and the first component release from the exposed surface region of the substrate.

Abstract: According to an aspect of an embodiment, a semiconductor device has a substrate a first insulator formed in a first area of the substrate, and a second insulator formed in the second area of the substrate, a first transistor formed over a first device region surrounded by the first area, the first transistor having a first gate insulating film having a first thickness, the first gate insulating film being formed over the first device region, a first gate electrode formed over the first gate insulating film and the second transistor having a second gate insulating film formed over the second device region, a second gate insulating film having a second thickness less than the first thickness of the first gate insulating film, a second gate electrode formed over the second gate insulating film.

Abstract: The present invention relates to a semiconductor-on-insulator (SOI) substrate having one or more device regions. Each device region comprises at least a base semiconductor substrate layer and a semiconductor device layer with a buried insulator layer located therebetween, while the semiconductor device layer is supported by one or more vertical insulating pillars. The vertical insulating pillars each preferably has a ledge extending between the base semiconductor substrate layer and the semiconductor device layer. The SOI substrates of the present invention can be readily formed from a precursor substrate structure with a “floating” semiconductor device layer that is spaced apart from the base semiconductor substrate layer by an air gap and is supported by one or more vertical insulating pillars. The air gap is preferably formed by selective removal of a sacrificial layer located between the base semiconductor substrate layer and the semiconductor device layer.

Abstract: A method of making a nanostructure array including disposing a masking material on a nanoporous template such that a first number of the plurality of nanopores are fully coated while a second number of the plurality of nanopores are not-fully coated by the masking material is provided. The method includes forming the nanostructures within the plurality of nanopores that are not-fully coated by the masking material. A nanostructure array fabricated in accordance to above said method and devices based on the nanostructure array is also provided.

Abstract: There is provided a semiconductor device comprising: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type provided on the first semiconductor layer of the first conductivity type; a semiconductor region of the first conductivity type selectively provided on a front surface portion of the second semiconductor layer of the second conductivity type; a first main electrode provided in contact with a surface of the semiconductor region; a second main electrode provided on a side of the first semiconductor layer of the first conductivity type, the side being opposite to the surface on which the second semiconductor layer of the second conductivity type is provided; a gate wiring provided on the second semiconductor layer of the second conductivity type around an element region in which the semiconductor region is provided; a trench penetrating the second semiconductor layer of the second conductivity type to reach the first semiconductor layer of the f

Abstract: An integrated circuit (IC) design, method and program product for reducing IC design power consumption. The IC is organized in circuit rows. Circuit rows may include a low voltage island powered by a low voltage (Vddl) supply and a high voltage island powered by a high voltage (Vddh) supply. Circuit elements including cells, latches and macros are placed with high or low voltage islands to minimize IC power while maintaining overall performance. Level converters may be placed with high voltage circuit elements.

Abstract: A semiconductor device having a thyristor SCR with reduced turn-off time. A third semiconductor region of the second conductivity type (anode AN) and a fourth semiconductor region of the first conductivity type (anode gate AG) are formed in the top layer of a first semiconductor region; fifth semiconductor region of the first conductivity type (cathode CA) and sixth semiconductor region of the second conductivity type (cathode gate CG) are formed in the top layer of a second semiconductor region; a gate insulating film and gate electrode MG are formed on the second semiconductor region. When the thyristor is turned off from the on state, a higher potential than that on the anode is applied to the anode gate, and a diode made up of the anode and the anode gate inside the thyristor is made to conduct so as to control the potential of the anode during driving.

Abstract: The present disclosed integrated circuit includes a substrate having a top surface, a buried N type layer in the substrate, N type contact region extending from the surface to the buried N type region, a buried P type region abutting and above the buried N type region in the substrate, a P type contact region extending from the surface to the buried P type region, and an N type device region in the surface and above the buried P type region. The P type impurity of the buried P type region including an impurity of a lower coefficient of diffusion than the coefficient of diffusion of the impurities of the P type contact region.