Abstract: An electrical circuit is disclosed that is capable of adjusting the peak-to-peak voltage of a binary signal symmetrically around a reference voltage, without human intervention and without introducing a transient response into the signal. One embodiment of the circuit comprises a current source, five resistors and two diodes, create an intelligent "voltage divider" that adjusts the peak-to-peak voltage of a binary signal symmetrically around a reference voltage.

Abstract: An apparatus and method for providing distortion to an input signal. A first alternating current component is separated from the input signal, to provide a first signal representing the first alternating current component and a second signal representing the input signal having the first alternating current component separated therefrom. The signal level of the first and second signals is adjusted. Nonlinear distortion is provided to the signal level adjusted first signal, to produce a distorted first signal. The signal level adjusted second signal is combined with the distorted first signal, to produce a corresponding output signal.

Abstract: An improved output driver that minimizes source point reflections when driving a signal on a transmission line by generating a constant source impedance. The improved output driver uses a transistor switching circuit for generating a nearly constant channel impedance when transistor switching circuit is enabled and is not operating in a saturation mode. A switched diode circuit is coupled in parallel to the transistor switching circuit for generating a nearly constant source impedance when a sufficient voltage to bias the switch diode circuit is applied. Control circuitry is coupled to both the transistor switching circuit and to the switched diode circuit for enabling and disabling the transistor switching circuit and the switched diode circuit. By alternatively enabling and disabling the transistor switching circuit and the switched diode circuit the control circuit is able to generate a constant source impedance.

Abstract: A method and apparatus for detecting pulse data is accomplished by a low voltage data detection circuit that includes a preamplifier circuit, an amplification stage, and a scaling circuit. The preamplifier circuit has a differential input, a predefined gain, and a maximum output limit and receives an input signal, which has a wide dynamic range. The preamplifier circuit amplifies the input signal based on the predefined gain to produce a preamplified data signal. The preamplified data signal is again amplified by the amplification stage and subsequently provided to the scaling circuit which scales the amplified data signal to a predetermined level. The resulting scaled data signal maintains the pulse width fidelity of the input data signal.

Abstract: An apparatus and method for automatically and periodically tuning a signal having a gain element, a variable impedance associated with the gain element, and a control device. The gain element has an input for receiving the signal and an output for providing an output signal and is preferably an operational amplifier with a feedback path extending from the output to the input. The variable impedance is preferably connected in series in the feedback path and includes a plurality of resistors connected in series and a plurality of switches, each switch being connected in parallel with one of the resistors. The control device receives the gain element output signal and generates a control signal in response to the amplitude of the gain element output signal. The control signal is transmitted to the variable impedance for regulating the setting of the impedance.

Abstract: The present invention provides a method and apparatus for improving immunity to common mode noise. The present invention prevents common mode noise from exceeding acceptable limits. The present invention is also useful to prevent common mode noise from being converted to differential mode noise by the action of parasitic diodes. One embodiment of the present invention bleeds charge off two differential lines such that the relative voltage differential is maintained, for example during a memory read, until at least one of the lines is low enough that the maximum possible upward noise (common+differential) is insufficient to turn on the parasitic diodes coupled to the positive voltage supply, leaving enough margin on the differential signal to allow a sensing circuit to accurately sense the differential signal.

Abstract: A method and device for driving signals over a capacitive bus is provided. The device comprises at least one input line selectively activatable for receiving an input signal having a first voltage level. A drive capacitor is positioned in series with and between each of the input lines and the capacitive bus to be driven. The drive capacitor and a capacitance of the capacitive bus forms a capacitive divider network which reduces the input signal to render an intermediate signal having a second voltage level less than the first voltage level. Each of the drive capacitors is also provided with a pre-charge input for receiving a pre-charge voltage signal when its corresponding input line is not selectively activated. At least one amplifier is provided for amplifying the intermediate signal to produce an output signal on an output line having a third voltage level which is approximately the same as the first voltage level.

Abstract: A semiconductor device is arranged by a push-pull circuit 1 for shifting a first center potential of an amplitude of an input signal to a second center potential, and for outputting first and seconc complimentary signals P1, P2 having said second center potential, and further a bipolar type differential amplifier 2 for receiving the first and second complementary signals as input signals thereof.

Abstract: A variable attenuator is provided with a plurality of amplifiers each comprising an emitter grounded or common source amplifier circuit. The amplifiers have different emitter degeneration impedances. One of the amplifiers is selected in accordance with a gain control signal under control of a current switch controller. The selected amplifier is connected to a current source and supplied with an operating current, and thus the selected amplifier is set in an operating state. The other amplifiers are not supplied with an operating current and thus do not operate. The gain of the variable attenuator is determined by a ratio between the emitter degeneration impedance of the selected amplifier and a load impedance.

Abstract: Disclosed is a variable gain semiconductor circuit enjoying a low insertion loss, good distortion characteristic, and large variable gain range. The variable gain semiconductor circuit comprises: a first kind of variable gain circuit that inputs an input signal and changes a gain on the basis of a first control signal; a second kind of variable gain circuit, installed in a stage succeeding the first kind of variable gain circuit, for changing a gain on the basis of a second control signal; and a control signal producing unit for producing the first and second control signals using an attenuation value control signal. When the attenuation value control signal falls within one of two variation ranges instructing a large gain, the control signal producing unit produces the first and second control signals so that the first kind of variable gain circuit decreases a gain according to the variation of the attenuation value control signal, and the second kind of variable gain circuit produces a constant gain.

Abstract: A charge pump having an output diode with a zero voltage drop. The present charge pump may be a multiple stage charge pump that may operate more efficiently than prior charge pumps by substantially removing the voltage drop across the output diode. The last stage in the charge pump receives a second input clock signal. The output diode includes a switch device coupled to a bootstrapping circuit which receives a third input clock signal and a fourth input clock signal. The third input clock signal and the fourth input clock signal are either non-overlapping high clock signals or non-overlapping low clock signals. A specified relationship between the second clock signal and the third clock signal, and a specified relationship between the third clock signal and the fourth clock signal are required to allow the bootstrapping circuit to properly augment the voltage passed through the switch device in the output diode.

Abstract: An equivalent variable resistor circuit for use in an integrated circuit includes a signal path extending from a signal input terminal through a first resistor to a signal output terminal, a first transistor having its collector connected with a signal output portion of the signal path between the first resistor and the signal output terminal, a second transistor having its collector connected with a DC voltage source and its emitter connected with an emitter of the first transistor for forming a differential pair with the first transistor, a third transistor having its collector connected with the emitters of the first and second transistors connected with each other and its emitter connected through a second resistor to a reference potential point to form a voltage to current converting portion with the second resistor, and a voltage controlling portion provided for varying a DC voltage supplied between bases of the first and second transistors, so as to vary equivalently a resistance of the signal path bet

Abstract: A level shift circuit includes a plurality of diodes connected in tandem in a forward direction, a normally-ON transistor connected between a high-potential power line and a node of a highest potential side among the plurality of diodes connected in tandem, and a first pull-down circuit connected between a node of a lowest potential side among the plurality of diodes connected in tandem and a low-potential power line. The level shift circuit further includes a second pull-down circuit connected between a node among the plurality of diodes and the low-potential power line. An input voltage is applied to a control electrode of the normally-ON transistor, and an output voltage is taken from the node of the lowest potential side among the plurality of diodes. By the constitution, the magnitude of a level shift can remain constant relative to a wide range of input voltages. Eventually, a linear input/output characteristic can be obtained.

Abstract: In a voltage-limiting circuit, the voltage to be limited is applied to the terminals of a resistive line, and the current flowing in this line is amplified by a current mirror that thus produces a reference current. A current-controlled voltage source receives this reference current and produces a reference voltage. This reference voltage is given to a hysteresis comparator that switches over for two distinct values of the voltage to be regulated. The disclosed device is particularly useful in the field of the load pumps used in electrically programmable memories.

Abstract: An ASIC (5) has four driver circuits (19a-19d), each with different output power. One of those driver circuits is selected from the content of register (13) on the ASIC. The register content being decoded by a decoder (15) on the ASIC to a signal which activates a single one of the drivers. The register is loaded from an external microprocessor during each initialization of a printer (1) in which the ASIC is a component. The ASIC is designed with the range of the powers of the drivers bracketing the estimated needs of the load to be attached to the ASIC. This permits the ASIC to be completed only once, while the most suitable driver for the final load is determined subsequently and selected by the entry of data to activate that driver into the register with each initialization of the printer. The ASIC need not have nonvolatile memory and only a single set of ASIC masks and other design aspects need be completed.

Abstract: Disclosed are method and apparatus for producing electric waveform driver signals for exciting acoustic emitters such as foghorns, wherein the frequency and amplitude of the signals are readily variable to match the input requirements of the respective drivers of the acoustic devices. In disclosed embodiments of a signal generator according to the present invention a coupling circuit outputs the driver signal through an array of field-effect transistors.

Abstract: A voltage-to-current converter for use with a bandgap voltage reference circuit for providing a correction current to compensate for the adverse effects of temperature. In one specific embodiment, the voltage-to-current converter is used to provide output voltage curvature correction to the resident bandgap voltage reference circuit.

Abstract: An electronic circuit having a circuit stage, such as a switched capacitor stage or a 1-bit digital-to-analog converter and switched capacitor filter, that is loaded with a load impedance employs current feedforward to substantially cancel effects of the load impedance. A circuit includes a circuit stage and a load impedance following and connected to the circuit stage. A current feedforward circuit is connected to the load impedance, substantially cancelling the load impedance to improve linearity of the digital-to-analog converter or switched capacitor filter.

Abstract: A phase generator circuit cyclically produces a first pair of phase signals and a second pair of phase signals, comprising a first circuit to produce a first phase of each pair of phase signals, these first phase signals being non-overlapping and switching over between a voltage 0 and a voltage VCC, and second and third circuits for the production, from the first phase signals, respectively of the second phase of the first pair and the second phase of the second pair of phase signals, these second phase signals being non-overlapping with the first phase signals and switching over between a negative voltage -V and a voltage VCC. The disclosure finds application in the piloting of charge pump type of negative voltage generator circuit.

Abstract: A charge pump circuit includes a plurality of voltage boost stages that are mutually parallel-connected between a supply line and an output line. Each of the stages includes first and second charge storing devices in each of which a first terminal is connected to a charge/discharge node and a second terminal is connected to a boost node to switch between a first charge state and a second charge state for transferring a charge to the output line. Each stage also includes an inverter with an input node connected to the boost node related to the first charge storing device and an output node which is connected to the boost node related to the second charge storing device. Further, a first charge transfer diode, which is connected between the charge/discharge node related to the first charge storing device and the output line and a second charge transfer diode, which is connected between the charge/discharge node related to the second charge storing device and the output line are also included in each stage.

Abstract: A digitally controlled programmable attenuator maintains tight phase matching between attenuated signals over wide ranges of frequencies and power levels regardless of the selected attenuation level. This is achieved with a multi-tap ladder network that sets a desired tap-to-tap dB step-size, a plurality of unity gain digitally switched voltage-to-voltage buffers that are connected between the respective taps and a common output, and a fixed gain stage that sets the attenuator's overall gain/attenuation. The buffers maintain a high and substantially constant impedance whether turned on or turned off. Phase matching within 0.2.degree. at frequencies up to 300 MHz for 30 dB of gain variation has been realized.

Abstract: Low power, high linearity log-linear control method and apparatus wherein a master log-linear cell generates a control voltage that is buffered and applied to a slave log-linear cell. By breaking this function up into two pieces, the control loop characteristics are isolated from the signal path. Low impedance buffers can be used to drive the slave log-linear cell control ports, independent of the control loop, providing improved gain control range and linearity. This log-linear control is of particular value in applications that require low harmonic distortion and high gain control range in power or pin-constrained applications. Details of the method are disclosed.

Abstract: A level converting circuit for an input clock signal having a relatively low amplitude comprising a level converting circuit for converting the input clock signal to an output clock signal having a relatively high amplitude, the level converting circuit having an input transistor which has a predetermined threshold voltage, and detecting/offsetting circuit for detecting the threshold voltage of the input transistor and adding an offset voltage in response to the detected threshold voltage to the input clock signal and then for providing the offset input clock signal to the level converting circuit. The novel setup performs clock interfacing of a thin-film transistor integrated circuit device represented by an active-matrix liquid crystal display device at a relatively high speed at a low voltage below 3 V for example.

Abstract: A method and apparatus are provided for gain adjustment of a signal. A plurality of comparators compare the signal with a plurality of threshold values. An envelope detector coupled to the comparator includes a peak capture function for detecting the amplitude of the signal and a polarity memory for detecting polarity of the signal. A gain control function for setting a gain correction value is responsive to the peak capture function and the polarity memory. Features of the signal gain adjustment method and apparatus of the invention include an intelligent hold of the gain control over both thermal asperities and null gaps in the signal.

Abstract: An integrated circuit employing quantized feedback is capable of compensating for decay in capacitively-coupled digital signals. In an exemplary embodiment, the integrated circuit includes a quantized feedback receiver connected to a capacitively-coupled integrated circuit input. The capacitively-coupled input produces a decaying signal for corresponding intervals of an input digital signal that are substantially DC voltages. Longer sequences of consecutive data bits of the same logic state in the input signal are represented by a corresponding longer DC voltage signals resulting in a greater decay in the capacitively-coupled signal. The receiver operates by generating a complementary feedback signal which is combined with the capacitively-coupled signal. The feedback signal is generated with a magnitude rate of change that compensates for the decay in the capacitively-coupled signal such that the digital information in the combined signal can be detected substantially without error due to the decay.

Abstract: A low power, low voltage level shifter is provided. The voltage level shifter includes a first switching circuit, and a second switching circuit. The first switching circuit has a first input terminal for receiving a first oscillating signal, and based on the first oscillating signal, switches the output of the first switching circuit between a first voltage level and a second voltage level. The second switching circuit has a second input terminal connected to the output terminal of the first switching circuit. The second switching circuit also has a third input terminal for receiving a second oscillating signal which is out of phase with the first oscillating signal. Based on the input signals received, the second switching circuit generates an output signal that switches between a third voltage level and a fourth voltage level at a selected rate and frequency.

Abstract: An embodiment of the present invention provides a method to reduce a regulated power source voltage spike during operation of a dynamic random access memory by the steps of: providing a voltage spike reducer enabling pulse via a pulse generator circuit responsive to a pulse generator input signal; translating the voltage level of an unregulated power source via a level translation stage during the presence of the voltage spike reducer enabling pulse; amplifying a translated voltage level; and providing a measure of current from the unregulated power supply to the regulated power supply via a current driver stage that is responsive to the amplified translated voltage level translation.

Abstract: A voltage stepup circuit having a plurality of setup circuit units connected in stages between an input voltage node and a stepup voltage node. Each circuit unit comprises at least two first and second MOS transistor T1 and T2. Each of first stepup capacitors is connected between a first clock signal supply node and a first connection node at which the drain and gate of a corresponding one of odd-numbered MOS transistors, of a plurality of MOS transistors connected in series through the plurality of stepup circuit units, are connected together. Each of second stepup capacitors is connected between a second connection node at which the drain and gate of a corresponding one of even-numbered MOS transistors of the plurality of MOS transistors connected together and a second clock signal supply node for supplying said second connection node with a second clock signal whose pulse width does not overlap in time with that of the first clock signal.

Abstract: A charge pump circuit including a number of pull-up stages connected in parallel with one another between a reference potential line and an output line. Each stage includes a capacitor having a first terminal connected to a charging and discharging node, and a second terminal connected to a pull-up node for switching between a first charging operating phase and a second charge transferring operating phase. The charging and discharging node is connected to the supply line via a charging transistor having a control terminal connected to a high-voltage bias node formed by the adjacent stage in the opposite operating phase, for charging the capacitor substantially up to the supply voltage.

Abstract: A technique for high speed transmission of digital signals on a bus line with reduced signal ringing, bounce and bus contention current. The approach uses a multi-partitioned driver design with temporary and steady state parts incorporating internal feedback and delay techniques to control the output slew rate. A built-in function outputs the driving status of the transceiver and allows the output to enter the high impedance status asynchronously.

Abstract: Embodiments of the present invention bias a field effect transistor with only a single voltage source and generally do not have the disadvantages of traditional "floated source" bias techniques. Furthermore, some embodiments of the present invention are capable of automatically compensating for the normal manufacturing variations that often result in the physical characteristics of individual FETs.

Abstract: A semiconductor device having an output circuit includes a first field-effect transistor having a source connected to a line from which a first voltage is inputted, and a second field-effect transistor having a source connected to a drain of the first field-effect transistor, a gate connected to a data line from which a level signal is inputted, and a drain connected to an output terminal to which an output signal is outputted. A control unit controls a voltage at a gate of the first field-effect transistor when the second field-effect transistor is in ON state, so that a voltage at the drain of the second field-effect transistor is equal to a second voltage.

Abstract: A pulse voltage doubler circuit for doubling the voltage of output pulses from a microcomputer or the like operating on a low voltage, the doubled output being used on drive a load connected to the microcomputer. The pulse voltage doubler circuit comprises: an inverter circuit having an input terminal, an output terminal, and a first and a second power terminal; a capacitor interconnecting the first and second power terminals of the inverter circuit; and a diode connected interposingly between the first power terminal and a power source. The input terminal of the inverter circuit is connected to the power source, the second power terminal is supplied with an input signal from the microcomputer, and the output terminal is connected to the load which is illustratively an MOSFET gate.

Abstract: In a voltage-limiting circuit, the voltage to be limited is applied to the terminals of a resistive line, and the current flowing in this line is amplified by a current mirror that thus produces a reference current. A current-controlled voltage source receives this reference current and produces a reference voltage. This reference voltage is given to a hysteresis comparator that switches over for two distinct values of the voltage to be regulated. The disclosed device is particularly useful in the field of the load pumps used in electrically programmable memories.

Abstract: A capacitor type voltage divider circuit is disclosed. The divider has a plurality of reference voltage signals applied from an external source. A plurality of switching sections are provided for switching the reference voltage signals from the source in response to first and second clock signals. A plurality of dividing sections are provided which are each comprised of two capacitors for dividing the voltage signals from the switching section into a predetermined value. With the dividing circuit, precise levels of reference voltage signals are obtained and power consumption is low without an increase in size or lowering of operational speed.

Abstract: The invention relates to charge-pump circuits used for the generation, in an integrated circuit, of an internal supply voltage Vpp which is considerably greater than the external supply voltage Vcc. In a charge pump configuration with capacitors and transistors, certain transistors must be driven by bootstrapped logic signals, i.e., having a logic level which is greater than Vcc in order to overcome the threshold voltage of the transistors. According to the invention, there is an oscillator followed by a phase splitter stage which is in turn followed by a bootstrap amplifier stage. The oscillator is a ring oscillator having a number of logic gates which is as small as possible, preferably only three. A satisfactory frequency stability of the charge pump is thus obtained and therefore its design is made easier and its adaptability to various electronic circuits is improved.

Abstract: The invention relates to charge-pump circuits used for the generation, in an integrated circuit, of an internal supply voltage Vpp which is considerably greater than the external supply voltage Vcc. In a charge pump configuration with capacitors and transistors, certain transistors must be driven by bootstrapped logic signals, i.e., having a logic level which is greater than Vcc in order to overcome the threshold voltage of the transistors. According to the invention, there is an oscillator followed by a phase splitter stage which is in turn followed by a bootstrap amplifier stage. The oscillator is a ring oscillator having a number of logic gates which is as small as possible, preferably only three. A satisfactory frequency stability of the charge pump is thus obtained and therefore its design is made easier and its adaptability to various electronic circuits is improved.

Abstract: In a D.C. restoration circuit for a digital FM radio receiver, in which demodulated signals may be presented at the output of the demodulator as low-level differential signals superimposed on a variable D.C. level, the differential signal paths are capacitively coupled to the inputs of a comparator, and the voltage excursions at these inputs are clamped when the voltage between the inputs exceeds a predetermined value.

Abstract: A direct-current stabilizer includes an n-p-n transistor as a control transistor, and a control terminal to which a control voltage for driving the control transistor is applied. The value of the control voltage is determined so that a voltage applied to the base of the control transistor is not lower than the sum of the emitter voltage and the base-emitter voltage. With this structure, since the control transistor is driven by the control voltage of a value different from that of the input voltage, it is possible to limit the input voltage to a low value, allowing the difference between the input voltage and the output voltage to be minimized. Moreover, it is possible to switch the output of the direct-current stabilizer by connecting to the control terminal a transistor for switching the application of the control voltage to the control terminal between on and off. Furthermore, when the control terminal is connected to the input terminal, the control transistor is driven by the input voltage.

Abstract: A variable slew control for output circuits is disclosed. The slew control circuit automatically adjusts the rate in which voltage on a slew node is driven to a reference voltage, minimizing noise at the output device driver. The variable slew control decreases the slew rate of the slew node during periods when di/dt is at a high level, but allows the voltage on the slew node to drop at faster rates during times when di/dt at the output driver is low.

Abstract: A glitch filter for eliminating noise pulses less than 12 nanoseconds (ns) created by large devices on the SCSI bus and reflections of the 12 ns pulses created by a long SCSI bus cable, as well as noise pulses on the order of 35 ns typically found on a SCSI bus. The glitch filter includes a Schmitt trigger connected to receive the SCSI bus signal along with three filters connected in series with the Schmitt trigger. The first filter removes positive pulses having a pulse width less than 12 ns and provides an inverted output. The second filter removes negative pulses having a pulse width less than 12 ns and provides an inverted output. The third filter removes pulses having a pulse width less than 35 ns and provides the output of the glitch filter.

Abstract: A clamping circuit for clamping a circuit node during an initial circuit powerup interval includes a switching circuit and a switching control circuit. The switching circuit is an N-MOSFET with its drain and source terminals connected to circuit ground and the subject node sought to be clamped, respectively, and its gate terminal connected to the switching control circuit. The switching control circuit includes a number of N-MOSFETs which are interconnected in such a manner as to receive the power supply voltage and generate a switching signal which turns the switching circuit N-MOSFET on during an initial circuit powerup interval to clamp the subject node and then off after the power supply has reached a preselected minimum value. Upon initial circuit powerup, the switching control circuit self-triggers itself to turn the switching circuit on and clamp the subject node at ground potential.

Abstract: An improved bootstrap circuit comprising a booster for boosting a binary signal and outputting the boosted binary signal through its output terminal, a voltage detector for detecting a variation of a supply voltage from a supply voltage source, and an active load for adjusting an output load amount of the booster under control of the voltage detector. According to the present invention, the binary signal is boosted to a voltage level which is stable regardless of the variation of the supply voltage.

Abstract: The turn-off delay time of a low-side driver (output power transistor), may be independently reduced and eventually made identical to the turn-on delay time by employing an auxiliary current generator that may be controlled by the same switching signal that controls a current generator employed for discharging the control node of the low-side driver, in order to provide an augmented discharging current during a first phase (only) of a turn-off process. The contribution to the capacitance discharge current provided by said third current generator is automatically interrupted by means responsive to the voltage present on the driving node of the low-side driver, when it approaches saturation.

Abstract: A drive circuit includes a voltage source supplying a reference voltage at its output; a voltage elevating circuit connected to a supply voltage and to the output of the voltage source, and supplying at its output, under normal operating conditions, a drive voltage greater than the supply voltage and increasing with the reference voltage. The input of the voltage source is connected to the output of the voltage elevating circuit, and defines a positive feedback path resulting in an increase in the reference voltage corresponding to an increase in the drive voltage, and therefore results in a corresponding increase in the drive voltage up to a maximum permissible value, thus providing for a sufficient drive voltage for driving the gate-source junction of power MOS transistors, even in the presence of a low supply voltage.

Abstract: An automatic gain and level control output circuit. The inventive circuit (10) includes a first component (12) for multiplying an input signal by a first reference signal to provide a gain adjusted signal. The input signal is level shifted by a second reference signal by a second component (16) to provide a level adjusted signal. The gain and level adjusted signals are compared to third and fourth reference signals by third and fourth components (26 and 28), respectively. The outputs of the third and fourth components (26 and 28) are combined to provide a first signal. Either the output of the third component (26) or the fourth component (28) is selected to provide a second signal having a first or a second level respectively. The first signal is integrated to provide the first reference signal and the fourth signal is integrated to provide the second reference signal.

Abstract: An integrated circuit charge pump circuit including a plurality of stages, each stage including a first N type field effect switching transistor device having source and drain terminals connected in series with the source and drain terminals of all other stages, a second N type field effect control transistor device having drain and source terminals connecting the drain terminal and the gate terminal of the first switching transistor device, and a storage capacitor joined to the source terminal of the first device; a source of voltage to be pumped is connected to the drain terminal of the first device of the first stage.

Abstract: In an electronic system such as an integrated circuit having a number of destination loads such as logic gates, signal is distributed along typically a zero'th level (e.g., polysilicon) electrical transmission line from an input terminal to the destination loads. The characteristics of the signal arriving at the destination loads are improved by (1) inserting an added electrical transmission line, and (2) connecting various nodes of the added electrical transmission line through auxiliary active devices, such as inverters, to various nodes on the zero'th level electrical transmission line. In one attractive arrangement, each of the auxiliary active devices has an electrical-current-drive capability that increases monotonically with the number of nodes intervening between it and the input terminal of the added electrical transmission line.

Abstract: A differential track and hold amplifier circuit (200) is provided. The track and hold amplifier includes an input transconductance amplifier (212), an output amplifier (111), and a second transconductance amplifier (214). The track and hold circuit further includes a switching circuit (108) for coupling the output of the input transconductance amplifier to a capacitor (110) in the output stage of the track and hold circuit during track mode, and for decoupling the capacitor from the input amplifier during hold mode. The track and hold circuit further includes a subtractor circuit (103) for reducing a common mode voltage of the output of the input transconductance amplifier, thereby maintaining a stable voltage across the capacitor during hold mode. Further, during hold mode, the second transconductance amplifier acts in a negative feedback configuration to reduce the gain of the input amplifier to attenuate its output signal.

Abstract: A level shifter includes an N-channel enhancement-mode field effect transistor (40), a P-channel depletion-mode field effect transistor (38), and a current mirror (42) coupled to the source of the enhancement-mode transistor and the drain of the depletion-mode transistor; wherein the gates of the transistors are coupled to an input terminal and the source of the enhancement-mode FET is coupled to an output terminal to provide a level shifted output signal.