Abstract: The present invention discloses a source driver powered by a power supply comprising at least one channel, at least one output pad coupled to the channel, at least one switch connected between the output pad and a predetermined voltage, and a power down detector for detecting whether a first supply voltage from the power supply is insufficient and generating a reset signal to turn on the switch if yes.

Abstract: The present invention provides an OOB detection circuit capable of making accurate signal determination even in the case where a characteristic fluctuation occurs in an analog circuit, thereby preventing deterioration in the yield of a product. To an amplitude determining circuit, a characteristic adjustment register for changing setting of an amplitude threshold adjustment mechanism for distinguishing a burst and a squelch from each other provided for the amplitude determining circuit is coupled. The characteristic adjustment register is controlled by a self determination circuit. An output of the amplitude determination circuit is supplied to a time determining circuit and also to the self determination circuit. On the basis of the output of the amplitude determining circuit, the self determination circuit controls the characteristic adjustment register.

Abstract: In the existing technique in which the attenuation characteristic of an attenuator is adjusted by a voltage value, there are problems that a scale of a circuit of the attenuator increases because a new circuit for supplying voltage such as a step-down circuit becomes necessary, and that a thermal noise and a shot noise are mixed in an output signal of the attenuator. To solve the above-mentioned problems, provided is an attenuator comprising a T-type two terminal pair network including first and second circuits connected in series, and a third circuit connected in shunt between these first and second circuits. A shunt capacitor is connected between the first and second circuits independent from the third circuit.

Abstract: A system or circuit for simulating a potentiometer, thermistor, or the like. A pulse stream, having a duty cycle which is varied as a changing pulse width or as a differing number of time slices per time period, may be input to the system. The pulse stream to a transistor or switch-like mechanism may allow a controlled connection of a fixed value resistor to a reference voltage or ground to provide various resultant values of impedance or resistance. A measuring circuit connected to the output of the system may determine a value which is of the fixed value resistor divided by the duty cycle of the pulse train effectively controlling the connection of the resistor to ground. One or more additional circuits may be connected in parallel to achieve greater accuracy.

Abstract: A control circuit for diode based RF circuit (6) comprising at least one analog communicating device (2, 3) having a plurality of digital control lines (A0, A1, A2, En1, B0, B1, B2, En2), a plurality of selectable poles (X0-X15) and at one common pole (Y1, Y2), the digital control lines being connected to a digital data generator (4) and the selectable poles and at least one common pole being connected to the control terminal(s) of the diode(s) of the RF circuit through a network of resistors (7-21) of differing values and a potential divider (22) and a power supply or voltage source (25) or a network of potential dividers of differing outputs and a power supply or voltage source, the analog communicating device establishing an internal coupling between the common pole and one of the selectable poles depending upon the digital value generated by the digital data generator and appearing at the digital control.

Abstract: A data receiver includes a plurality of amplifiers for receiving data in response to clock signals having a predetermined phase difference, and amplifying the received data by performing an equalization function based on feedback data, thereby outputting amplification signals, and a plurality of latches for latching output of the amplifiers, respectively. One amplifier receives the amplification signal, as feedback data, from another amplifier receiving a clock signal having a phase more advanced than a phase of a clock signal received in the one amplifier.

Abstract: A source driver eliminates the need for a level shifter and enables the use of a low voltage digital-to-analog converter by using an operational buffer that performs voltage amplification in addition to driving a TFT panel.

Abstract: The EMI-free planar inductor is the core technology of the green technology. The EMI-free planar inductor adopts the structure of the closed magnetic field flux IC inductor (CMFFICI). All the magnetic field being confined in a small volume. The magnetic field is parallel to the surface of the chip. The EMI-free planar inductor makes the on-chip LC tank having very high Q and saves a lot of energy. Combining with the gain-boost-Q technology, it makes the high performance Tales clock chip have the performance being comparable to the xtalchip. The xtalchip is the inductor being replaced with the crystal in the gain-boost Q resonator. Furthermore, the EMI-free planar inductor makes the highest power efficiency boost-buck converter and the on-chip spinning motor. It makes the PC laser TV projector being implementable. The PC laser TV projector is RGB full color for each pixel and having the fast object movement sensitivity and wide dynamic range for the light contrast.

Abstract: A switch circuit includes a pair of metal oxide semiconductor (MOS) switches and an adjusting unit. Each of the MOS switches has an input terminal and an output terminal. The MOS switches receive a pair of differential input voltages at the input terminals thereof, and output a pair of differential output voltages at the output terminals thereof when the MOS switches conduct. The adjusting unit changes a difference between common mode levels of the input terminals and the output terminals of the MOS switches so as to adjust linearity of differential mode resistances of the MOS switches.

Abstract: The electronic circuit (1) for measuring at least one physical parameter supplies an analogue output measurement signal (SA) dependent upon the value of a supply voltage. The circuit includes a sensor interface (2) connected to a sensor (C) for supplying an analogue measurement signal (Vm) which is then filtered. The circuit further includes an analogue-digital converter (8) for digitally converting the filtered signal (Sm), a digital signal control and processing unit (9) for receiving a converted signal from the converter, and supplying a digital measurement signal (SD). The sensor interface, the analogue-digital converter and the processing unit (9) are powered by a regulated voltage supplied by a voltage regulator (4). The analogue and digital measurement signals are thus independent of any variation in the supply voltage (VCC) of the electronic unit.

Abstract: A differential pair circuit includes a first transistor having a first control terminal, a first input terminal, and a first output terminal; a second transistor having a second control terminal, a second input terminal, and a second output terminal, a first buffer stage including a third transistor having a third control terminal, a third input terminal, and a third output terminal; and a second buffer stage including a fourth transistor having a fourth control terminal, a fourth input terminal, and a fourth output terminal. The first output terminal and the second output terminal are electrically connected; the third output terminal and the first control terminal are electrically connected; the fourth output terminal and the second control terminal are electrically connected; the first input terminal and the fourth input terminal are electrically connected; and the second input terminal and the third input terminal are electrically connected.

Abstract: A calibration circuit for calibrating an adjustable capacitance of a circuit having a time constant depending on the adjustable capacitance, the calibration circuit generating a calibration signal for calibrating the capacitance and including a calibration loop, suitable to carry out a calibration cycle in several sequential steps.

Abstract: In an electronic high-frequency switch, comprising a field-effect transistor as the switching element, the size of the gate voltage may be switched between at least two values (?5.5 V and ?8 V), according to the desired linearity or switching speed. The switching device for the gate voltage is preferably coupled to a correction device in which different correcting values for the different gate voltage values corresponding to different correcting values for transmission or reflection by the high frequency switch are stored.

Abstract: The invention relates to a method for adjusting a pulse detection threshold consisting in detecting a pulse when the edge of said pulse envelop crosses the threshold, in allocating (A) a staring value (TH0) to the threshold and in adjusting (B1) the threshold (TH) in such a way that the number of pulses detected on at least one observation window (OWj) satisfies a predetermined criterion in a determined time.

Abstract: Disclosed is a reference voltage generating circuit which includes resistors R0, R0 and R3, a differential amplifier A1 and transistors Q1, Q2 and Q3. The collectors of the transistors Q1 and Q2 are connected to differential input terminals of the differential amplifier, while one ends of the R0, R0 and R3 are connected in common to an output of the differential amplifier A1. The other ends of the two resistors R0 are connected in common to the collectors of the transistors Q1 and Q2, while the other end of the resistor R1 is connected to the collector and the base of the transistor Q3, which transistor Q3 has the base connected to the bases of the transistors Q1 and Q2. The emitter size ratio of the transistors Q1 and Q2 is set to 1:N. A current of a value approximately equal to that of the collector current of the transistor Q1 or Q2 and a current with a positive temperature coefficient larger than the first-stated current are caused to flow through the resistor R1.

Abstract: It permits switching signals with a peak level equal to the source voltage by means of a transistor, the peak to peak level being double the source. It is characterized by the connection of a transistor (17) to the signal source (10) and a load (19) by means of a series of capacitors (11, 18), resistors (15, 16) and an inductor (12) that form the circuit of the invention, and by the application of two complementary control voltages (13 and 14) in order to control the off and on states of the switch circuit.

Abstract: A reference voltage selection circuit includes a first switch element SW1 that outputs a first selection voltage among first to third selection voltages as a first reference voltage among first and second reference voltages, a second switch element SW2 that outputs the second selection voltage as the first reference voltage, a third switch element SW3 that outputs the second selection voltage as the second reference voltage, and a fourth switch element SW4 that outputs the third selection voltage as the second reference voltage. The first to fourth switch elements SW1 to SW4 are ON/OFF-controlled using gamma correction data that contains at least three bits. When the first selection voltage is a ground power supply voltage, reliability can be improved by protecting the first switch element.

Abstract: The invention relates to an integrated circuit (1) which comprises a novel bidirectional mixed signal single-wire interface (6) via which the circuit receives command information from a host and transmits conditioned analog signals to the host. In order to implement the mixed signal interface, the integrated circuit is provided with means for analog signal conditioning (2), command detection (3), and digital control (4). In a preferred embodiment of the invention, current detectors are used for command detection and respond to the current flowing through the interface connection (6) so that commands can be given even when analog signals are present on the bus. The invention relates to several methods of operation, especially methods for operating a plurality of the integrated circuits on the same mixed signal bus, and methods for the compatible operation with conventional integrated circuits.

Abstract: The invention relates to a digital acquisition device for an amplitude modulation signal of a carrier. The acquisition device digitally acquires a useful signal. The useful signal modulates the amplitude of a carrier HF1 which has a frequency and a phase that are known. A modulation of the amplitude of the carrier by the useful signals forms a signal to be processed. According to the invention, the device has a summing device for creating an aggregate signal from a sum of the signal to be processed and a neutralizing signal. The neutralizing signal is a product of the carrier HF1 and of a neutralizing coefficient that can evolve over time, produced by a controlled-gain amplifier device. A load amplifier device amplifies the aggregate signal and produces an amplified aggregate signal. A quadrant comparison device QC is provided for the signal of the amplified aggregate signal and the sign of the carrier which delivers a comparison signal. A sampling device produces a bitstream from the comparison signal.

Abstract: Various apparatuses, methods and systems for a multi-mode DAC with selectable output range, granularity and offset and controlled slew rate are disclosed herein. For example, some embodiments of the present invention provide an apparatus for supplying a reference signal, including a digital-to-analog converter, a counter and a clock. The digital-to-analog converter has a digital input and an analog output that supplies a reference signal based on the digital input. The counter has a digital control word input, a clock input, a clock enable output and a count output connected to the digital input of the digital-to-analog converter. The counter is adapted to assert the clock enable output when the digital control word input requests an output count that is different from an actual count at the count output of the counter. The clock has an enable input connected to the clock enable output of the counter and a clock output connected to the clock input of the counter.

Abstract: A voltage level shifting circuit (5) for shifting the common mode voltage of a differential signal to be within the working range of a differential input buffer circuit (3) comprises a first resistive voltage divider circuit (18) coupled between a first input terminal (10) and a voltage reference terminal (15) for receiving a voltage reference to which the common mode voltage of the level shifted differential signal is to be referenced, and a second resistive voltage divider circuit (18) coupled between a second input terminal (11) and the voltage reference terminal (15). The differential signal is applied to the first and second terminals (10,11), and the level shifted differential signal is produced on first and second output taps (17,19) of the first and second resistive voltage divider circuits (16,18) with the common mode of the level shifted differential signal referenced to the voltage reference applied to the voltage reference terminal (15).

Abstract: A high frequency part, which amplifies a high frequency signal outputted from an intermediate frequency part and supplies to an antenna, is equipped with a gain controller with switch function. The gain controller with switch function comprises an attenuator with switch function has a function of switching a selected band between two bands outputted from the intermediate frequency part and controlling the gain of the high frequency signal in the selected band. The attenuator with switch function comprises a first variable resistor which connects a signal input part with a signal output part and a second variable resistor which is disposed parallel to said first variable resistor and connects a signal input part with a signal output part. The first and the second variable resistors are controlled by a common gain control voltage and set such that the gain control voltage ranges, which are for changing the resistor values, will not overlap with each other.

Abstract: A signal conversion circuit 2 comprises a differential amplifier portion 10 and a source follower portion 20. When differential voltage signals INp and INn are input to a first input terminal 5 and second input terminal 6 respectively, operations occurs either in a mode in which only the differential amplifier portion 10 operates, or a mode in which both the differential amplifier portion 10 and the source follower portion 20 operate, or a mode in which only the source follower portion 20 operates, according to the levels of the differential voltage signals INp and INn. The differential amplifier portion 10 and source follower portion 20 have fewer components compared with a circuit comprising two differential amplifier circuits. By this means, the circuit area can be reduced, and in addition current consumption can be reduced. Also, because the source follower portion 20 performs non-inverting amplification of the differential voltage signals INp and INn, high-speed operation is possible.

Abstract: A method of determining the speed of a spinning sensorless brushless motor driven by an inverter when the phase terminals of the motor are shorted including determining a voltage related to the voltage developed in a phase leg of the inverter; from the determined voltage, determining the direction of current and providing a first signal determining transitions between current flowing in each of two directions; and from the first signal, determining the frequency of the current and thus the motor speed.

Abstract: A digital interface system that includes a first circuit that transmits a set of voltage levels and a second circuit that receives the set of voltage levels and generates a set of voltage differential levels based on the set of voltage levels. The set of voltage differential levels corresponds to a first predetermined value. Each of the voltage levels is different from another of the voltage levels.

Abstract: A high sensitivity, three-dimensional gamma ray detection and imaging system is provided. The system uses the Compton double scatter technique with recoil electron tracking. The system preferably includes two detector subassemblies; a silicon microstrip hodoscope and a calorimeter. In this system the incoming photon Compton scatters in the hodoscope. The second scatter layer is the calorimeter where the scattered gamma ray is totally absorbed. The recoil electron in the hodoscope is tracked through several detector planes until it stops. The x and y position signals from the first two planes of the electron track determine the direction of the recoil electron while the energy loss from all planes determines the energy of the recoil electron.

Abstract: A power supply device capable of suitably reducing a loss even in a case where power is supplied to an output device which outputs a high-frequency signal, a signal output apparatus in which a loss is suitably reduced, and a power supply method capable of suitably reducing a loss. The power supply device has a power supply section which supplies a power supply voltage to an output device which is supplied with the power supply voltage and outputs an output signal, and a voltage control section which controls the power supply section so that the power supply voltage follows the envelope of the output signal from the output device.

Abstract: A reference clock receiver structure according to the invention is provided. The structure preferably includes an input buffer that is formed from a PMOS differentiated pair of transistors and a first supply voltage. The PMOS differential pair receives a pair of differential inputs, and produces a pair of differential outputs. The structure also includes a level shifter that is coupled to receive the pair of differential outputs from the input buffer to provide gain to the pair of differential outputs to form a gained pair of differential outputs. The level shifter that includes a second supply voltage. The second supply voltage may have a smaller magnitude than the first supply voltage. Finally, the structure includes a CMOS buffer that is coupled to receive the gained pair of differential outputs. The CMOS buffer boosts the gained pair of differential outputs and converts the gained differential pair outputs into a single signal.

Abstract: A semiconductor device receives differential input signals, performs predetermined signal processing, and outputs differential output signals. Plural rear surface electrodes, disposed in an m-row, n-column (m and n being integers) matrix form, on a rear surface of the semiconductor device, are formed. The rear surface electrodes for the differential input signals or differential output signals are disposed in rows, 1, 2, m?1, and m, or in columns, 1, 2, n?1, and n, of a matrix. Furthermore, a pair of rear surface electrodes for differential input signals that for a pair, and a pair of rear surface electrodes PAD for differential output signals that form a pair, are respectively disposed so as to be adjacent.

Abstract: A signal amplification device which uses inexpensive standard CMOS and yet is capable of high-accuracy threshold setting. An offset voltage generator detects the direct-current level of an input signal, and generates a positive or negative offset voltage signal. A peak detector outputs, as a peak value, the positive offset voltage signal if the level thereof is higher than the maximum level of the input signal, or the maximum level of the input signal if the maximum level is higher than the positive offset voltage signal. A bottom detector outputs, as a bottom value, the negative offset voltage signal if the level thereof is lower than the minimum level of the input signal, or the minimum level of the input signal if the minimum level is lower than the negative offset voltage signal. A voltage divider subjects the peak and bottom values to voltage division, to generate a threshold level.

Abstract: Disclosed is a semiconductor circuit in which a floating node is set to any voltage by utilizing a control signal which is applied to a refresh terminal and has a period shorter than that of a clock signal. The semiconductor circuit includes first and second transistors connected between a first clock terminal and a first power supply terminal, third and fourth transistors connected between the refresh terminal and the first power supply terminal, and fifth and sixth transistors connected between a second power supply terminal and the first power supply. Gates of the fourth and fifth transistors are connected in common to an input terminal, a gate of the third transistor is connected to a second clock terminal, a gate of the first transistor is connected to a connection node between the fifth and sixth transistors, the gate of the second transistor is connected to the gate of the sixth transistor, and a connection node between the first and second transistors is connected to an output terminal.

Abstract: An optical spike is generated at an arbitrarily selected location within an arbitrary optical link. The optical spike is generated by deriving a spike signal having a plurality of components, and launching the spike signal into the a transmitter end of the optical link. An initial phase relationship between the components is selected such that the involved signal components will be phase aligned at the selected location. In order to achieve this operation, the initial phase relationship between the components may be selected to offset dispersion induced phase changes between the transmitter end of the link and the selected location. One or more optical spikes can be generated at respective arbitrarily selected locations within the link, and may be used for performance monitoring, system control, or other purposes.

Abstract: A semiconductor device includes a differential level converter circuit that receives a first signal and outputs a second signal of greater amplitude. The differential level converter has a first MISFET pair for receiving the first signal, a second MISFET pair for enhancing the withstand voltage of the first MISFET pair, and a third MISFET pair with cross-coupled gates for latching the second signal from output. The film thickness of the gate insulating films of the second and third MISFET pairs is made thicker than that of the first MISFET pair, and the threshold voltages of the first and second MISFET pairs are made smaller than that of the third MISFET pair. This level converter circuit operates at high speed even if there is a large difference in the signal amplitude before and after level conversion.

Abstract: Many bit-ization also offers the semiconductor device which suppresses increase of chip size. Part voltage of the voltage produced between potential VH and potential VL is carried out, high electric strength digital to analog converter 1 in which an output of either of plural potentials 3-9 produced with part voltage based on the input signal (D0-DN-1) is possible, plural elements 11 and 13, output elements 15, it has level shift part 17 which carries out the level shift of the potential of an input signal to potential required in order that output elements 15, plural elements 11, and each of 13 may operate, and impresses it to it. grouping of plural potentials 3-9 is carried out to the order of a potential level at plurality, the voltage between the potentials of the group which provides and corresponds corresponding to each group is applied, and each of plural elements 11 and 13 operates.

Abstract: A reference clock receiver structure according to the invention is provided. The structure preferably includes an input buffer that is formed from a PMOS differentiated pair of transistors and a first supply voltage. The PMOS differential pair receives a pair of differential inputs, and produces a pair of differential outputs. The structure also includes a level shifter that is coupled to receive the pair of differential outputs from the input buffer to provide gain to the pair of differential outputs to form a gained pair of differential outputs. The level shifter that includes a second supply voltage. The second supply voltage may have a smaller magnitude than the first supply voltage. Finally, the structure includes a CMOS buffer that is coupled to receive the gained pair of differential outputs. The CMOS buffer boosts the gained pair of differential outputs and converts the gained differential pair outputs into a single signal.

Abstract: A level-determining device of pulse width modulation (PWM) signal includes a PWM signal generating circuit, a reference voltage generating circuit and a determining circuit. The PWM signal generating circuit generates a first PWM signal. The reference voltage generating circuit generates a reference voltage signal. The determining circuit is respectively electrically connected to the PWM signal generating circuit and the reference voltage generating circuit for determining high level or low level of the first PWM signal in accordance with the reference voltage signal for generating a second PWM signal.

Abstract: A low-power consumption level shifter circuit is provided by preventing a through current which is generated when a level of a signal is changed. In order to prevent a through current which flows when a level of a signal of the input is changed, the p-channel TFTs are controlled so that the p-channel TFTs and the n-channel TFT or the p-channel TFTs and the n-channel TFT are not turned on at once. A high level signal is inputted to the gate of the n-channel TFT, and at the moment when the n-channel TFT is turned on, the p-channel TFT is turned off. Similarly, at the moment when the n-channel TFT is turned on, the p-channel TFT is turned off. The p-channel TFTs and the n-channel TFT, or the p-channel TFTs and the n-channel TFT are not turned on at once, thereby a path in which the through current flows is cut off.

Abstract: An amplitude adjusting circuit comprises a first current mirror where a variable current of a variable current source is copied into each of 1st-3rd transistors; a second current mirror where the variable current is copied into each of 11th-13th transistors; a third current mirror having 6th-7th transistors where a current through the 2nd transistor copied from the variable current flows through the 6th transistor; a fourth current mirror having 8th-9th transistors where a current through the 12th transistor copied from the variable current flows through the 8th transistor; an inverter that has 1st-2nd conductivity type transistors and produces an output signal corresponding to a current level of the 7th or 9th transistor; a fifth current mirror having 15th-14th transistors where a current through the 14th transistor copied from the 15th transistor's becomes a current sourced by the 7th transistor; and a sixth current mirror having 5th-4th transistors where a current through the 4th transistor copied from the

Abstract: A high frequency part, which amplifies a high frequency signal outputted from an intermediate frequency part and supplies to an antenna, is equipped with a gain controller with switch function. The gain controller with switch function comprises an attenuator with switch function has a function of switching a selected band between two bands outputted from the intermediate frequency part and controlling the gain of the high frequency signal in the selected band. The attenuator with switch function comprises a first variable resistor which connects a signal input part with a signal output part and a second variable resistor which is disposed parallel to said first variable resistor and connects a signal input part with a signal output part. The first and the second variable resistors are controlled by a common gain control voltage and set such that the gain control voltage ranges, which are for changing the resistor values, will not overlap with each other.

Abstract: Provided are: at least one or more series variable resistors implemented by field effect transistors connected to a signal line A; and at least one or more shunt variable resistors implemented by field effect transistors connected between a signal outputting section A and a reference potential section GND. Further provided are: at least one or more series variable resistors implemented by field effect transistors connected to a signal line B arranged in parallel to the signal line A; and at least one or more shunt variable resistors implemented by field effect transistors connected between a signal outputting section B and a reference potential section GND.

Abstract: A circuit for providing a base operating voltage for a bipolar transistor includes a UBE multiplier providing, in response to a working-point control current, a working voltage fed to a circuit for reducing the working voltage in order to generate a base operating voltage smaller than a base-emitter voltage drop of a bipolar power transistor. With this, the bipolar power transistor may be maintained in the class C operation in a flexible and robust manner, so that an amplifier with high efficiency is obtained.

Abstract: There is provided an amplitude varying driver circuit operable to output an output signal, which is an amplified input signal being supplied. The amplitude varying driver circuit includes: a plurality of differential amplifiers provided in parallel with one another, wherein a signal corresponding to the input signal is input into each base terminal thereof; a resistor section, which is provided in series with the plurality of differential amplifiers, operable to establish potential of the output signal according to total current flowing to the plurality of differential amplifiers; and an amplitude control transistor, which is provided in series with the plurality of differential amplifiers, operable to define total current flowing to the plurality of differential amplifiers.

Abstract: A system for communicating information includes a variable gain amplifier (VGA) responsive to an input signal and a gain control signal for controlling a gain of the VGA. The system also includes a power amplifier responsive to the VGA. An output power level of the power amplifier is compared to a predetermined reference value to generate the gain control signal. The gain control signal is offset by a gain offset value. To change the output power level of the power amplifier from a first output power level to a second output power level, a first predetermined reference value and a first gain offset value associated with the first output power level are changed substantially concurrently to a second predetermined reference value and a second gain offset value, respectively, associated with the second output power level.

Abstract: A level shift circuit includes first and second inverters and an inversion circuit. The first inverter has a first input terminal and a first output terminal for generating the output signal. The first inverter includes a first transistor having a first current driving capacity. The second inverter has a second input terminal connected to the first output terminal and a second output terminal connected to the first input terminal. The second inverter includes a second transistor having a second current driving capacity smaller than the first capacity. The inversion circuit has an output terminal connected to the first input terminal. The inversion circuit receives an input signal including a first input signal and a second input signal one of which is a one-shot pulse signal. The inversion circuit includes a third transistor having a third current driving capacity smaller than the first capacity and larger than the second capacity.

Abstract: A differential circuit and an amplifier circuit for reducing an amplitude difference deviation, performing a full-range drive, and consuming less power are disclosed. The circuit includes a first pair of p-type transistors and a second pair of n-type transistors. A first current source and a first switch are connected in parallel between the sources of the first pair of transistors, which are tied together, and a power supply VDD. A second current source and a second switch are connected in parallel between the sources of the second pair of transistors, which are tied together, and a power supply VSS. The circuit further includes connection changeover means that performs the changeover of first and second pairs between a differential pair that receives differential input voltages and a current mirror pair that is the load of the differential pair. When one of the two pairs is the differential pair, the other is the current mirror pair.

Abstract: A booster includes a boosting circuit and a feedback control circuit. The boosting circuit is used to boost an input voltage into a predetermined output voltage; the feedback control circuit detects the output voltage of the boosting circuit and stops boosting the voltage when the output voltage is higher than a predetermined value so as to prevent additional power consumption of a battery and increase transferring efficiency.

Abstract: A circuit for converting an input signal at a first voltage level to an output signal at a second voltage level uses only thin oxide transistors. The circuit includes a first unit operating at a first power supply voltage and receiving the input signal, a second unit operating at a second power supply voltage, and a third unit coupling the first unit to the second unit. The third unit enables generation of the output signal. Use of an extra fabrication mask for thick oxide transistors is avoided by using only thin oxide transistors.

Abstract: A positive charge of a sensor element is charged in a signal converting circuit, is converted into a positive voltage, and is outputted. When the polarity of the charge of the sensor element is inverted to the negative and an output of the signal converting circuit is decreased, the leaked charges are superimposed and become the negative. An automatic correction circuit detects the negative output and discharges the charges so as to set the input to “0”. Thus, the offset of the signal level due to the charge leakage is automatically corrected.

Abstract: An amplifier system containing a polynomial predistorer and a polynominal predistorter configured for use with an RF power amplifier, the polynomial predistorter having a polynomial generator configured to receive an RF input signal and generate a predistortion function based thereon, and a combiner circuit also configured to receive the RF input signal and coupled to the polynomial generator and configured to combine the RF input signal with the predistortion function to form a predistorted input signal, the predistorted input signal operable to improve the adjacent channel power and/or the error vector magnitude performance of the RF power amplifier.

Abstract: A method and apparatus is provided for detecting the output power of an RF power amplifier for purposes of controlling the output power. A circuit for generating an output power control signal includes a power detector to detect the output power of an RF power amplifier. A variable gain amplifier is coupled to the power detector for amplifying the output of the power detector. The value of the generated control signal is a function of the gain of the variable gain amplifier.